Commit 414355a7 authored by Damien Lespiau's avatar Damien Lespiau Committed by Jani Nikula

drm/i915/skl: Don't warn if reading back DPLL0 is disabled

We can operate with DPLL0 off with CDCLK backed by the 24Mhz reference
clock, and that's a supported configuration. Don't warn when notice
DPLL0 is off then.

We still have a separate warn at boot if cdclk is disabled (because we
don't currently try to handle the case (that shouldn't happen on SKL as
far as I know) where we boot with display not initialized.
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent a9419e84
...@@ -6737,10 +6737,8 @@ static int skylake_get_display_clock_speed(struct drm_device *dev) ...@@ -6737,10 +6737,8 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
uint32_t cdctl = I915_READ(CDCLK_CTL); uint32_t cdctl = I915_READ(CDCLK_CTL);
uint32_t linkrate; uint32_t linkrate;
if (!(lcpll1 & LCPLL_PLL_ENABLE)) { if (!(lcpll1 & LCPLL_PLL_ENABLE))
WARN(1, "LCPLL1 not enabled\n");
return 24000; /* 24MHz is the cd freq with NSSC ref */ return 24000; /* 24MHz is the cd freq with NSSC ref */
}
if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
return 540000; return 540000;
......
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