Commit 41a8a7ee authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller

tg3: Fix read DMA FIFO overruns on recent devices

Earlier versions of tg3 devices had a problem where the read DMA FIFO
could be overrun in certain edge conditions.  The fix was to limit the
number of rx BDs the hardware would fetch at a time.  For later devices
(5761, 5784 and later ASIC revs), there is a hardware fix that must be
enabled to fix the same problem.  This patch adds that hardware fix.

There is a gap in the ASIC revision lineage where neither fix is
applied.  This is intentional as these ASIC revisions are not afflicted
by the bug.
Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Reviewed-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 21a45917
...@@ -8015,6 +8015,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) ...@@ -8015,6 +8015,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
val = tr32(TG3_RDMA_RSRVCTRL_REG);
tw32(TG3_RDMA_RSRVCTRL_REG,
val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
}
/* Receive/send statistics. */ /* Receive/send statistics. */
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
val = tr32(RCVLPC_STATS_ENABLE); val = tr32(RCVLPC_STATS_ENABLE);
......
...@@ -1302,7 +1302,11 @@ ...@@ -1302,7 +1302,11 @@
#define RDMAC_STATUS_FIFOURUN 0x00000080 #define RDMAC_STATUS_FIFOURUN 0x00000080
#define RDMAC_STATUS_FIFOOREAD 0x00000100 #define RDMAC_STATUS_FIFOOREAD 0x00000100
#define RDMAC_STATUS_LNGREAD 0x00000200 #define RDMAC_STATUS_LNGREAD 0x00000200
/* 0x4808 --> 0x4c00 unused */ /* 0x4808 --> 0x4900 unused */
#define TG3_RDMA_RSRVCTRL_REG 0x00004900
#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
/* 0x4904 --> 0x4c00 unused */
/* Write DMA control registers */ /* Write DMA control registers */
#define WDMAC_MODE 0x00004c00 #define WDMAC_MODE 0x00004c00
......
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