Commit 42047699 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

USB: mct_u232.h: checkpatch cleanups

Minor whitespace cleanups to make checkpatch happy.
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 7f1cccd3
......@@ -42,34 +42,42 @@
#define MCT_U232_SET_REQUEST_TYPE 0x40
#define MCT_U232_GET_REQUEST_TYPE 0xc0
#define MCT_U232_GET_MODEM_STAT_REQUEST 2 /* Get Modem Status Register (MSR) */
/* Get Modem Status Register (MSR) */
#define MCT_U232_GET_MODEM_STAT_REQUEST 2
#define MCT_U232_GET_MODEM_STAT_SIZE 1
#define MCT_U232_GET_LINE_CTRL_REQUEST 6 /* Get Line Control Register (LCR) */
#define MCT_U232_GET_LINE_CTRL_SIZE 1 /* ... not used by this driver */
/* Get Line Control Register (LCR) */
/* ... not used by this driver */
#define MCT_U232_GET_LINE_CTRL_REQUEST 6
#define MCT_U232_GET_LINE_CTRL_SIZE 1
#define MCT_U232_SET_BAUD_RATE_REQUEST 5 /* Set Baud Rate Divisor */
/* Set Baud Rate Divisor */
#define MCT_U232_SET_BAUD_RATE_REQUEST 5
#define MCT_U232_SET_BAUD_RATE_SIZE 4
#define MCT_U232_SET_LINE_CTRL_REQUEST 7 /* Set Line Control Register (LCR) */
/* Set Line Control Register (LCR) */
#define MCT_U232_SET_LINE_CTRL_REQUEST 7
#define MCT_U232_SET_LINE_CTRL_SIZE 1
#define MCT_U232_SET_MODEM_CTRL_REQUEST 10 /* Set Modem Control Register (MCR) */
/* Set Modem Control Register (MCR) */
#define MCT_U232_SET_MODEM_CTRL_REQUEST 10
#define MCT_U232_SET_MODEM_CTRL_SIZE 1
/* This USB device request code is not well understood. It is transmitted by
the MCT-supplied Windows driver whenever the baud rate changes.
*/
/*
* This USB device request code is not well understood. It is transmitted by
* the MCT-supplied Windows driver whenever the baud rate changes.
*/
#define MCT_U232_SET_UNKNOWN1_REQUEST 11 /* Unknown functionality */
#define MCT_U232_SET_UNKNOWN1_SIZE 1
/* This USB device request code appears to control whether CTS is required
during transmission.
Sending a zero byte allows data transmission to a device which is not
asserting CTS. Sending a '1' byte will cause transmission to be deferred
until the device asserts CTS.
*/
/*
* This USB device request code appears to control whether CTS is required
* during transmission.
*
* Sending a zero byte allows data transmission to a device which is not
* asserting CTS. Sending a '1' byte will cause transmission to be deferred
* until the device asserts CTS.
*/
#define MCT_U232_SET_CTS_REQUEST 12
#define MCT_U232_SET_CTS_SIZE 1
......@@ -81,7 +89,8 @@
* and "Intel solution". They are the regular MCT and "Sitecom" for us.
* This is pointless to document in the header, see the code for the bits.
*/
static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value, speed_t *result);
static int mct_u232_calculate_baud_rate(struct usb_serial *serial,
speed_t value, speed_t *result);
/*
* Line Control Register (LCR)
......@@ -290,31 +299,34 @@ static int mct_u232_calculate_baud_rate(struct usb_serial *serial, speed_t value
* --------------------------
*
* Bit 7 Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero.
* This bit is set to "1" when any of the bytes in the FIFO have one or
* more of the following error conditions: PE, FE, or BI.
* This bit is set to "1" when any of the bytes in the FIFO have one
* or more of the following error conditions: PE, FE, or BI.
* Bit 6 Transmitter Empty (TEMT). When set to "1", there are no words
* remaining in the transmit FIFO or the transmit shift register. The
* transmitter is completely idle.
* Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the FIFO
* (or holding register) now has room for at least one additional word
* to transmit. The transmitter may still be transmitting when this bit
* is set to "1".
* Bit 5 Transmitter Holding Register Empty (THRE). When set to "1", the
* FIFO (or holding register) now has room for at least one additional
* word to transmit. The transmitter may still be transmitting when
* this bit is set to "1".
* Bit 4 Break Interrupt (BI). The receiver has detected a Break signal.
* Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did not
* appear at the expected time. The received word is probably garbled.
* Bit 2 Parity Error (PE). The parity bit was incorrect for the word received.
* Bit 1 Overrun Error (OE). A new word was received and there was no room in
* the receive buffer. The newly-arrived word in the shift register is
* discarded. On 8250/16450 UARTs, the word in the holding register is
* discarded and the newly- arrived word is put in the holding register.
* Bit 3 Framing Error (FE). A Start Bit was detected but the Stop Bit did
* not appear at the expected time. The received word is probably
* garbled.
* Bit 2 Parity Error (PE). The parity bit was incorrect for the word
* received.
* Bit 1 Overrun Error (OE). A new word was received and there was no room
* in the receive buffer. The newly-arrived word in the shift register
* is discarded. On 8250/16450 UARTs, the word in the holding register
* is discarded and the newly- arrived word is put in the holding
* register.
* Bit 0 Data Ready (DR). One or more words are in the receive FIFO that the
* host may read. A word must be completely received and moved from the
* shift register into the FIFO (or holding register for 8250/16450
* designs) before this bit is set.
* host may read. A word must be completely received and moved from
* the shift register into the FIFO (or holding register for
* 8250/16450 designs) before this bit is set.
*
* SniffUSB observations: the LSR is returned as second byte on the interrupt-in
* endpoint 0x83 to signal error conditions. Such errors have been seen with
* minicom/zmodem transfers (CRC errors).
* SniffUSB observations: the LSR is returned as second byte on the
* interrupt-in endpoint 0x83 to signal error conditions. Such errors have
* been seen with minicom/zmodem transfers (CRC errors).
*
*
* Unknown #1
......
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