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Commit 42594600 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/mmu: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d7e5fcd2
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Showing with 351 additions and 374 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View file @ 42594600
...@@ -240,5 +240,6 @@ ...@@ -240,5 +240,6 @@
#define nvc0_pte_storage_type_map gf100_pte_storage_type_map #define nvc0_pte_storage_type_map gf100_pte_storage_type_map
#define nouveau_fuse nvkm_fuse #define nouveau_fuse nvkm_fuse
#define nouveau_mc nvkm_mc #define nouveau_mc nvkm_mc
#define nouveau_mmu nvkm_mmu
#endif #endif
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
View file @ 42594600
#ifndef __NVKM_CE_H__ #ifndef __NVKM_CE_H__
#define __NVKM_CE_H__ #define __NVKM_CE_H__
#include <core/engine.h>
void nva3_ce_intr(struct nouveau_subdev *); void nva3_ce_intr(struct nouveau_subdev *);
......
drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
View file @ 42594600
/* #ifndef __NVKM_MMU_H__
* Copyright 2010 Red Hat Inc. #define __NVKM_MMU_H__
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifndef __NOUVEAU_MMU_H__
#define __NOUVEAU_MMU_H__
#include <core/object.h>
#include <core/subdev.h> #include <core/subdev.h>
#include <core/device.h>
#include <core/mm.h> #include <core/mm.h>
struct nvkm_device;
struct nvkm_mem;
struct nouveau_vm_pgt { struct nvkm_vm_pgt {
struct nouveau_gpuobj *obj[2]; struct nvkm_gpuobj *obj[2];
u32 refcount[2]; u32 refcount[2];
}; };
struct nouveau_vm_pgd { struct nvkm_vm_pgd {
struct list_head head; struct list_head head;
struct nouveau_gpuobj *obj; struct nvkm_gpuobj *obj;
}; };
struct nouveau_gpuobj; struct nvkm_vma {
struct nouveau_mem;
struct nouveau_vma {
struct list_head head; struct list_head head;
int refcount; int refcount;
struct nouveau_vm *vm; struct nvkm_vm *vm;
struct nouveau_mm_node *node; struct nvkm_mm_node *node;
u64 offset; u64 offset;
u32 access; u32 access;
}; };
struct nouveau_vm { struct nvkm_vm {
struct nouveau_mmu *mmu; struct nvkm_mmu *mmu;
struct nouveau_mm mm; struct nvkm_mm mm;
struct kref refcount; struct kref refcount;
struct list_head pgd_list; struct list_head pgd_list;
atomic_t engref[NVDEV_SUBDEV_NR]; atomic_t engref[NVDEV_SUBDEV_NR];
struct nouveau_vm_pgt *pgt; struct nvkm_vm_pgt *pgt;
u32 fpde; u32 fpde;
u32 lpde; u32 lpde;
}; };
struct nouveau_mmu { struct nvkm_mmu {
struct nouveau_subdev base; struct nvkm_subdev base;
u64 limit; u64 limit;
u8 dma_bits; u8 dma_bits;
...@@ -74,62 +46,59 @@ struct nouveau_mmu { ...@@ -74,62 +46,59 @@ struct nouveau_mmu {
u8 spg_shift; u8 spg_shift;
u8 lpg_shift; u8 lpg_shift;
int (*create)(struct nouveau_mmu *, u64 offset, u64 length, int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **); u64 mm_offset, struct nvkm_vm **);
void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
struct nouveau_gpuobj *pgt[2]); struct nvkm_gpuobj *pgt[2]);
void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *,
struct nouveau_mem *, u32 pte, u32 cnt, struct nvkm_mem *, u32 pte, u32 cnt,
u64 phys, u64 delta); u64 phys, u64 delta);
void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *,
struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt);
void (*flush)(struct nouveau_vm *); void (*flush)(struct nvkm_vm *);
}; };
static inline struct nouveau_mmu * static inline struct nvkm_mmu *
nouveau_mmu(void *obj) nvkm_mmu(void *obj)
{ {
return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU); return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
} }
#define nouveau_mmu_create(p,e,o,i,f,d) \ #define nvkm_mmu_create(p,e,o,i,f,d) \
nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
#define nouveau_mmu_destroy(p) \ #define nvkm_mmu_destroy(p) \
nouveau_subdev_destroy(&(p)->base) nvkm_subdev_destroy(&(p)->base)
#define nouveau_mmu_init(p) \ #define nvkm_mmu_init(p) \
nouveau_subdev_init(&(p)->base) nvkm_subdev_init(&(p)->base)
#define nouveau_mmu_fini(p,s) \ #define nvkm_mmu_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s)) nvkm_subdev_fini(&(p)->base, (s))
#define _nouveau_mmu_dtor _nouveau_subdev_dtor #define _nvkm_mmu_dtor _nvkm_subdev_dtor
#define _nouveau_mmu_init _nouveau_subdev_init #define _nvkm_mmu_init _nvkm_subdev_init
#define _nouveau_mmu_fini _nouveau_subdev_fini #define _nvkm_mmu_fini _nvkm_subdev_fini
extern struct nouveau_oclass nv04_mmu_oclass; extern struct nvkm_oclass nv04_mmu_oclass;
extern struct nouveau_oclass nv41_mmu_oclass; extern struct nvkm_oclass nv41_mmu_oclass;
extern struct nouveau_oclass nv44_mmu_oclass; extern struct nvkm_oclass nv44_mmu_oclass;
extern struct nouveau_oclass nv50_mmu_oclass; extern struct nvkm_oclass nv50_mmu_oclass;
extern struct nouveau_oclass nvc0_mmu_oclass; extern struct nvkm_oclass gf100_mmu_oclass;
int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64, int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64,
struct nouveau_vm **); struct nvkm_vm **);
void nv04_mmu_dtor(struct nouveau_object *); void nv04_mmu_dtor(struct nvkm_object *);
/* nouveau_vm.c */ int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length, u32 block, struct nvkm_vm **);
u64 mm_offset, u32 block, struct nouveau_vm **); int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, struct nvkm_vm **);
u64 mm_offset, struct nouveau_vm **); int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
struct nouveau_gpuobj *pgd); struct nvkm_vma *);
int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, void nvkm_vm_put(struct nvkm_vma *);
u32 access, struct nouveau_vma *); void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
void nouveau_vm_put(struct nouveau_vma *); void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); void nvkm_vm_unmap(struct nvkm_vma *);
void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
void nouveau_vm_unmap(struct nouveau_vma *);
void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
#endif #endif
drivers/gpu/drm/nouveau/nvkm/core/engctx.c
View file @ 42594600
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/engctx.h> #include <core/engctx.h>
#include <core/engine.h>
#include <core/client.h> #include <core/client.h>
static inline int static inline int
......
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
View file @ 42594600
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <core/engine.h>
#include <subdev/instmem.h> #include <subdev/instmem.h>
#include <subdev/bar.h> #include <subdev/bar.h>
......
drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
View file @ 42594600
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <subdev/mmu.h> #include <subdev/mmu.h>
#include <core/client.h> #include <core/client.h>
#include <core/device.h>
#include <core/enum.h> #include <core/enum.h>
......
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View file @ 42594600
...@@ -76,7 +76,7 @@ gm100_identify(struct nouveau_device *device) ...@@ -76,7 +76,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
...@@ -120,7 +120,7 @@ gm100_identify(struct nouveau_device *device) ...@@ -120,7 +120,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0 #if 0
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View file @ 42594600
...@@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -109,7 +109,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -109,7 +109,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -142,7 +142,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -142,7 +142,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -174,7 +174,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -174,7 +174,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -239,7 +239,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -239,7 +239,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -271,7 +271,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -271,7 +271,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View file @ 42594600
...@@ -76,7 +76,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -76,7 +76,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -110,7 +110,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -110,7 +110,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -144,7 +144,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -144,7 +144,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -172,7 +172,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -172,7 +172,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
...@@ -200,7 +200,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -200,7 +200,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -234,7 +234,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -234,7 +234,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -268,7 +268,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -268,7 +268,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
...@@ -301,7 +301,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -301,7 +301,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
View file @ 42594600
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <core/object.h> #include <core/object.h>
#include <core/client.h> #include <core/client.h>
#include <core/device.h>
#include <nvif/unpack.h> #include <nvif/unpack.h>
#include <nvif/class.h> #include <nvif/class.h>
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View file @ 42594600
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
*/ */
#include <core/client.h> #include <core/client.h>
#include <core/device.h>
#include <nvif/unpack.h> #include <nvif/unpack.h>
#include <nvif/class.h> #include <nvif/class.h>
#include <core/engctx.h> #include <core/engctx.h>
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
View file @ 42594600
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE. * OTHER DEALINGS IN THE SOFTWARE.
*/ */
#include <core/device.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#define CP_FLAG_CLEAR 0 #define CP_FLAG_CLEAR 0
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
View file @ 42594600
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
*/ */
#include <core/client.h> #include <core/client.h>
#include <core/device.h>
#include <core/os.h> #include <core/os.h>
#include <core/handle.h> #include <core/handle.h>
......
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
View file @ 42594600
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE. * OTHER DEALINGS IN THE SOFTWARE.
*/ */
#include <engine/xtensa.h> #include <engine/xtensa.h>
#include <core/device.h>
#include <core/engctx.h> #include <core/engctx.h>
......
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
View file @ 42594600
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
*/ */
#include "priv.h" #include "priv.h"
#include <core/device.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <subdev/fb.h> #include <subdev/fb.h>
#include <subdev/mmu.h> #include <subdev/mmu.h>
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
View file @ 42594600
...@@ -23,6 +23,8 @@ ...@@ -23,6 +23,8 @@
*/ */
#include "gf100.h" #include "gf100.h"
#include <core/device.h>
extern const u8 gf100_pte_storage_type_map[256]; extern const u8 gf100_pte_storage_type_map[256];
bool bool
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
View file @ 42594600
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
*/ */
#include "nv04.h" #include "nv04.h"
#include <core/device.h>
void void
nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nvkm_fb_tile *tile) u32 flags, struct nvkm_fb_tile *tile)
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
View file @ 42594600
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include "nv50.h" #include "nv50.h"
#include <core/client.h> #include <core/client.h>
#include <core/device.h>
#include <core/engctx.h> #include <core/engctx.h>
#include <core/enum.h> #include <core/enum.h>
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
View file @ 42594600
...@@ -21,6 +21,8 @@ ...@@ -21,6 +21,8 @@
*/ */
#include "priv.h" #include "priv.h"
#include <core/device.h>
struct gk20a_mem { struct gk20a_mem {
struct nvkm_mem base; struct nvkm_mem base;
void *cpuaddr; void *cpuaddr;
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
View file @ 42594600
...@@ -23,6 +23,8 @@ ...@@ -23,6 +23,8 @@
*/ */
#include "priv.h" #include "priv.h"
#include <core/device.h>
static int static int
nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
View file @ 42594600
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include "nv50.h" #include "nv50.h"
#include "ramseq.h" #include "ramseq.h"
#include <core/device.h>
#include <core/option.h> #include <core/option.h>
#include <subdev/bios.h> #include <subdev/bios.h>
#include <subdev/bios/perf.h> #include <subdev/bios/perf.h>
......
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
View file @ 42594600
...@@ -3,4 +3,4 @@ nvkm-y += nvkm/subdev/mmu/nv04.o ...@@ -3,4 +3,4 @@ nvkm-y += nvkm/subdev/mmu/nv04.o
nvkm-y += nvkm/subdev/mmu/nv41.o nvkm-y += nvkm/subdev/mmu/nv41.o
nvkm-y += nvkm/subdev/mmu/nv44.o nvkm-y += nvkm/subdev/mmu/nv44.o
nvkm-y += nvkm/subdev/mmu/nv50.o nvkm-y += nvkm/subdev/mmu/nv50.o
nvkm-y += nvkm/subdev/mmu/nvc0.o nvkm-y += nvkm/subdev/mmu/gf100.o
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c → drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
View file @ 42594600
...@@ -21,25 +21,23 @@ ...@@ -21,25 +21,23 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/device.h>
#include <core/gpuobj.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/mmu.h> #include <subdev/mmu.h>
#include <subdev/ltc.h>
#include <subdev/bar.h> #include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/timer.h>
struct nvc0_mmu_priv { #include <core/gpuobj.h>
struct nouveau_mmu base;
struct gf100_mmu_priv {
struct nvkm_mmu base;
}; };
/* Map from compressed to corresponding uncompressed storage type. /* Map from compressed to corresponding uncompressed storage type.
* The value 0xff represents an invalid storage type. * The value 0xff represents an invalid storage type.
*/ */
const u8 nvc0_pte_storage_type_map[256] = const u8 gf100_pte_storage_type_map[256] =
{ {
0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */
0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff,
...@@ -77,8 +75,7 @@ const u8 nvc0_pte_storage_type_map[256] = ...@@ -77,8 +75,7 @@ const u8 nvc0_pte_storage_type_map[256] =
static void static void
nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_gpuobj *pgt[2])
struct nouveau_gpuobj *pgt[2])
{ {
u32 pde[2] = { 0, 0 }; u32 pde[2] = { 0, 0 };
...@@ -92,7 +89,7 @@ nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, ...@@ -92,7 +89,7 @@ nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
} }
static inline u64 static inline u64
nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
{ {
phys >>= 8; phys >>= 8;
...@@ -102,21 +99,20 @@ nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) ...@@ -102,21 +99,20 @@ nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
phys |= ((u64)target << 32); phys |= ((u64)target << 32);
phys |= ((u64)memtype << 36); phys |= ((u64)memtype << 36);
return phys; return phys;
} }
static void static void
nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, gf100_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{ {
u64 next = 1 << (vma->node->type - 8); u64 next = 1 << (vma->node->type - 8);
phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); phys = gf100_vm_addr(vma, phys, mem->memtype, 0);
pte <<= 3; pte <<= 3;
if (mem->tag) { if (mem->tag) {
struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu); struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu);
u32 tag = mem->tag->offset + (delta >> 17); u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12); phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12); next |= (u64)1 << (32 + 12);
...@@ -132,16 +128,16 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -132,16 +128,16 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{ {
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
/* compressed storage types are invalid for system memory */ /* compressed storage types are invalid for system memory */
u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff];
pte <<= 3; pte <<= 3;
while (cnt--) { while (cnt--) {
u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); u64 phys = gf100_vm_addr(vma, *list++, memtype, target);
nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 0, lower_32_bits(phys));
nv_wo32(pgt, pte + 4, upper_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys));
pte += 8; pte += 8;
...@@ -149,7 +145,7 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -149,7 +145,7 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) gf100_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{ {
pte <<= 3; pte <<= 3;
while (cnt--) { while (cnt--) {
...@@ -160,11 +156,11 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) ...@@ -160,11 +156,11 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
} }
static void static void
nvc0_vm_flush(struct nouveau_vm *vm) gf100_vm_flush(struct nvkm_vm *vm)
{ {
struct nvc0_mmu_priv *priv = (void *)vm->mmu; struct gf100_mmu_priv *priv = (void *)vm->mmu;
struct nouveau_bar *bar = nouveau_bar(priv); struct nvkm_bar *bar = nvkm_bar(priv);
struct nouveau_vm_pgd *vpgd; struct nvkm_vm_pgd *vpgd;
u32 type; u32 type;
bar->flush(bar); bar->flush(bar);
...@@ -196,21 +192,21 @@ nvc0_vm_flush(struct nouveau_vm *vm) ...@@ -196,21 +192,21 @@ nvc0_vm_flush(struct nouveau_vm *vm)
} }
static int static int
nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
u64 mm_offset, struct nouveau_vm **pvm) struct nvkm_vm **pvm)
{ {
return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm); return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
} }
static int static int
nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nvc0_mmu_priv *priv; struct gf100_mmu_priv *priv;
int ret; int ret;
ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
...@@ -220,22 +216,22 @@ nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -220,22 +216,22 @@ nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.pgt_bits = 27 - 12; priv->base.pgt_bits = 27 - 12;
priv->base.spg_shift = 12; priv->base.spg_shift = 12;
priv->base.lpg_shift = 17; priv->base.lpg_shift = 17;
priv->base.create = nvc0_vm_create; priv->base.create = gf100_vm_create;
priv->base.map_pgt = nvc0_vm_map_pgt; priv->base.map_pgt = gf100_vm_map_pgt;
priv->base.map = nvc0_vm_map; priv->base.map = gf100_vm_map;
priv->base.map_sg = nvc0_vm_map_sg; priv->base.map_sg = gf100_vm_map_sg;
priv->base.unmap = nvc0_vm_unmap; priv->base.unmap = gf100_vm_unmap;
priv->base.flush = nvc0_vm_flush; priv->base.flush = gf100_vm_flush;
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nvc0_mmu_oclass = { gf100_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0xc0), .handle = NV_SUBDEV(MMU, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nvc0_mmu_ctor, .ctor = gf100_mmu_ctor,
.dtor = _nouveau_mmu_dtor, .dtor = _nvkm_mmu_dtor,
.init = _nouveau_mmu_init, .init = _nvkm_mmu_init,
.fini = _nouveau_mmu_fini, .fini = _nvkm_mmu_fini,
}, },
}; };
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
View file @ 42594600
...@@ -21,11 +21,11 @@ ...@@ -21,11 +21,11 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h"
#include <core/device.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include "nv04.h"
#define NV04_PDMA_SIZE (128 * 1024 * 1024) #define NV04_PDMA_SIZE (128 * 1024 * 1024)
#define NV04_PDMA_PAGE ( 4 * 1024) #define NV04_PDMA_PAGE ( 4 * 1024)
...@@ -34,8 +34,8 @@ ...@@ -34,8 +34,8 @@
******************************************************************************/ ******************************************************************************/
static void static void
nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{ {
pte = 0x00008 + (pte * 4); pte = 0x00008 + (pte * 4);
while (cnt) { while (cnt) {
...@@ -51,7 +51,7 @@ nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -51,7 +51,7 @@ nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{ {
pte = 0x00008 + (pte * 4); pte = 0x00008 + (pte * 4);
while (cnt--) { while (cnt--) {
...@@ -61,7 +61,7 @@ nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) ...@@ -61,7 +61,7 @@ nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
} }
static void static void
nv04_vm_flush(struct nouveau_vm *vm) nv04_vm_flush(struct nvkm_vm *vm)
{ {
} }
...@@ -70,8 +70,8 @@ nv04_vm_flush(struct nouveau_vm *vm) ...@@ -70,8 +70,8 @@ nv04_vm_flush(struct nouveau_vm *vm)
******************************************************************************/ ******************************************************************************/
int int
nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart, nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
struct nouveau_vm **pvm) struct nvkm_vm **pvm)
{ {
return -EINVAL; return -EINVAL;
} }
...@@ -81,15 +81,15 @@ nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart, ...@@ -81,15 +81,15 @@ nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
******************************************************************************/ ******************************************************************************/
static int static int
nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nv04_mmu_priv *priv; struct nv04_mmu_priv *priv;
struct nouveau_gpuobj *dma; struct nvkm_gpuobj *dma;
int ret; int ret;
ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART", ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
"pcigart", &priv); "pcigart", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
...@@ -105,14 +105,14 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -105,14 +105,14 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.unmap = nv04_vm_unmap; priv->base.unmap = nv04_vm_unmap;
priv->base.flush = nv04_vm_flush; priv->base.flush = nv04_vm_flush;
ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
&priv->vm); &priv->vm);
if (ret) if (ret)
return ret; return ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, ret = nvkm_gpuobj_new(nv_object(priv), NULL,
(NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8,
8, 16, NVOBJ_FLAG_ZERO_ALLOC, 16, NVOBJ_FLAG_ZERO_ALLOC,
&priv->vm->pgt[0].obj[0]); &priv->vm->pgt[0].obj[0]);
dma = priv->vm->pgt[0].obj[0]; dma = priv->vm->pgt[0].obj[0];
priv->vm->pgt[0].refcount[0] = 1; priv->vm->pgt[0].refcount[0] = 1;
...@@ -125,27 +125,27 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -125,27 +125,27 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
} }
void void
nv04_mmu_dtor(struct nouveau_object *object) nv04_mmu_dtor(struct nvkm_object *object)
{ {
struct nv04_mmu_priv *priv = (void *)object; struct nv04_mmu_priv *priv = (void *)object;
if (priv->vm) { if (priv->vm) {
nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
nouveau_vm_ref(NULL, &priv->vm, NULL); nvkm_vm_ref(NULL, &priv->vm, NULL);
} }
if (priv->nullp) { if (priv->nullp) {
pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
priv->nullp, priv->null); priv->nullp, priv->null);
} }
nouveau_mmu_destroy(&priv->base); nvkm_mmu_destroy(&priv->base);
} }
struct nouveau_oclass struct nvkm_oclass
nv04_mmu_oclass = { nv04_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x04), .handle = NV_SUBDEV(MMU, 0x04),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_mmu_ctor, .ctor = nv04_mmu_ctor,
.dtor = nv04_mmu_dtor, .dtor = nv04_mmu_dtor,
.init = _nouveau_mmu_init, .init = _nvkm_mmu_init,
.fini = _nouveau_mmu_fini, .fini = _nvkm_mmu_fini,
}, },
}; };
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
View file @ 42594600
...@@ -4,8 +4,8 @@ ...@@ -4,8 +4,8 @@
#include <subdev/mmu.h> #include <subdev/mmu.h>
struct nv04_mmu_priv { struct nv04_mmu_priv {
struct nouveau_mmu base; struct nvkm_mmu base;
struct nouveau_vm *vm; struct nvkm_vm *vm;
dma_addr_t null; dma_addr_t null;
void *nullp; void *nullp;
}; };
...@@ -13,7 +13,7 @@ struct nv04_mmu_priv { ...@@ -13,7 +13,7 @@ struct nv04_mmu_priv {
static inline struct nv04_mmu_priv * static inline struct nv04_mmu_priv *
nv04_mmu(void *obj) nv04_mmu(void *obj)
{ {
return (void *)nouveau_mmu(obj); return (void *)nvkm_mmu(obj);
} }
#endif #endif
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
View file @ 42594600
...@@ -21,14 +21,12 @@ ...@@ -21,14 +21,12 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h"
#include <core/device.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <core/option.h> #include <core/option.h>
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/mmu.h>
#include "nv04.h"
#define NV41_GART_SIZE (512 * 1024 * 1024) #define NV41_GART_SIZE (512 * 1024 * 1024)
#define NV41_GART_PAGE ( 4 * 1024) #define NV41_GART_PAGE ( 4 * 1024)
...@@ -38,8 +36,8 @@ ...@@ -38,8 +36,8 @@
******************************************************************************/ ******************************************************************************/
static void static void
nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{ {
pte = pte * 4; pte = pte * 4;
while (cnt) { while (cnt) {
...@@ -55,7 +53,7 @@ nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -55,7 +53,7 @@ nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{ {
pte = pte * 4; pte = pte * 4;
while (cnt--) { while (cnt--) {
...@@ -65,7 +63,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) ...@@ -65,7 +63,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
} }
static void static void
nv41_vm_flush(struct nouveau_vm *vm) nv41_vm_flush(struct nvkm_vm *vm)
{ {
struct nv04_mmu_priv *priv = (void *)vm->mmu; struct nv04_mmu_priv *priv = (void *)vm->mmu;
...@@ -84,21 +82,21 @@ nv41_vm_flush(struct nouveau_vm *vm) ...@@ -84,21 +82,21 @@ nv41_vm_flush(struct nouveau_vm *vm)
******************************************************************************/ ******************************************************************************/
static int static int
nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nouveau_device *device = nv_device(parent); struct nvkm_device *device = nv_device(parent);
struct nv04_mmu_priv *priv; struct nv04_mmu_priv *priv;
int ret; int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
data, size, pobject); data, size, pobject);
} }
ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
"pciegart", &priv); "pciegart", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
...@@ -114,14 +112,14 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -114,14 +112,14 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.unmap = nv41_vm_unmap; priv->base.unmap = nv41_vm_unmap;
priv->base.flush = nv41_vm_flush; priv->base.flush = nv41_vm_flush;
ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
&priv->vm); &priv->vm);
if (ret) if (ret)
return ret; return ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, ret = nvkm_gpuobj_new(nv_object(priv), NULL,
(NV41_GART_SIZE / NV41_GART_PAGE) * 4, (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16,
16, NVOBJ_FLAG_ZERO_ALLOC, NVOBJ_FLAG_ZERO_ALLOC,
&priv->vm->pgt[0].obj[0]); &priv->vm->pgt[0].obj[0]);
priv->vm->pgt[0].refcount[0] = 1; priv->vm->pgt[0].refcount[0] = 1;
if (ret) if (ret)
...@@ -131,13 +129,13 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -131,13 +129,13 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
} }
static int static int
nv41_mmu_init(struct nouveau_object *object) nv41_mmu_init(struct nvkm_object *object)
{ {
struct nv04_mmu_priv *priv = (void *)object; struct nv04_mmu_priv *priv = (void *)object;
struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0];
int ret; int ret;
ret = nouveau_mmu_init(&priv->base); ret = nvkm_mmu_init(&priv->base);
if (ret) if (ret)
return ret; return ret;
...@@ -147,13 +145,13 @@ nv41_mmu_init(struct nouveau_object *object) ...@@ -147,13 +145,13 @@ nv41_mmu_init(struct nouveau_object *object)
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nv41_mmu_oclass = { nv41_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x41), .handle = NV_SUBDEV(MMU, 0x41),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv41_mmu_ctor, .ctor = nv41_mmu_ctor,
.dtor = nv04_mmu_dtor, .dtor = nv04_mmu_dtor,
.init = nv41_mmu_init, .init = nv41_mmu_init,
.fini = _nouveau_mmu_fini, .fini = _nvkm_mmu_fini,
}, },
}; };
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
View file @ 42594600
...@@ -21,14 +21,12 @@ ...@@ -21,14 +21,12 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "nv04.h"
#include <core/device.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <core/option.h> #include <core/option.h>
#include <subdev/timer.h> #include <subdev/timer.h>
#include <subdev/mmu.h>
#include "nv04.h"
#define NV44_GART_SIZE (512 * 1024 * 1024) #define NV44_GART_SIZE (512 * 1024 * 1024)
#define NV44_GART_PAGE ( 4 * 1024) #define NV44_GART_PAGE ( 4 * 1024)
...@@ -38,7 +36,7 @@ ...@@ -38,7 +36,7 @@
******************************************************************************/ ******************************************************************************/
static void static void
nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null,
dma_addr_t *list, u32 pte, u32 cnt) dma_addr_t *list, u32 pte, u32 cnt)
{ {
u32 base = (pte << 2) & ~0x0000000f; u32 base = (pte << 2) & ~0x0000000f;
...@@ -84,8 +82,8 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, ...@@ -84,8 +82,8 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
} }
static void static void
nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{ {
struct nv04_mmu_priv *priv = (void *)vma->vm->mmu; struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
u32 tmp[4]; u32 tmp[4];
...@@ -115,9 +113,9 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -115,9 +113,9 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{ {
struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt); struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt);
if (pte & 3) { if (pte & 3) {
u32 max = 4 - (pte & 3); u32 max = 4 - (pte & 3);
...@@ -140,7 +138,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) ...@@ -140,7 +138,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
} }
static void static void
nv44_vm_flush(struct nouveau_vm *vm) nv44_vm_flush(struct nvkm_vm *vm)
{ {
struct nv04_mmu_priv *priv = (void *)vm->mmu; struct nv04_mmu_priv *priv = (void *)vm->mmu;
nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
...@@ -155,21 +153,21 @@ nv44_vm_flush(struct nouveau_vm *vm) ...@@ -155,21 +153,21 @@ nv44_vm_flush(struct nouveau_vm *vm)
******************************************************************************/ ******************************************************************************/
static int static int
nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nouveau_device *device = nv_device(parent); struct nvkm_device *device = nv_device(parent);
struct nv04_mmu_priv *priv; struct nv04_mmu_priv *priv;
int ret; int ret;
if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
!nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
data, size, pobject); data, size, pobject);
} }
ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
"pciegart", &priv); "pciegart", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
...@@ -191,12 +189,12 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -191,12 +189,12 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return -ENOMEM; return -ENOMEM;
} }
ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, ret = nvkm_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
&priv->vm); &priv->vm);
if (ret) if (ret)
return ret; return ret;
ret = nouveau_gpuobj_new(nv_object(priv), NULL, ret = nvkm_gpuobj_new(nv_object(priv), NULL,
(NV44_GART_SIZE / NV44_GART_PAGE) * 4, (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
&priv->vm->pgt[0].obj[0]); &priv->vm->pgt[0].obj[0]);
...@@ -208,14 +206,14 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -208,14 +206,14 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
} }
static int static int
nv44_mmu_init(struct nouveau_object *object) nv44_mmu_init(struct nvkm_object *object)
{ {
struct nv04_mmu_priv *priv = (void *)object; struct nv04_mmu_priv *priv = (void *)object;
struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0];
u32 addr; u32 addr;
int ret; int ret;
ret = nouveau_mmu_init(&priv->base); ret = nvkm_mmu_init(&priv->base);
if (ret) if (ret)
return ret; return ret;
...@@ -237,13 +235,13 @@ nv44_mmu_init(struct nouveau_object *object) ...@@ -237,13 +235,13 @@ nv44_mmu_init(struct nouveau_object *object)
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nv44_mmu_oclass = { nv44_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x44), .handle = NV_SUBDEV(MMU, 0x44),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv44_mmu_ctor, .ctor = nv44_mmu_ctor,
.dtor = nv04_mmu_dtor, .dtor = nv04_mmu_dtor,
.init = nv44_mmu_init, .init = nv44_mmu_init,
.fini = _nouveau_mmu_fini, .fini = _nvkm_mmu_fini,
}, },
}; };
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
View file @ 42594600
...@@ -21,22 +21,20 @@ ...@@ -21,22 +21,20 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <core/device.h> #include <core/engine.h>
#include <core/gpuobj.h> #include <core/gpuobj.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/bar.h>
#include <subdev/mmu.h>
struct nv50_mmu_priv { struct nv50_mmu_priv {
struct nouveau_mmu base; struct nvkm_mmu base;
}; };
static void static void
nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2])
struct nouveau_gpuobj *pgt[2])
{ {
u64 phys = 0xdeadcafe00000000ULL; u64 phys = 0xdeadcafe00000000ULL;
u32 coverage = 0; u32 coverage = 0;
...@@ -64,7 +62,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, ...@@ -64,7 +62,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
} }
static inline u64 static inline u64
vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
{ {
phys |= 1; /* present */ phys |= 1; /* present */
phys |= (u64)memtype << 40; phys |= (u64)memtype << 40;
...@@ -77,8 +75,8 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) ...@@ -77,8 +75,8 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
} }
static void static void
nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{ {
u32 comp = (mem->memtype & 0x180) >> 7; u32 comp = (mem->memtype & 0x180) >> 7;
u32 block, target; u32 block, target;
...@@ -86,8 +84,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -86,8 +84,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
/* IGPs don't have real VRAM, re-target to stolen system memory */ /* IGPs don't have real VRAM, re-target to stolen system memory */
target = 0; target = 0;
if (nouveau_fb(vma->vm->mmu)->ram->stolen) { if (nvkm_fb(vma->vm->mmu)->ram->stolen) {
phys += nouveau_fb(vma->vm->mmu)->ram->stolen; phys += nvkm_fb(vma->vm->mmu)->ram->stolen;
target = 3; target = 3;
} }
...@@ -124,8 +122,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -124,8 +122,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{ {
u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
pte <<= 3; pte <<= 3;
...@@ -138,7 +136,7 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, ...@@ -138,7 +136,7 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
} }
static void static void
nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{ {
pte <<= 3; pte <<= 3;
while (cnt--) { while (cnt--) {
...@@ -149,11 +147,11 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) ...@@ -149,11 +147,11 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
} }
static void static void
nv50_vm_flush(struct nouveau_vm *vm) nv50_vm_flush(struct nvkm_vm *vm)
{ {
struct nv50_mmu_priv *priv = (void *)vm->mmu; struct nv50_mmu_priv *priv = (void *)vm->mmu;
struct nouveau_bar *bar = nouveau_bar(priv); struct nvkm_bar *bar = nvkm_bar(priv);
struct nouveau_engine *engine; struct nvkm_engine *engine;
int i, vme; int i, vme;
bar->flush(bar); bar->flush(bar);
...@@ -164,7 +162,7 @@ nv50_vm_flush(struct nouveau_vm *vm) ...@@ -164,7 +162,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
continue; continue;
/* unfortunate hw bug workaround... */ /* unfortunate hw bug workaround... */
engine = nouveau_engine(priv, i); engine = nvkm_engine(priv, i);
if (engine && engine->tlb_flush) { if (engine && engine->tlb_flush) {
engine->tlb_flush(engine); engine->tlb_flush(engine);
continue; continue;
...@@ -194,25 +192,25 @@ nv50_vm_flush(struct nouveau_vm *vm) ...@@ -194,25 +192,25 @@ nv50_vm_flush(struct nouveau_vm *vm)
} }
static int static int
nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **pvm) u64 mm_offset, struct nvkm_vm **pvm)
{ {
u32 block = (1 << (mmu->pgt_bits + 12)); u32 block = (1 << (mmu->pgt_bits + 12));
if (block > length) if (block > length)
block = length; block = length;
return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm); return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm);
} }
static int static int
nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nvkm_object **pobject)
{ {
struct nv50_mmu_priv *priv; struct nv50_mmu_priv *priv;
int ret; int ret;
ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret) if (ret)
return ret; return ret;
...@@ -231,13 +229,13 @@ nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -231,13 +229,13 @@ nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nvkm_oclass
nv50_mmu_oclass = { nv50_mmu_oclass = {
.handle = NV_SUBDEV(MMU, 0x50), .handle = NV_SUBDEV(MMU, 0x50),
.ofuncs = &(struct nouveau_ofuncs) { .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_mmu_ctor, .ctor = nv50_mmu_ctor,
.dtor = _nouveau_mmu_dtor, .dtor = _nvkm_mmu_dtor,
.init = _nouveau_mmu_init, .init = _nvkm_mmu_init,
.fini = _nouveau_mmu_fini, .fini = _nvkm_mmu_fini,
}, },
}; };
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