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Commit 42c1a2ed authored by Kedareswara rao Appana's avatar Kedareswara rao Appana Committed by Vinod Koul
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dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma 

This patch renames the xilinx_vdma_ prefix to xilinx_dma
for the API's and masks that will be shared b/w three DMA
IP cores.
Signed-off-by: default avatarKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 2ba4f8ab
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Showing with 316 additions and 316 deletions
drivers/dma/xilinx/xilinx_vdma.c
View file @ 42c1a2ed
......@@ -39,106 +39,106 @@
#include "../dmaengine.h"
/* Register/Descriptor Offsets */
#define XILINX_VDMA_MM2S_CTRL_OFFSET 0x0000
#define XILINX_VDMA_S2MM_CTRL_OFFSET 0x0030
#define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000
#define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030
#define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050
#define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0
/* Control Registers */
#define XILINX_VDMA_REG_DMACR 0x0000
#define XILINX_VDMA_DMACR_DELAY_MAX 0xff
#define XILINX_VDMA_DMACR_DELAY_SHIFT 24
#define XILINX_VDMA_DMACR_FRAME_COUNT_MAX 0xff
#define XILINX_VDMA_DMACR_FRAME_COUNT_SHIFT 16
#define XILINX_VDMA_DMACR_ERR_IRQ BIT(14)
#define XILINX_VDMA_DMACR_DLY_CNT_IRQ BIT(13)
#define XILINX_VDMA_DMACR_FRM_CNT_IRQ BIT(12)
#define XILINX_VDMA_DMACR_MASTER_SHIFT 8
#define XILINX_VDMA_DMACR_FSYNCSRC_SHIFT 5
#define XILINX_VDMA_DMACR_FRAMECNT_EN BIT(4)
#define XILINX_VDMA_DMACR_GENLOCK_EN BIT(3)
#define XILINX_VDMA_DMACR_RESET BIT(2)
#define XILINX_VDMA_DMACR_CIRC_EN BIT(1)
#define XILINX_VDMA_DMACR_RUNSTOP BIT(0)
#define XILINX_VDMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
#define XILINX_VDMA_REG_DMASR 0x0004
#define XILINX_VDMA_DMASR_EOL_LATE_ERR BIT(15)
#define XILINX_VDMA_DMASR_ERR_IRQ BIT(14)
#define XILINX_VDMA_DMASR_DLY_CNT_IRQ BIT(13)
#define XILINX_VDMA_DMASR_FRM_CNT_IRQ BIT(12)
#define XILINX_VDMA_DMASR_SOF_LATE_ERR BIT(11)
#define XILINX_VDMA_DMASR_SG_DEC_ERR BIT(10)
#define XILINX_VDMA_DMASR_SG_SLV_ERR BIT(9)
#define XILINX_VDMA_DMASR_EOF_EARLY_ERR BIT(8)
#define XILINX_VDMA_DMASR_SOF_EARLY_ERR BIT(7)
#define XILINX_VDMA_DMASR_DMA_DEC_ERR BIT(6)
#define XILINX_VDMA_DMASR_DMA_SLAVE_ERR BIT(5)
#define XILINX_VDMA_DMASR_DMA_INT_ERR BIT(4)
#define XILINX_VDMA_DMASR_IDLE BIT(1)
#define XILINX_VDMA_DMASR_HALTED BIT(0)
#define XILINX_VDMA_DMASR_DELAY_MASK GENMASK(31, 24)
#define XILINX_VDMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
#define XILINX_VDMA_REG_CURDESC 0x0008
#define XILINX_VDMA_REG_TAILDESC 0x0010
#define XILINX_VDMA_REG_REG_INDEX 0x0014
#define XILINX_VDMA_REG_FRMSTORE 0x0018
#define XILINX_VDMA_REG_THRESHOLD 0x001c
#define XILINX_VDMA_REG_FRMPTR_STS 0x0024
#define XILINX_VDMA_REG_PARK_PTR 0x0028
#define XILINX_VDMA_PARK_PTR_WR_REF_SHIFT 8
#define XILINX_VDMA_PARK_PTR_RD_REF_SHIFT 0
#define XILINX_VDMA_REG_VDMA_VERSION 0x002c
#define XILINX_DMA_REG_DMACR 0x0000
#define XILINX_DMA_DMACR_DELAY_MAX 0xff
#define XILINX_DMA_DMACR_DELAY_SHIFT 24
#define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff
#define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16
#define XILINX_DMA_DMACR_ERR_IRQ BIT(14)
#define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13)
#define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12)
#define XILINX_DMA_DMACR_MASTER_SHIFT 8
#define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5
#define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4)
#define XILINX_DMA_DMACR_GENLOCK_EN BIT(3)
#define XILINX_DMA_DMACR_RESET BIT(2)
#define XILINX_DMA_DMACR_CIRC_EN BIT(1)
#define XILINX_DMA_DMACR_RUNSTOP BIT(0)
#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
#define XILINX_DMA_REG_DMASR 0x0004
#define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
#define XILINX_DMA_DMASR_ERR_IRQ BIT(14)
#define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13)
#define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12)
#define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11)
#define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10)
#define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9)
#define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8)
#define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7)
#define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6)
#define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5)
#define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4)
#define XILINX_DMA_DMASR_IDLE BIT(1)
#define XILINX_DMA_DMASR_HALTED BIT(0)
#define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24)
#define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16)
#define XILINX_DMA_REG_CURDESC 0x0008
#define XILINX_DMA_REG_TAILDESC 0x0010
#define XILINX_DMA_REG_REG_INDEX 0x0014
#define XILINX_DMA_REG_FRMSTORE 0x0018
#define XILINX_DMA_REG_THRESHOLD 0x001c
#define XILINX_DMA_REG_FRMPTR_STS 0x0024
#define XILINX_DMA_REG_PARK_PTR 0x0028
#define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8
#define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0
#define XILINX_DMA_REG_VDMA_VERSION 0x002c
/* Register Direct Mode Registers */
#define XILINX_VDMA_REG_VSIZE 0x0000
#define XILINX_VDMA_REG_HSIZE 0x0004
#define XILINX_DMA_REG_VSIZE 0x0000
#define XILINX_DMA_REG_HSIZE 0x0004
#define XILINX_VDMA_REG_FRMDLY_STRIDE 0x0008
#define XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
#define XILINX_VDMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
#define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008
#define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24
#define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0
#define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n))
#define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
/* HW specific definitions */
#define XILINX_VDMA_MAX_CHANS_PER_DEVICE 0x2
#define XILINX_VDMA_DMAXR_ALL_IRQ_MASK \
(XILINX_VDMA_DMASR_FRM_CNT_IRQ | \
XILINX_VDMA_DMASR_DLY_CNT_IRQ | \
XILINX_VDMA_DMASR_ERR_IRQ)
#define XILINX_VDMA_DMASR_ALL_ERR_MASK \
(XILINX_VDMA_DMASR_EOL_LATE_ERR | \
XILINX_VDMA_DMASR_SOF_LATE_ERR | \
XILINX_VDMA_DMASR_SG_DEC_ERR | \
XILINX_VDMA_DMASR_SG_SLV_ERR | \
XILINX_VDMA_DMASR_EOF_EARLY_ERR | \
XILINX_VDMA_DMASR_SOF_EARLY_ERR | \
XILINX_VDMA_DMASR_DMA_DEC_ERR | \
XILINX_VDMA_DMASR_DMA_SLAVE_ERR | \
XILINX_VDMA_DMASR_DMA_INT_ERR)
#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2
#define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
(XILINX_DMA_DMASR_FRM_CNT_IRQ | \
XILINX_DMA_DMASR_DLY_CNT_IRQ | \
XILINX_DMA_DMASR_ERR_IRQ)
#define XILINX_DMA_DMASR_ALL_ERR_MASK \
(XILINX_DMA_DMASR_EOL_LATE_ERR | \
XILINX_DMA_DMASR_SOF_LATE_ERR | \
XILINX_DMA_DMASR_SG_DEC_ERR | \
XILINX_DMA_DMASR_SG_SLV_ERR | \
XILINX_DMA_DMASR_EOF_EARLY_ERR | \
XILINX_DMA_DMASR_SOF_EARLY_ERR | \
XILINX_DMA_DMASR_DMA_DEC_ERR | \
XILINX_DMA_DMASR_DMA_SLAVE_ERR | \
XILINX_DMA_DMASR_DMA_INT_ERR)
/*
* Recoverable errors are DMA Internal error, SOF Early, EOF Early
* and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC
* is enabled in the h/w system.
*/
#define XILINX_VDMA_DMASR_ERR_RECOVER_MASK \
(XILINX_VDMA_DMASR_SOF_LATE_ERR | \
XILINX_VDMA_DMASR_EOF_EARLY_ERR | \
XILINX_VDMA_DMASR_SOF_EARLY_ERR | \
XILINX_VDMA_DMASR_DMA_INT_ERR)
#define XILINX_DMA_DMASR_ERR_RECOVER_MASK \
(XILINX_DMA_DMASR_SOF_LATE_ERR | \
XILINX_DMA_DMASR_EOF_EARLY_ERR | \
XILINX_DMA_DMASR_SOF_EARLY_ERR | \
XILINX_DMA_DMASR_DMA_INT_ERR)
/* Axi VDMA Flush on Fsync bits */
#define XILINX_VDMA_FLUSH_S2MM 3
#define XILINX_VDMA_FLUSH_MM2S 2
#define XILINX_VDMA_FLUSH_BOTH 1
#define XILINX_DMA_FLUSH_S2MM 3
#define XILINX_DMA_FLUSH_MM2S 2
#define XILINX_DMA_FLUSH_BOTH 1
/* Delay loop counter to prevent hardware failure */
#define XILINX_VDMA_LOOP_COUNT 1000000
#define XILINX_DMA_LOOP_COUNT 1000000
/**
* struct xilinx_vdma_desc_hw - Hardware Descriptor
......@@ -174,19 +174,19 @@ struct xilinx_vdma_tx_segment {
} __aligned(64);
/**
* struct xilinx_vdma_tx_descriptor - Per Transaction structure
* struct xilinx_dma_tx_descriptor - Per Transaction structure
* @async_tx: Async transaction descriptor
* @segments: TX segments list
* @node: Node in the channel descriptors list
*/
struct xilinx_vdma_tx_descriptor {
struct xilinx_dma_tx_descriptor {
struct dma_async_tx_descriptor async_tx;
struct list_head segments;
struct list_head node;
};
/**
* struct xilinx_vdma_chan - Driver specific VDMA channel structure
* struct xilinx_dma_chan - Driver specific DMA channel structure
* @xdev: Driver specific device structure
* @ctrl_offset: Control registers offset
* @desc_offset: TX descriptor registers offset
......@@ -211,8 +211,8 @@ struct xilinx_vdma_tx_descriptor {
* @ext_addr: Indicates 64 bit addressing is supported by dma channel
* @desc_submitcount: Descriptor h/w submitted count
*/
struct xilinx_vdma_chan {
struct xilinx_vdma_device *xdev;
struct xilinx_dma_chan {
struct xilinx_dma_device *xdev;
u32 ctrl_offset;
u32 desc_offset;
spinlock_t lock;
......@@ -238,20 +238,20 @@ struct xilinx_vdma_chan {
};
/**
* struct xilinx_vdma_device - VDMA device structure
* struct xilinx_dma_device - DMA device structure
* @regs: I/O mapped base address
* @dev: Device Structure
* @common: DMA device structure
* @chan: Driver specific VDMA channel
* @chan: Driver specific DMA channel
* @has_sg: Specifies whether Scatter-Gather is present or not
* @flush_on_fsync: Flush on frame sync
* @ext_addr: Indicates 64 bit addressing is supported by dma device
*/
struct xilinx_vdma_device {
struct xilinx_dma_device {
void __iomem *regs;
struct device *dev;
struct dma_device common;
struct xilinx_vdma_chan *chan[XILINX_VDMA_MAX_CHANS_PER_DEVICE];
struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
bool has_sg;
u32 flush_on_fsync;
bool ext_addr;
......@@ -259,51 +259,51 @@ struct xilinx_vdma_device {
/* Macros */
#define to_xilinx_chan(chan) \
container_of(chan, struct xilinx_vdma_chan, common)
#define to_vdma_tx_descriptor(tx) \
container_of(tx, struct xilinx_vdma_tx_descriptor, async_tx)
#define xilinx_vdma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
container_of(chan, struct xilinx_dma_chan, common)
#define to_dma_tx_descriptor(tx) \
container_of(tx, struct xilinx_dma_tx_descriptor, async_tx)
#define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \
cond, delay_us, timeout_us)
/* IO accessors */
static inline u32 vdma_read(struct xilinx_vdma_chan *chan, u32 reg)
static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg)
{
return ioread32(chan->xdev->regs + reg);
}
static inline void vdma_write(struct xilinx_vdma_chan *chan, u32 reg, u32 value)
static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value)
{
iowrite32(value, chan->xdev->regs + reg);
}
static inline void vdma_desc_write(struct xilinx_vdma_chan *chan, u32 reg,
static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg,
u32 value)
{
vdma_write(chan, chan->desc_offset + reg, value);
dma_write(chan, chan->desc_offset + reg, value);
}
static inline u32 vdma_ctrl_read(struct xilinx_vdma_chan *chan, u32 reg)
static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg)
{
return vdma_read(chan, chan->ctrl_offset + reg);
return dma_read(chan, chan->ctrl_offset + reg);
}
static inline void vdma_ctrl_write(struct xilinx_vdma_chan *chan, u32 reg,
static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,
u32 value)
{
vdma_write(chan, chan->ctrl_offset + reg, value);
dma_write(chan, chan->ctrl_offset + reg, value);
}
static inline void vdma_ctrl_clr(struct xilinx_vdma_chan *chan, u32 reg,
static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg,
u32 clr)
{
vdma_ctrl_write(chan, reg, vdma_ctrl_read(chan, reg) & ~clr);
dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
}
static inline void vdma_ctrl_set(struct xilinx_vdma_chan *chan, u32 reg,
static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg,
u32 set)
{
vdma_ctrl_write(chan, reg, vdma_ctrl_read(chan, reg) | set);
dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
}
/**
......@@ -317,7 +317,7 @@ static inline void vdma_ctrl_set(struct xilinx_vdma_chan *chan, u32 reg,
* multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits
* instead of a single 64 bit register write.
*/
static inline void vdma_desc_write_64(struct xilinx_vdma_chan *chan, u32 reg,
static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg,
u32 value_lsb, u32 value_msb)
{
/* Write the lsb 32 bits*/
......@@ -333,12 +333,12 @@ static inline void vdma_desc_write_64(struct xilinx_vdma_chan *chan, u32 reg,
/**
* xilinx_vdma_alloc_tx_segment - Allocate transaction segment
* @chan: Driver specific VDMA channel
* @chan: Driver specific DMA channel
*
* Return: The allocated segment on success and NULL on failure.
*/
static struct xilinx_vdma_tx_segment *
xilinx_vdma_alloc_tx_segment(struct xilinx_vdma_chan *chan)
xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_tx_segment *segment;
dma_addr_t phys;
......@@ -354,25 +354,25 @@ xilinx_vdma_alloc_tx_segment(struct xilinx_vdma_chan *chan)
/**
* xilinx_vdma_free_tx_segment - Free transaction segment
* @chan: Driver specific VDMA channel
* @segment: VDMA transaction segment
* @chan: Driver specific DMA channel
* @segment: DMA transaction segment
*/
static void xilinx_vdma_free_tx_segment(struct xilinx_vdma_chan *chan,
static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan,
struct xilinx_vdma_tx_segment *segment)
{
dma_pool_free(chan->desc_pool, segment, segment->phys);
}
/**
* xilinx_vdma_tx_descriptor - Allocate transaction descriptor
* @chan: Driver specific VDMA channel
* xilinx_dma_tx_descriptor - Allocate transaction descriptor
* @chan: Driver specific DMA channel
*
* Return: The allocated descriptor on success and NULL on failure.
*/
static struct xilinx_vdma_tx_descriptor *
xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
static struct xilinx_dma_tx_descriptor *
xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_tx_descriptor *desc;
struct xilinx_dma_tx_descriptor *desc;
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
if (!desc)
......@@ -384,13 +384,13 @@ xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
}
/**
* xilinx_vdma_free_tx_descriptor - Free transaction descriptor
* @chan: Driver specific VDMA channel
* @desc: VDMA transaction descriptor
* xilinx_dma_free_tx_descriptor - Free transaction descriptor
* @chan: Driver specific DMA channel
* @desc: DMA transaction descriptor
*/
static void
xilinx_vdma_free_tx_descriptor(struct xilinx_vdma_chan *chan,
struct xilinx_vdma_tx_descriptor *desc)
xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan,
struct xilinx_dma_tx_descriptor *desc)
{
struct xilinx_vdma_tx_segment *segment, *next;
......@@ -408,60 +408,60 @@ xilinx_vdma_free_tx_descriptor(struct xilinx_vdma_chan *chan,
/* Required functions */
/**
* xilinx_vdma_free_desc_list - Free descriptors list
* @chan: Driver specific VDMA channel
* xilinx_dma_free_desc_list - Free descriptors list
* @chan: Driver specific DMA channel
* @list: List to parse and delete the descriptor
*/
static void xilinx_vdma_free_desc_list(struct xilinx_vdma_chan *chan,
static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan,
struct list_head *list)
{
struct xilinx_vdma_tx_descriptor *desc, *next;
struct xilinx_dma_tx_descriptor *desc, *next;
list_for_each_entry_safe(desc, next, list, node) {
list_del(&desc->node);
xilinx_vdma_free_tx_descriptor(chan, desc);
xilinx_dma_free_tx_descriptor(chan, desc);
}
}
/**
* xilinx_vdma_free_descriptors - Free channel descriptors
* @chan: Driver specific VDMA channel
* xilinx_dma_free_descriptors - Free channel descriptors
* @chan: Driver specific DMA channel
*/
static void xilinx_vdma_free_descriptors(struct xilinx_vdma_chan *chan)
static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan)
{
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
xilinx_vdma_free_desc_list(chan, &chan->pending_list);
xilinx_vdma_free_desc_list(chan, &chan->done_list);
xilinx_vdma_free_desc_list(chan, &chan->active_list);
xilinx_dma_free_desc_list(chan, &chan->pending_list);
xilinx_dma_free_desc_list(chan, &chan->done_list);
xilinx_dma_free_desc_list(chan, &chan->active_list);
spin_unlock_irqrestore(&chan->lock, flags);
}
/**
* xilinx_vdma_free_chan_resources - Free channel resources
* xilinx_dma_free_chan_resources - Free channel resources
* @dchan: DMA channel
*/
static void xilinx_vdma_free_chan_resources(struct dma_chan *dchan)
static void xilinx_dma_free_chan_resources(struct dma_chan *dchan)
{
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
dev_dbg(chan->dev, "Free all channel resources.\n");
xilinx_vdma_free_descriptors(chan);
xilinx_dma_free_descriptors(chan);
dma_pool_destroy(chan->desc_pool);
chan->desc_pool = NULL;
}
/**
* xilinx_vdma_chan_desc_cleanup - Clean channel descriptors
* @chan: Driver specific VDMA channel
* xilinx_dma_chan_desc_cleanup - Clean channel descriptors
* @chan: Driver specific DMA channel
*/
static void xilinx_vdma_chan_desc_cleanup(struct xilinx_vdma_chan *chan)
static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_tx_descriptor *desc, *next;
struct xilinx_dma_tx_descriptor *desc, *next;
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
......@@ -484,32 +484,32 @@ static void xilinx_vdma_chan_desc_cleanup(struct xilinx_vdma_chan *chan)
/* Run any dependencies, then free the descriptor */
dma_run_dependencies(&desc->async_tx);
xilinx_vdma_free_tx_descriptor(chan, desc);
xilinx_dma_free_tx_descriptor(chan, desc);
}
spin_unlock_irqrestore(&chan->lock, flags);
}
/**
* xilinx_vdma_do_tasklet - Schedule completion tasklet
* @data: Pointer to the Xilinx VDMA channel structure
* xilinx_dma_do_tasklet - Schedule completion tasklet
* @data: Pointer to the Xilinx DMA channel structure
*/
static void xilinx_vdma_do_tasklet(unsigned long data)
static void xilinx_dma_do_tasklet(unsigned long data)
{
struct xilinx_vdma_chan *chan = (struct xilinx_vdma_chan *)data;
struct xilinx_dma_chan *chan = (struct xilinx_dma_chan *)data;
xilinx_vdma_chan_desc_cleanup(chan);
xilinx_dma_chan_desc_cleanup(chan);
}
/**
* xilinx_vdma_alloc_chan_resources - Allocate channel resources
* xilinx_dma_alloc_chan_resources - Allocate channel resources
* @dchan: DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_vdma_alloc_chan_resources(struct dma_chan *dchan)
static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
{
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
/* Has this channel already been allocated? */
if (chan->desc_pool)
......@@ -535,14 +535,14 @@ static int xilinx_vdma_alloc_chan_resources(struct dma_chan *dchan)
}
/**
* xilinx_vdma_tx_status - Get VDMA transaction status
* xilinx_dma_tx_status - Get DMA transaction status
* @dchan: DMA channel
* @cookie: Transaction identifier
* @txstate: Transaction state
*
* Return: DMA transaction status
*/
static enum dma_status xilinx_vdma_tx_status(struct dma_chan *dchan,
static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
......@@ -550,73 +550,73 @@ static enum dma_status xilinx_vdma_tx_status(struct dma_chan *dchan,
}
/**
* xilinx_vdma_is_running - Check if VDMA channel is running
* @chan: Driver specific VDMA channel
* xilinx_dma_is_running - Check if DMA channel is running
* @chan: Driver specific DMA channel
*
* Return: '1' if running, '0' if not.
*/
static bool xilinx_vdma_is_running(struct xilinx_vdma_chan *chan)
static bool xilinx_dma_is_running(struct xilinx_dma_chan *chan)
{
return !(vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) &
XILINX_VDMA_DMASR_HALTED) &&
(vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR) &
XILINX_VDMA_DMACR_RUNSTOP);
return !(dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
XILINX_DMA_DMASR_HALTED) &&
(dma_ctrl_read(chan, XILINX_DMA_REG_DMACR) &
XILINX_DMA_DMACR_RUNSTOP);
}
/**
* xilinx_vdma_is_idle - Check if VDMA channel is idle
* @chan: Driver specific VDMA channel
* xilinx_dma_is_idle - Check if DMA channel is idle
* @chan: Driver specific DMA channel
*
* Return: '1' if idle, '0' if not.
*/
static bool xilinx_vdma_is_idle(struct xilinx_vdma_chan *chan)
static bool xilinx_dma_is_idle(struct xilinx_dma_chan *chan)
{
return vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) &
XILINX_VDMA_DMASR_IDLE;
return dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) &
XILINX_DMA_DMASR_IDLE;
}
/**
* xilinx_vdma_halt - Halt VDMA channel
* @chan: Driver specific VDMA channel
* xilinx_dma_halt - Halt DMA channel
* @chan: Driver specific DMA channel
*/
static void xilinx_vdma_halt(struct xilinx_vdma_chan *chan)
static void xilinx_dma_halt(struct xilinx_dma_chan *chan)
{
int err;
u32 val;
vdma_ctrl_clr(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RUNSTOP);
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
/* Wait for the hardware to halt */
err = xilinx_vdma_poll_timeout(chan, XILINX_VDMA_REG_DMASR, val,
(val & XILINX_VDMA_DMASR_HALTED), 0,
XILINX_VDMA_LOOP_COUNT);
err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
(val & XILINX_DMA_DMASR_HALTED), 0,
XILINX_DMA_LOOP_COUNT);
if (err) {
dev_err(chan->dev, "Cannot stop channel %p: %x\n",
chan, vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR));
chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
chan->err = true;
}
}
/**
* xilinx_vdma_start - Start VDMA channel
* @chan: Driver specific VDMA channel
* xilinx_dma_start - Start DMA channel
* @chan: Driver specific DMA channel
*/
static void xilinx_vdma_start(struct xilinx_vdma_chan *chan)
static void xilinx_dma_start(struct xilinx_dma_chan *chan)
{
int err;
u32 val;
vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RUNSTOP);
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP);
/* Wait for the hardware to start */
err = xilinx_vdma_poll_timeout(chan, XILINX_VDMA_REG_DMASR, val,
!(val & XILINX_VDMA_DMASR_HALTED), 0,
XILINX_VDMA_LOOP_COUNT);
err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
!(val & XILINX_DMA_DMASR_HALTED), 0,
XILINX_DMA_LOOP_COUNT);
if (err) {
dev_err(chan->dev, "Cannot start channel %p: %x\n",
chan, vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR));
chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
chan->err = true;
}
......@@ -626,10 +626,10 @@ static void xilinx_vdma_start(struct xilinx_vdma_chan *chan)
* xilinx_vdma_start_transfer - Starts VDMA transfer
* @chan: Driver specific channel struct pointer
*/
static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_config *config = &chan->config;
struct xilinx_vdma_tx_descriptor *desc, *tail_desc;
struct xilinx_dma_tx_descriptor *desc, *tail_desc;
u32 reg;
struct xilinx_vdma_tx_segment *tail_segment;
......@@ -641,16 +641,16 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
return;
desc = list_first_entry(&chan->pending_list,
struct xilinx_vdma_tx_descriptor, node);
struct xilinx_dma_tx_descriptor, node);
tail_desc = list_last_entry(&chan->pending_list,
struct xilinx_vdma_tx_descriptor, node);
struct xilinx_dma_tx_descriptor, node);
tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_vdma_tx_segment, node);
/* If it is SG mode and hardware is busy, cannot submit */
if (chan->has_sg && xilinx_vdma_is_running(chan) &&
!xilinx_vdma_is_idle(chan)) {
if (chan->has_sg && xilinx_dma_is_running(chan) &&
!xilinx_dma_is_idle(chan)) {
dev_dbg(chan->dev, "DMA controller still busy\n");
return;
}
......@@ -660,19 +660,19 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
* done, start new transfers
*/
if (chan->has_sg)
vdma_ctrl_write(chan, XILINX_VDMA_REG_CURDESC,
dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
desc->async_tx.phys);
/* Configure the hardware using info in the config structure */
reg = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR);
reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
if (config->frm_cnt_en)
reg |= XILINX_VDMA_DMACR_FRAMECNT_EN;
reg |= XILINX_DMA_DMACR_FRAMECNT_EN;
else
reg &= ~XILINX_VDMA_DMACR_FRAMECNT_EN;
reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
/* Configure channel to allow number frame buffers */
vdma_ctrl_write(chan, XILINX_VDMA_REG_FRMSTORE,
dma_ctrl_write(chan, XILINX_DMA_REG_FRMSTORE,
chan->desc_pendingcount);
/*
......@@ -680,34 +680,34 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
* In direct register mode, if not parking, enable circular mode
*/
if (chan->has_sg || !config->park)
reg |= XILINX_VDMA_DMACR_CIRC_EN;
reg |= XILINX_DMA_DMACR_CIRC_EN;
if (config->park)
reg &= ~XILINX_VDMA_DMACR_CIRC_EN;
reg &= ~XILINX_DMA_DMACR_CIRC_EN;
vdma_ctrl_write(chan, XILINX_VDMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
if (config->park && (config->park_frm >= 0) &&
(config->park_frm < chan->num_frms)) {
if (chan->direction == DMA_MEM_TO_DEV)
vdma_write(chan, XILINX_VDMA_REG_PARK_PTR,
dma_write(chan, XILINX_DMA_REG_PARK_PTR,
config->park_frm <<
XILINX_VDMA_PARK_PTR_RD_REF_SHIFT);
XILINX_DMA_PARK_PTR_RD_REF_SHIFT);
else
vdma_write(chan, XILINX_VDMA_REG_PARK_PTR,
dma_write(chan, XILINX_DMA_REG_PARK_PTR,
config->park_frm <<
XILINX_VDMA_PARK_PTR_WR_REF_SHIFT);
XILINX_DMA_PARK_PTR_WR_REF_SHIFT);
}
/* Start the hardware */
xilinx_vdma_start(chan);
xilinx_dma_start(chan);
if (chan->err)
return;
/* Start the transfer */
if (chan->has_sg) {
vdma_ctrl_write(chan, XILINX_VDMA_REG_TAILDESC,
dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
tail_segment->phys);
} else {
struct xilinx_vdma_tx_segment *segment, *last = NULL;
......@@ -734,10 +734,10 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
return;
/* HW expects these parameters to be same for one transaction */
vdma_desc_write(chan, XILINX_VDMA_REG_HSIZE, last->hw.hsize);
vdma_desc_write(chan, XILINX_VDMA_REG_FRMDLY_STRIDE,
vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize);
vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE,
last->hw.stride);
vdma_desc_write(chan, XILINX_VDMA_REG_VSIZE, last->hw.vsize);
vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize);
}
if (!chan->has_sg) {
......@@ -754,12 +754,12 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
}
/**
* xilinx_vdma_issue_pending - Issue pending transactions
* xilinx_dma_issue_pending - Issue pending transactions
* @dchan: DMA channel
*/
static void xilinx_vdma_issue_pending(struct dma_chan *dchan)
static void xilinx_dma_issue_pending(struct dma_chan *dchan)
{
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
......@@ -768,14 +768,14 @@ static void xilinx_vdma_issue_pending(struct dma_chan *dchan)
}
/**
* xilinx_vdma_complete_descriptor - Mark the active descriptor as complete
* xilinx_dma_complete_descriptor - Mark the active descriptor as complete
* @chan : xilinx DMA channel
*
* CONTEXT: hardirq
*/
static void xilinx_vdma_complete_descriptor(struct xilinx_vdma_chan *chan)
static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
{
struct xilinx_vdma_tx_descriptor *desc, *next;
struct xilinx_dma_tx_descriptor *desc, *next;
/* This function was invoked with lock held */
if (list_empty(&chan->active_list))
......@@ -789,27 +789,27 @@ static void xilinx_vdma_complete_descriptor(struct xilinx_vdma_chan *chan)
}
/**
* xilinx_vdma_reset - Reset VDMA channel
* @chan: Driver specific VDMA channel
* xilinx_dma_reset - Reset DMA channel
* @chan: Driver specific DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_vdma_reset(struct xilinx_vdma_chan *chan)
static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
{
int err;
u32 tmp;
vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RESET);
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET);
/* Wait for the hardware to finish reset */
err = xilinx_vdma_poll_timeout(chan, XILINX_VDMA_REG_DMACR, tmp,
!(tmp & XILINX_VDMA_DMACR_RESET), 0,
XILINX_VDMA_LOOP_COUNT);
err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
!(tmp & XILINX_DMA_DMACR_RESET), 0,
XILINX_DMA_LOOP_COUNT);
if (err) {
dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR),
vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR));
dma_ctrl_read(chan, XILINX_DMA_REG_DMACR),
dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
return -ETIMEDOUT;
}
......@@ -819,48 +819,48 @@ static int xilinx_vdma_reset(struct xilinx_vdma_chan *chan)
}
/**
* xilinx_vdma_chan_reset - Reset VDMA channel and enable interrupts
* @chan: Driver specific VDMA channel
* xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
* @chan: Driver specific DMA channel
*
* Return: '0' on success and failure value on error
*/
static int xilinx_vdma_chan_reset(struct xilinx_vdma_chan *chan)
static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan)
{
int err;
/* Reset VDMA */
err = xilinx_vdma_reset(chan);
err = xilinx_dma_reset(chan);
if (err)
return err;
/* Enable interrupts */
vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR,
XILINX_VDMA_DMAXR_ALL_IRQ_MASK);
dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
XILINX_DMA_DMAXR_ALL_IRQ_MASK);
return 0;
}
/**
* xilinx_vdma_irq_handler - VDMA Interrupt handler
* xilinx_dma_irq_handler - DMA Interrupt handler
* @irq: IRQ number
* @data: Pointer to the Xilinx VDMA channel structure
* @data: Pointer to the Xilinx DMA channel structure
*
* Return: IRQ_HANDLED/IRQ_NONE
*/
static irqreturn_t xilinx_vdma_irq_handler(int irq, void *data)
static irqreturn_t xilinx_dma_irq_handler(int irq, void *data)
{
struct xilinx_vdma_chan *chan = data;
struct xilinx_dma_chan *chan = data;
u32 status;
/* Read the status and ack the interrupts. */
status = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR);
if (!(status & XILINX_VDMA_DMAXR_ALL_IRQ_MASK))
status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR);
if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK))
return IRQ_NONE;
vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR,
status & XILINX_VDMA_DMAXR_ALL_IRQ_MASK);
dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
status & XILINX_DMA_DMAXR_ALL_IRQ_MASK);
if (status & XILINX_VDMA_DMASR_ERR_IRQ) {
if (status & XILINX_DMA_DMASR_ERR_IRQ) {
/*
* An error occurred. If C_FLUSH_ON_FSYNC is enabled and the
* error is recoverable, ignore it. Otherwise flag the error.
......@@ -868,23 +868,23 @@ static irqreturn_t xilinx_vdma_irq_handler(int irq, void *data)
* Only recoverable errors can be cleared in the DMASR register,
* make sure not to write to other error bits to 1.
*/
u32 errors = status & XILINX_VDMA_DMASR_ALL_ERR_MASK;
u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK;
vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR,
errors & XILINX_VDMA_DMASR_ERR_RECOVER_MASK);
dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK);
if (!chan->flush_on_fsync ||
(errors & ~XILINX_VDMA_DMASR_ERR_RECOVER_MASK)) {
(errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) {
dev_err(chan->dev,
"Channel %p has errors %x, cdr %x tdr %x\n",
chan, errors,
vdma_ctrl_read(chan, XILINX_VDMA_REG_CURDESC),
vdma_ctrl_read(chan, XILINX_VDMA_REG_TAILDESC));
dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC),
dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC));
chan->err = true;
}
}
if (status & XILINX_VDMA_DMASR_DLY_CNT_IRQ) {
if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) {
/*
* Device takes too long to do the transfer when user requires
* responsiveness.
......@@ -892,9 +892,9 @@ static irqreturn_t xilinx_vdma_irq_handler(int irq, void *data)
dev_dbg(chan->dev, "Inter-packet latency too long\n");
}
if (status & XILINX_VDMA_DMASR_FRM_CNT_IRQ) {
if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) {
spin_lock(&chan->lock);
xilinx_vdma_complete_descriptor(chan);
xilinx_dma_complete_descriptor(chan);
xilinx_vdma_start_transfer(chan);
spin_unlock(&chan->lock);
}
......@@ -908,11 +908,11 @@ static irqreturn_t xilinx_vdma_irq_handler(int irq, void *data)
* @chan: Driver specific dma channel
* @desc: dma transaction descriptor
*/
static void append_desc_queue(struct xilinx_vdma_chan *chan,
struct xilinx_vdma_tx_descriptor *desc)
static void append_desc_queue(struct xilinx_dma_chan *chan,
struct xilinx_dma_tx_descriptor *desc)
{
struct xilinx_vdma_tx_segment *tail_segment;
struct xilinx_vdma_tx_descriptor *tail_desc;
struct xilinx_dma_tx_descriptor *tail_desc;
if (list_empty(&chan->pending_list))
goto append;
......@@ -922,7 +922,7 @@ static void append_desc_queue(struct xilinx_vdma_chan *chan,
* that already exists in memory.
*/
tail_desc = list_last_entry(&chan->pending_list,
struct xilinx_vdma_tx_descriptor, node);
struct xilinx_dma_tx_descriptor, node);
tail_segment = list_last_entry(&tail_desc->segments,
struct xilinx_vdma_tx_segment, node);
tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
......@@ -943,15 +943,15 @@ static void append_desc_queue(struct xilinx_vdma_chan *chan,
}
/**
* xilinx_vdma_tx_submit - Submit DMA transaction
* xilinx_dma_tx_submit - Submit DMA transaction
* @tx: Async transaction descriptor
*
* Return: cookie value on success and failure value on error
*/
static dma_cookie_t xilinx_vdma_tx_submit(struct dma_async_tx_descriptor *tx)
static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct xilinx_vdma_tx_descriptor *desc = to_vdma_tx_descriptor(tx);
struct xilinx_vdma_chan *chan = to_xilinx_chan(tx->chan);
struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan);
dma_cookie_t cookie;
unsigned long flags;
int err;
......@@ -961,7 +961,7 @@ static dma_cookie_t xilinx_vdma_tx_submit(struct dma_async_tx_descriptor *tx)
* If reset fails, need to hard reset the system.
* Channel is no longer functional
*/
err = xilinx_vdma_chan_reset(chan);
err = xilinx_dma_chan_reset(chan);
if (err < 0)
return err;
}
......@@ -992,8 +992,8 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
struct dma_interleaved_template *xt,
unsigned long flags)
{
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_vdma_tx_descriptor *desc;
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
struct xilinx_vdma_tx_segment *segment, *prev = NULL;
struct xilinx_vdma_desc_hw *hw;
......@@ -1007,12 +1007,12 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
return NULL;
/* Allocate a transaction descriptor. */
desc = xilinx_vdma_alloc_tx_descriptor(chan);
desc = xilinx_dma_alloc_tx_descriptor(chan);
if (!desc)
return NULL;
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
desc->async_tx.tx_submit = xilinx_vdma_tx_submit;
desc->async_tx.tx_submit = xilinx_dma_tx_submit;
async_tx_ack(&desc->async_tx);
/* Allocate the link descriptor from DMA pool */
......@@ -1025,9 +1025,9 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
hw->vsize = xt->numf;
hw->hsize = xt->sgl[0].size;
hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) <<
XILINX_VDMA_FRMDLY_STRIDE_STRIDE_SHIFT;
XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT;
hw->stride |= chan->config.frm_dly <<
XILINX_VDMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT;
if (xt->dir != DMA_MEM_TO_DEV) {
if (chan->ext_addr) {
......@@ -1058,29 +1058,29 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
return &desc->async_tx;
error:
xilinx_vdma_free_tx_descriptor(chan, desc);
xilinx_dma_free_tx_descriptor(chan, desc);
return NULL;
}
/**
* xilinx_vdma_terminate_all - Halt the channel and free descriptors
* @chan: Driver specific VDMA Channel pointer
* xilinx_dma_terminate_all - Halt the channel and free descriptors
* @chan: Driver specific DMA Channel pointer
*/
static int xilinx_vdma_terminate_all(struct dma_chan *dchan)
static int xilinx_dma_terminate_all(struct dma_chan *dchan)
{
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
/* Halt the DMA engine */
xilinx_vdma_halt(chan);
xilinx_dma_halt(chan);
/* Remove and free all of the descriptors in the lists */
xilinx_vdma_free_descriptors(chan);
xilinx_dma_free_descriptors(chan);
return 0;
}
/**
* xilinx_vdma_channel_set_config - Configure VDMA channel
* xilinx_dma_channel_set_config - Configure VDMA channel
* Run-time configuration for Axi VDMA, supports:
* . halt the channel
* . configure interrupt coalescing and inter-packet delay threshold
......@@ -1095,13 +1095,13 @@ static int xilinx_vdma_terminate_all(struct dma_chan *dchan)
int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
struct xilinx_vdma_config *cfg)
{
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
u32 dmacr;
if (cfg->reset)
return xilinx_vdma_chan_reset(chan);
return xilinx_dma_chan_reset(chan);
dmacr = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR);
dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
chan->config.frm_dly = cfg->frm_dly;
chan->config.park = cfg->park;
......@@ -1111,8 +1111,8 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
chan->config.master = cfg->master;
if (cfg->gen_lock && chan->genlock) {
dmacr |= XILINX_VDMA_DMACR_GENLOCK_EN;
dmacr |= cfg->master << XILINX_VDMA_DMACR_MASTER_SHIFT;
dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
}
chan->config.frm_cnt_en = cfg->frm_cnt_en;
......@@ -1124,21 +1124,21 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
chan->config.coalesc = cfg->coalesc;
chan->config.delay = cfg->delay;
if (cfg->coalesc <= XILINX_VDMA_DMACR_FRAME_COUNT_MAX) {
dmacr |= cfg->coalesc << XILINX_VDMA_DMACR_FRAME_COUNT_SHIFT;
if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
chan->config.coalesc = cfg->coalesc;
}
if (cfg->delay <= XILINX_VDMA_DMACR_DELAY_MAX) {
dmacr |= cfg->delay << XILINX_VDMA_DMACR_DELAY_SHIFT;
if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
chan->config.delay = cfg->delay;
}
/* FSync Source selection */
dmacr &= ~XILINX_VDMA_DMACR_FSYNCSRC_MASK;
dmacr |= cfg->ext_fsync << XILINX_VDMA_DMACR_FSYNCSRC_SHIFT;
dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK;
dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT;
vdma_ctrl_write(chan, XILINX_VDMA_REG_DMACR, dmacr);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
return 0;
}
......@@ -1149,14 +1149,14 @@ EXPORT_SYMBOL(xilinx_vdma_channel_set_config);
*/
/**
* xilinx_vdma_chan_remove - Per Channel remove function
* @chan: Driver specific VDMA channel
* xilinx_dma_chan_remove - Per Channel remove function
* @chan: Driver specific DMA channel
*/
static void xilinx_vdma_chan_remove(struct xilinx_vdma_chan *chan)
static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan)
{
/* Disable all interrupts */
vdma_ctrl_clr(chan, XILINX_VDMA_REG_DMACR,
XILINX_VDMA_DMAXR_ALL_IRQ_MASK);
dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
XILINX_DMA_DMAXR_ALL_IRQ_MASK);
if (chan->irq > 0)
free_irq(chan->irq, chan);
......@@ -1167,7 +1167,7 @@ static void xilinx_vdma_chan_remove(struct xilinx_vdma_chan *chan)
}
/**
* xilinx_vdma_chan_probe - Per Channel Probing
* xilinx_dma_chan_probe - Per Channel Probing
* It get channel features from the device tree entry and
* initialize special channel handling routines
*
......@@ -1176,10 +1176,10 @@ static void xilinx_vdma_chan_remove(struct xilinx_vdma_chan *chan)
*
* Return: '0' on success and failure value on error
*/
static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev,
static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
struct device_node *node)
{
struct xilinx_vdma_chan *chan;
struct xilinx_dma_chan *chan;
bool has_dre = false;
u32 value, width;
int err;
......@@ -1223,22 +1223,22 @@ static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev,
chan->direction = DMA_MEM_TO_DEV;
chan->id = 0;
chan->ctrl_offset = XILINX_VDMA_MM2S_CTRL_OFFSET;
chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET;
if (xdev->flush_on_fsync == XILINX_VDMA_FLUSH_BOTH ||
xdev->flush_on_fsync == XILINX_VDMA_FLUSH_MM2S)
if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S)
chan->flush_on_fsync = true;
} else if (of_device_is_compatible(node,
"xlnx,axi-vdma-s2mm-channel")) {
chan->direction = DMA_DEV_TO_MEM;
chan->id = 1;
chan->ctrl_offset = XILINX_VDMA_S2MM_CTRL_OFFSET;
chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET;
if (xdev->flush_on_fsync == XILINX_VDMA_FLUSH_BOTH ||
xdev->flush_on_fsync == XILINX_VDMA_FLUSH_S2MM)
if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH ||
xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM)
chan->flush_on_fsync = true;
} else {
dev_err(xdev->dev, "Invalid channel compatible node\n");
......@@ -1247,15 +1247,15 @@ static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev,
/* Request the interrupt */
chan->irq = irq_of_parse_and_map(node, 0);
err = request_irq(chan->irq, xilinx_vdma_irq_handler, IRQF_SHARED,
"xilinx-vdma-controller", chan);
err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
"xilinx-dma-controller", chan);
if (err) {
dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
return err;
}
/* Initialize the tasklet */
tasklet_init(&chan->tasklet, xilinx_vdma_do_tasklet,
tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet,
(unsigned long)chan);
/*
......@@ -1268,7 +1268,7 @@ static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev,
xdev->chan[chan->id] = chan;
/* Reset the channel */
err = xilinx_vdma_chan_reset(chan);
err = xilinx_dma_chan_reset(chan);
if (err < 0) {
dev_err(xdev->dev, "Reset channel failed\n");
return err;
......@@ -1287,25 +1287,25 @@ static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev,
static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
struct of_dma *ofdma)
{
struct xilinx_vdma_device *xdev = ofdma->of_dma_data;
struct xilinx_dma_device *xdev = ofdma->of_dma_data;
int chan_id = dma_spec->args[0];
if (chan_id >= XILINX_VDMA_MAX_CHANS_PER_DEVICE)
if (chan_id >= XILINX_DMA_MAX_CHANS_PER_DEVICE)
return NULL;
return dma_get_slave_channel(&xdev->chan[chan_id]->common);
}
/**
* xilinx_vdma_probe - Driver probe function
* xilinx_dma_probe - Driver probe function
* @pdev: Pointer to the platform_device structure
*
* Return: '0' on success and failure value on error
*/
static int xilinx_vdma_probe(struct platform_device *pdev)
static int xilinx_dma_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct xilinx_vdma_device *xdev;
struct xilinx_dma_device *xdev;
struct device_node *child;
struct resource *io;
u32 num_frames, addr_width;
......@@ -1358,25 +1358,25 @@ static int xilinx_vdma_probe(struct platform_device *pdev)
dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
xdev->common.device_alloc_chan_resources =
xilinx_vdma_alloc_chan_resources;
xilinx_dma_alloc_chan_resources;
xdev->common.device_free_chan_resources =
xilinx_vdma_free_chan_resources;
xilinx_dma_free_chan_resources;
xdev->common.device_prep_interleaved_dma =
xilinx_vdma_dma_prep_interleaved;
xdev->common.device_terminate_all = xilinx_vdma_terminate_all;
xdev->common.device_tx_status = xilinx_vdma_tx_status;
xdev->common.device_issue_pending = xilinx_vdma_issue_pending;
xdev->common.device_terminate_all = xilinx_dma_terminate_all;
xdev->common.device_tx_status = xilinx_dma_tx_status;
xdev->common.device_issue_pending = xilinx_dma_issue_pending;
platform_set_drvdata(pdev, xdev);
/* Initialize the channels */
for_each_child_of_node(node, child) {
err = xilinx_vdma_chan_probe(xdev, child);
err = xilinx_dma_chan_probe(xdev, child);
if (err < 0)
goto error;
}
for (i = 0; i < XILINX_VDMA_MAX_CHANS_PER_DEVICE; i++)
for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
if (xdev->chan[i])
xdev->chan[i]->num_frms = num_frames;
......@@ -1396,48 +1396,48 @@ static int xilinx_vdma_probe(struct platform_device *pdev)
return 0;
error:
for (i = 0; i < XILINX_VDMA_MAX_CHANS_PER_DEVICE; i++)
for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
if (xdev->chan[i])
xilinx_vdma_chan_remove(xdev->chan[i]);
xilinx_dma_chan_remove(xdev->chan[i]);
return err;
}
/**
* xilinx_vdma_remove - Driver remove function
* xilinx_dma_remove - Driver remove function
* @pdev: Pointer to the platform_device structure
*
* Return: Always '0'
*/
static int xilinx_vdma_remove(struct platform_device *pdev)
static int xilinx_dma_remove(struct platform_device *pdev)
{
struct xilinx_vdma_device *xdev = platform_get_drvdata(pdev);
struct xilinx_dma_device *xdev = platform_get_drvdata(pdev);
int i;
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&xdev->common);
for (i = 0; i < XILINX_VDMA_MAX_CHANS_PER_DEVICE; i++)
for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
if (xdev->chan[i])
xilinx_vdma_chan_remove(xdev->chan[i]);
xilinx_dma_chan_remove(xdev->chan[i]);
return 0;
}
static const struct of_device_id xilinx_vdma_of_ids[] = {
static const struct of_device_id xilinx_dma_of_ids[] = {
{ .compatible = "xlnx,axi-vdma-1.00.a",},
{}
};
MODULE_DEVICE_TABLE(of, xilinx_vdma_of_ids);
MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids);
static struct platform_driver xilinx_vdma_driver = {
.driver = {
.name = "xilinx-vdma",
.of_match_table = xilinx_vdma_of_ids,
.of_match_table = xilinx_dma_of_ids,
},
.probe = xilinx_vdma_probe,
.remove = xilinx_vdma_remove,
.probe = xilinx_dma_probe,
.remove = xilinx_dma_remove,
};
module_platform_driver(xilinx_vdma_driver);
......
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