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Commit 443f18d0 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Mauro Carvalho Chehab
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[media] drx-j: CodingStyle fixes 

Do the automatic CodingStyle fixes found at Lindent.

No functional changes.
Acked-by: default avatarDevin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent ca3355a9
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Showing with 26522 additions and 21562 deletions
drivers/media/dvb-frontends/drx39xyj/bsp_host.h
View file @ 443f18d0
......@@ -50,7 +50,6 @@ extern "C" {
TYPEDEFS
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
......@@ -58,17 +57,17 @@ DEFINES
/*-------------------------------------------------------------------------
Exported FUNCTIONS
-------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_HST_Init( void );
DRXStatus_t DRXBSP_HST_Init(void);
DRXStatus_t DRXBSP_HST_Term( void );
DRXStatus_t DRXBSP_HST_Term(void);
void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n);
void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n);
int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n);
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n);
u32_t DRXBSP_HST_Clock( void );
u32_t DRXBSP_HST_Clock(void);
DRXStatus_t DRXBSP_HST_Sleep( u32_t n );
DRXStatus_t DRXBSP_HST_Sleep(u32_t n);
/*-------------------------------------------------------------------------
THE END
......@@ -76,5 +75,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXBSP_HOST_H__ */
#endif /* __DRXBSP_HOST_H__ */
drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h
View file @ 443f18d0
......@@ -59,7 +59,7 @@ TYPEDEFS
* \typedef I2Caddr_t
* \brief I2C device address (7-bit or 10-bit)
*/
typedef u16_t I2Caddr_t;
typedef u16_t I2Caddr_t;
/**
* \typedef I2CdevId_t
......@@ -71,7 +71,7 @@ typedef u16_t I2Caddr_t;
* I2C bus.
*
*/
typedef u16_t I2CdevId_t;
typedef u16_t I2CdevId_t;
/**
* \struct _I2CDeviceAddr_t
......@@ -81,11 +81,14 @@ typedef u16_t I2CdevId_t;
* The userData pointer can be used for application specific purposes.
*
*/
struct _I2CDeviceAddr_t {
I2Caddr_t i2cAddr; /**< The I2C address of the device. */
I2CdevId_t i2cDevId; /**< The device identifier. */
void *userData; /**< User data pointer */
};
struct _I2CDeviceAddr_t {
I2Caddr_t i2cAddr;
/**< The I2C address of the device. */
I2CdevId_t i2cDevId;
/**< The device identifier. */
void *userData;
/**< User data pointer */
};
/**
* \typedef I2CDeviceAddr_t
......@@ -94,13 +97,13 @@ struct _I2CDeviceAddr_t {
* This structure contains the I2C address and the device ID.
*
*/
typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t;
typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t;
/**
* \typedef pI2CDeviceAddr_t
* \brief Pointer to I2C device parameters.
*/
typedef I2CDeviceAddr_t *pI2CDeviceAddr_t;
typedef I2CDeviceAddr_t *pI2CDeviceAddr_t;
/*------------------------------------------------------------------------------
DEFINES
......@@ -133,7 +136,6 @@ STRUCTS
Exported FUNCTIONS
------------------------------------------------------------------------------*/
/**
* \fn DRXBSP_I2C_Init()
* \brief Initialize I2C communication module.
......@@ -141,8 +143,7 @@ Exported FUNCTIONS
* \retval DRX_STS_OK Initialization successful.
* \retval DRX_STS_ERROR Initialization failed.
*/
DRXStatus_t DRXBSP_I2C_Init( void );
DRXStatus_t DRXBSP_I2C_Init(void);
/**
* \fn DRXBSP_I2C_Term()
......@@ -151,7 +152,7 @@ DRXStatus_t DRXBSP_I2C_Init( void );
* \retval DRX_STS_OK Termination successful.
* \retval DRX_STS_ERROR Termination failed.
*/
DRXStatus_t DRXBSP_I2C_Term( void );
DRXStatus_t DRXBSP_I2C_Term(void);
/**
* \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
......@@ -183,13 +184,11 @@ DRXStatus_t DRXBSP_I2C_Term( void );
* The device ID can be useful if several devices share an I2C address.
* It can be used to control a "switch" on the I2C bus to the correct device.
*/
DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData);
DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount, pu8_t rData);
/**
* \fn DRXBSP_I2C_ErrorText()
......@@ -198,14 +197,13 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
*
* \return char* Pointer to human readable error text.
*/
char* DRXBSP_I2C_ErrorText( void );
char *DRXBSP_I2C_ErrorText(void);
/**
* \var DRX_I2C_Error_g;
* \brief I2C specific error codes, platform dependent.
*/
extern int DRX_I2C_Error_g;
extern int DRX_I2C_Error_g;
/*------------------------------------------------------------------------------
THE END
......@@ -213,4 +211,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __BSPI2C_H__ */
#endif /* __BSPI2C_H__ */
drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h
View file @ 443f18d0
......@@ -51,24 +51,23 @@ extern "C" {
DEFINES
------------------------------------------------------------------------------*/
/* Sub-mode bits should be adjacent and incremental */
#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
/* Sub-mode bits should be adjacent and incremental */
#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
#define TUNER_MODE_SUB_MAX 8
#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
......@@ -80,92 +79,90 @@ DEFINES
TYPEDEFS
------------------------------------------------------------------------------*/
typedef u32_t TUNERMode_t;
typedef pu32_t pTUNERMode_t;
typedef char* TUNERSubMode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t;
typedef enum {
TUNER_LOCKED,
TUNER_NOT_LOCKED
typedef u32_t TUNERMode_t;
typedef pu32_t pTUNERMode_t;
} TUNERLockStatus_t, *pTUNERLockStatus_t;
typedef char *TUNERSubMode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t;
typedef enum {
typedef struct {
TUNER_LOCKED,
TUNER_NOT_LOCKED
} TUNERLockStatus_t, *pTUNERLockStatus_t;
char *name; /* Tuner brand & type name */
DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */
DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */
typedef struct {
u8_t subMode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/
u8_t subModes; /* Number of available sub-modes */
char *name; /* Tuner brand & type name */
DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */
DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */
/* The following fields will be either 0, NULL or FALSE and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
Bool_t programmed; /* only valid if selfCheck is OK */
DRXFrequency_t RFfrequency; /* only valid if programmed */
DRXFrequency_t IFfrequency; /* only valid if programmed */
u8_t subMode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */
u8_t subModes; /* Number of available sub-modes */
void* myUserData; /* pointer to associated demod instance */
u16_t myCapabilities; /* value for storing application flags */
/* The following fields will be either 0, NULL or FALSE and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
Bool_t programmed; /* only valid if selfCheck is OK */
DRXFrequency_t RFfrequency; /* only valid if programmed */
DRXFrequency_t IFfrequency; /* only valid if programmed */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
void *myUserData; /* pointer to associated demod instance */
u16_t myCapabilities; /* value for storing application flags */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
/*
* Generic functions for DRX devices.
*/
typedef struct TUNERInstance_s *pTUNERInstance_t;
typedef DRXStatus_t (*TUNEROpenFunc_t)( pTUNERInstance_t tuner );
typedef DRXStatus_t (*TUNERCloseFunc_t)( pTUNERInstance_t tuner );
typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency );
typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency );
typedef DRXStatus_t (*TUNERLockStatusFunc_t)( pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat );
typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData );
typedef struct
{
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
} TUNERFunc_t, *pTUNERFunc_t;
typedef struct TUNERInstance_s {
I2CDeviceAddr_t myI2CDevAddr;
pTUNERCommonAttr_t myCommonAttr;
void* myExtAttr;
pTUNERFunc_t myFunct;
} TUNERInstance_t;
typedef struct TUNERInstance_s *pTUNERInstance_t;
typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner);
typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner);
typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t
frequency);
typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t
RFfrequency,
pDRXFrequency_t
IFfrequency);
typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner,
pTUNERLockStatus_t
lockStat);
typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner,
pI2CDeviceAddr_t
wDevAddr, u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t
rDevAddr, u16_t rCount,
pu8_t rData);
typedef struct {
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
} TUNERFunc_t, *pTUNERFunc_t;
typedef struct TUNERInstance_s {
I2CDeviceAddr_t myI2CDevAddr;
pTUNERCommonAttr_t myCommonAttr;
void *myExtAttr;
pTUNERFunc_t myFunct;
} TUNERInstance_t;
/*------------------------------------------------------------------------------
ENUM
......@@ -175,34 +172,32 @@ ENUM
STRUCTS
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Exported FUNCTIONS
------------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner );
DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner);
DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner );
DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner);
DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency );
DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency);
DRXStatus_t DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency );
DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency);
DRXStatus_t DRXBSP_TUNER_LockStatus( pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat );
DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat);
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData);
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount, pu8_t rData);
/*------------------------------------------------------------------------------
THE END
......@@ -210,6 +205,5 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXBSP_TUNER_H__ */
#endif /* __DRXBSP_TUNER_H__ */
/* End of file */
drivers/media/dvb-frontends/drx39xyj/bsp_types.h
View file @ 443f18d0
......@@ -56,114 +56,113 @@ TYPEDEFS
* \typedef unsigned char u8_t
* \brief type definition of an unsigned 8 bits integer
*/
typedef unsigned char u8_t;
typedef unsigned char u8_t;
/**
* \typedef char s8_t
* \brief type definition of a signed 8 bits integer
*/
typedef char s8_t;
typedef char s8_t;
/**
* \typedef unsigned short u16_t *pu16_t
* \brief type definition of an unsigned 16 bits integer
*/
typedef unsigned short u16_t;
typedef unsigned short u16_t;
/**
* \typedef short s16_t
* \brief type definition of a signed 16 bits integer
*/
typedef short s16_t;
typedef short s16_t;
/**
* \typedef unsigned long u32_t
* \brief type definition of an unsigned 32 bits integer
*/
typedef unsigned long u32_t;
typedef unsigned long u32_t;
/**
* \typedef long s32_t
* \brief type definition of a signed 32 bits integer
*/
typedef long s32_t;
typedef long s32_t;
/*
* \typedef struct ... u64_t
* \brief type definition of an usigned 64 bits integer
*/
typedef struct {
u32_t MSLW;
u32_t LSLW;
} u64_t;
typedef struct {
u32_t MSLW;
u32_t LSLW;
} u64_t;
/*
* \typedef struct ... i64_t
* \brief type definition of a signed 64 bits integer
*/
typedef struct {
s32_t MSLW;
u32_t LSLW;
} s64_t;
typedef struct {
s32_t MSLW;
u32_t LSLW;
} s64_t;
/**
* \typedef u8_t *pu8_t
* \brief type definition of pointer to an unsigned 8 bits integer
*/
typedef u8_t *pu8_t;
typedef u8_t *pu8_t;
/**
* \typedef s8_t *ps8_t
* \brief type definition of pointer to a signed 8 bits integer
*/
typedef s8_t *ps8_t;
typedef s8_t *ps8_t;
/**
* \typedef u16_t *pu16_t
* \brief type definition of pointer to an unsigned 16 bits integer
*/
typedef u16_t *pu16_t;
typedef u16_t *pu16_t;
/**
* \typedef s16_t *ps16_t
* \brief type definition of pointer to a signed 16 bits integer
*/
typedef s16_t *ps16_t;
typedef s16_t *ps16_t;
/**
* \typedef u32_t *pu32_t
* \brief type definition of pointer to an unsigned 32 bits integer
*/
typedef u32_t *pu32_t;
typedef u32_t *pu32_t;
/**
* \typedef s32_t *ps32_t
* \brief type definition of pointer to a signed 32 bits integer
*/
typedef s32_t *ps32_t;
typedef s32_t *ps32_t;
/**
* \typedef u64_t *pu64_t
* \brief type definition of pointer to an usigned 64 bits integer
*/
typedef u64_t *pu64_t;
typedef u64_t *pu64_t;
/**
* \typedef s64_t *ps64_t
* \brief type definition of pointer to a signed 64 bits integer
*/
typedef s64_t *ps64_t;
typedef s64_t *ps64_t;
/**
* \typedef s32_t DRXFrequency_t
* \brief type definition of frequency
*/
typedef s32_t DRXFrequency_t;
typedef s32_t DRXFrequency_t;
/**
* \typedef DRXFrequency_t *pDRXFrequency_t
* \brief type definition of a pointer to a frequency
*/
typedef DRXFrequency_t *pDRXFrequency_t;
typedef DRXFrequency_t *pDRXFrequency_t;
/**
* \typedef u32_t DRXSymbolrate_t
* \brief type definition of symbol rate
*/
typedef u32_t DRXSymbolrate_t;
typedef u32_t DRXSymbolrate_t;
/**
* \typedef DRXSymbolrate_t *pDRXSymbolrate_t
* \brief type definition of a pointer to a symbol rate
*/
typedef DRXSymbolrate_t *pDRXSymbolrate_t;
typedef DRXSymbolrate_t *pDRXSymbolrate_t;
/*-------------------------------------------------------------------------
DEFINES
......@@ -184,32 +183,33 @@ ENUM
* Boolean datatype. Only define if not already defined TRUE or FALSE.
*/
#if defined (TRUE) || defined (FALSE)
typedef int Bool_t;
typedef int Bool_t;
#else
/**
* \enum Bool_t
* \brief Boolean type
*/
typedef enum {
FALSE = 0,
TRUE
} Bool_t;
typedef enum {
FALSE = 0,
TRUE
} Bool_t;
#endif
typedef Bool_t *pBool_t;
typedef Bool_t *pBool_t;
/**
* \enum DRXStatus_t
* \brief Various return statusses
*/
typedef enum {
DRX_STS_READY = 3, /**< device/service is ready */
DRX_STS_BUSY = 2, /**< device/service is busy */
DRX_STS_OK = 1, /**< everything is OK */
DRX_STS_INVALID_ARG = -1, /**< invalid arguments */
DRX_STS_ERROR = -2, /**< general error */
DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */
} DRXStatus_t, *pDRXStatus_t;
typedef enum {
DRX_STS_READY = 3, /**< device/service is ready */
DRX_STS_BUSY = 2, /**< device/service is busy */
DRX_STS_OK = 1, /**< everything is OK */
DRX_STS_INVALID_ARG = -1,
/**< invalid arguments */
DRX_STS_ERROR = -2, /**< general error */
DRX_STS_FUNC_NOT_AVAILABLE = -3
/**< unavailable functionality */
} DRXStatus_t, *pDRXStatus_t;
/*-------------------------------------------------------------------------
STRUCTS
......@@ -225,4 +225,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __BSP_TYPES_H__ */
#endif /* __BSP_TYPES_H__ */
drivers/media/dvb-frontends/drx39xyj/drx39xxj.c
View file @ 443f18d0
......@@ -32,7 +32,7 @@
#include "drxj_mc.h"
#include "drxj.h"
static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable)
static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
......@@ -54,10 +54,10 @@ static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable)
return 0;
}
static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t * status)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXLockStatus_t lock_status;
......@@ -87,16 +87,12 @@ static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
case DRX_LOCK_STATE_8:
case DRX_LOCK_STATE_9:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC;
| FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
break;
case DRX_LOCKED:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
| FE_HAS_CARRIER
| FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
break;
default:
printk("Lock state unknown %d\n", lock_status);
......@@ -105,10 +101,10 @@ static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
return 0;
}
static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber)
static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
......@@ -123,10 +119,11 @@ static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber)
return 0;
}
static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength)
static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
u16 * strength)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
......@@ -142,10 +139,10 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength)
return 0;
}
static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr)
static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
......@@ -160,10 +157,10 @@ static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr)
return 0;
}
static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
......@@ -178,38 +175,40 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
return 0;
}
static int drx39xxj_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
static int drx39xxj_get_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p)
{
return 0;
}
static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
static int drx39xxj_set_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p)
{
#ifdef DJH_DEBUG
int i;
#endif
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStandard_t standard = DRX_STANDARD_8VSB;
DRXChannel_t channel;
DRXStatus_t result;
DRXUIOData_t uioData;
DRXChannel_t defChannel = {/* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
/* hierarchy */ DRX_HIERARCHY_UNKNOWN,
/* priority */ DRX_PRIORITY_UNKNOWN,
/* coderate */ DRX_CODERATE_UNKNOWN,
/* guard */ DRX_GUARD_UNKNOWN,
/* fftmode */ DRX_FFTMODE_UNKNOWN,
/* classification */ DRX_CLASSIFICATION_AUTO,
/* symbolrate */ 5057000,
/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
/* ldpc */ DRX_LDPC_UNKNOWN,
/* carrier */ DRX_CARRIER_UNKNOWN,
/* frame mode */ DRX_FRAMEMODE_UNKNOWN
};
DRXChannel_t defChannel = { /* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
/* hierarchy */ DRX_HIERARCHY_UNKNOWN,
/* priority */ DRX_PRIORITY_UNKNOWN,
/* coderate */ DRX_CODERATE_UNKNOWN,
/* guard */ DRX_GUARD_UNKNOWN,
/* fftmode */ DRX_FFTMODE_UNKNOWN,
/* classification */ DRX_CLASSIFICATION_AUTO,
/* symbolrate */ 5057000,
/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
/* ldpc */ DRX_LDPC_UNKNOWN,
/* carrier */ DRX_CARRIER_UNKNOWN,
/* frame mode */ DRX_FRAMEMODE_UNKNOWN
};
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
......@@ -236,9 +235,9 @@ static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
/* set channel parameters */
channel = defChannel;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO;
/* program channel */
result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
......@@ -246,31 +245,28 @@ static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
printk("Failed to set channel!\n");
return -EINVAL;
}
// Just for giggles, let's shut off the LNA again....
uioData.uio = DRX_UIO1;
uioData.uio = DRX_UIO1;
uioData.value = FALSE;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
if (result != DRX_STS_OK) {
printk("Failed to disable LNA!\n");
return 0;
}
#ifdef DJH_DEBUG
for(i = 0; i < 2000; i++) {
fe_status_t status;
drx39xxj_read_status(fe, &status);
printk("i=%d status=%d\n", i, status);
msleep(100);
i += 100;
for (i = 0; i < 2000; i++) {
fe_status_t status;
drx39xxj_read_status(fe, &status);
printk("i=%d status=%d\n", i, status);
msleep(100);
i += 100;
}
#endif
return 0;
}
static int drx39xxj_sleep(struct dvb_frontend* fe)
static int drx39xxj_sleep(struct dvb_frontend *fe)
{
/* power-down the demodulator */
return drx39xxj_set_powerstate(fe, 0);
......@@ -308,8 +304,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
return 0;
}
static int drx39xxj_init(struct dvb_frontend* fe)
static int drx39xxj_init(struct dvb_frontend *fe)
{
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
......@@ -318,15 +313,15 @@ static int drx39xxj_init(struct dvb_frontend* fe)
}
static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void drx39xxj_release(struct dvb_frontend* fe)
static void drx39xxj_release(struct dvb_frontend *fe)
{
struct drx39xxj_state* state = fe->demodulator_priv;
struct drx39xxj_state *state = fe->demodulator_priv;
kfree(state);
}
......@@ -334,31 +329,36 @@ static struct dvb_frontend_ops drx39xxj_ops;
struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
{
struct drx39xxj_state* state = NULL;
struct drx39xxj_state *state = NULL;
I2CDeviceAddr_t *demodAddr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL;
DRXJData_t *demodExtAttr = NULL;
DRXDemodInstance_t *demod = NULL;
I2CDeviceAddr_t *demodAddr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL;
DRXJData_t *demodExtAttr = NULL;
DRXDemodInstance_t *demod = NULL;
DRXUIOCfg_t uioCfg;
DRXUIOData_t uioData;
DRXStatus_t result;
/* allocate memory for the internal state */
state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
if (state == NULL) goto error;
if (state == NULL)
goto error;
demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL);
if (demod == NULL) goto error;
if (demod == NULL)
goto error;
demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL);
if (demodAddr == NULL) goto error;
if (demodAddr == NULL)
goto error;
demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL);
if (demodCommAttr == NULL) goto error;
if (demodCommAttr == NULL)
goto error;
demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL);
if (demodExtAttr == NULL) goto error;
if (demodExtAttr == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
......@@ -374,13 +374,14 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g,
sizeof(DRXCommonAttr_t));
demod->myCommonAttr->microcode = DRXJ_MC_MAIN;
// demod->myCommonAttr->verifyMicrocode = FALSE;
// demod->myCommonAttr->verifyMicrocode = FALSE;
demod->myCommonAttr->verifyMicrocode = TRUE;
demod->myCommonAttr->intermediateFreq = 5000;
demod->myExtAttr = demodExtAttr;
memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t));
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE;
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode =
DRX_UIO_MODE_READWRITE;
demod->myTuner = NULL;
......@@ -392,8 +393,8 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
}
/* Turn off the LNA */
uioCfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE;
uioCfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE;
/* Configure user-I/O #3: enable read/write */
result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg);
if (result != DRX_STS_OK) {
......@@ -401,7 +402,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
return NULL;
}
uioData.uio = DRX_UIO1;
uioData.uio = DRX_UIO1;
uioData.value = FALSE;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
if (result != DRX_STS_OK) {
......@@ -427,13 +428,12 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
static struct dvb_frontend_ops drx39xxj_ops = {
.info = {
.name = "Micronas DRX39xxj family Frontend",
.type = FE_ATSC | FE_QAM,
.frequency_stepsize = 62500,
.frequency_min = 51000000,
.frequency_max = 858000000,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.name = "Micronas DRX39xxj family Frontend",
.type = FE_ATSC | FE_QAM,
.frequency_stepsize = 62500,
.frequency_min = 51000000,
.frequency_max = 858000000,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB},
.init = drx39xxj_init,
.i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
......
drivers/media/dvb-frontends/drx39xyj/drx39xxj.h
View file @ 443f18d0
......@@ -35,6 +35,6 @@ struct drx39xxj_state {
unsigned int i2c_gate_open:1;
};
extern struct dvb_frontend* drx39xxj_attach(struct i2c_adapter *i2c);
extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c);
#endif // DVB_DUMMY_FE_H
drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c
View file @ 443f18d0
......@@ -13,59 +13,58 @@
#include "drx39xxj.h"
/* Dummy function to satisfy drxj.c */
DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner )
DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner)
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner )
DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner)
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t centerFrequency )
DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t centerFrequency)
{
return DRX_STS_OK;
}
DRXStatus_t
DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency )
DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency)
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_HST_Sleep( u32_t n )
DRXStatus_t DRXBSP_HST_Sleep(u32_t n)
{
msleep(n);
return DRX_STS_OK;
}
u32_t DRXBSP_HST_Clock( void )
u32_t DRXBSP_HST_Clock(void)
{
return jiffies_to_msecs(jiffies);
}
int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n)
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n)
{
return ( memcmp( s1, s2, (size_t) n) );
return (memcmp(s1, s2, (size_t) n));
}
void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n)
void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n)
{
return ( memcpy( to, from, (size_t) n) );
return (memcpy(to, from, (size_t) n));
}
DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData )
DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount, pu8_t rData)
{
struct drx39xxj_state *state;
struct i2c_msg msg[2];
......@@ -102,8 +101,8 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
}
if (state->i2c == NULL) {
printk("i2c was zero, aborting\n");
return 0;
printk("i2c was zero, aborting\n");
return 0;
}
if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
printk(KERN_WARNING "drx3933: I2C write/read failed\n");
......@@ -116,10 +115,10 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
struct drx39xxj_state *state = wDevAddr->userData;
struct i2c_msg msg[2] = {
{ .addr = wDevAddr->i2cAddr,
.flags = 0, .buf = wData, .len = wCount },
{ .addr = rDevAddr->i2cAddr,
.flags = I2C_M_RD, .buf = rData, .len = rCount },
{.addr = wDevAddr->i2cAddr,
.flags = 0,.buf = wData,.len = wCount},
{.addr = rDevAddr->i2cAddr,
.flags = I2C_M_RD,.buf = rData,.len = rCount},
};
printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
......
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c
View file @ 443f18d0
......@@ -50,154 +50,137 @@
*******************************************************************************/
#include "drx_dap_fasi.h"
#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
/*============================================================================*/
/* Function prototypes */
static DRXStatus_t DRXDAP_FASI_WriteBlock (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadBlock (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u16_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu16_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u16_t datain, /* data to send */
pu16_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u32_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu32_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u16_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu16_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u16_t datain, /* data to send */
pu16_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u32_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu32_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout); /* data to receive back */
/* The version structure of this protocol implementation */
char drxDapFASIModuleName[] = "FASI Data Access Protocol";
char drxDapFASIModuleName[] = "FASI Data Access Protocol";
char drxDapFASIVersionText[] = "";
DRXVersion_t drxDapFASIVersion =
{
DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */
DRXVersion_t drxDapFASIVersion = {
DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */
0, /**< major version number */
0, /**< minor version number */
0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */
0, /**< major version number */
0, /**< minor version number */
0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */
};
/* The structure containing the protocol interface */
DRXAccessFunc_t drxDapFASIFunct_g =
{
&drxDapFASIVersion,
DRXDAP_FASI_WriteBlock, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
DRXAccessFunc_t drxDapFASIFunct_g = {
&drxDapFASIVersion,
DRXDAP_FASI_WriteBlock, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
};
/*============================================================================*/
/* Functions not supported by protocol*/
static DRXStatus_t DRXDAP_FASI_WriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags) /* special device flags */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags)
{ /* special device flags */
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags) /* special device flags */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags)
{ /* special device flags */
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout) /* data to receive back */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout)
{ /* data to receive back */
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout) /* data to receive back */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout)
{ /* data to receive back */
return DRX_STS_ERROR;
}
/*============================================================================*/
......@@ -227,105 +210,96 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data, DRXflags_t flags)
{
u8_t buf[4];
u16_t bufx;
DRXStatus_t rc;
u16_t overheadSize = 0;
/* Check parameters ********************************************************/
if ( devAddr == NULL )
{
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize!=0) && (data==NULL)) ||
((datasize & 1)==1 ) )
{
return DRX_STS_INVALID_ARG;
}
/* ReadModifyWrite & mode flag bits are not allowed */
flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
u8_t buf[4];
u16_t bufx;
DRXStatus_t rc;
u16_t overheadSize = 0;
/* Check parameters ******************************************************* */
if (devAddr == NULL) {
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG;
}
/* ReadModifyWrite & mode flag bits are not allowed */
flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Read block from I2C *****************************************************/
do {
u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ?
datasize : DRXDAP_MAX_RCHUNKSIZE);
/* Read block from I2C **************************************************** */
do {
u16_t todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
datasize : DRXDAP_MAX_RCHUNKSIZE);
bufx = 0;
bufx = 0;
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
/* short format address preferred but long format otherwise */
if ( DRXDAP_FASI_LONG_FORMAT(addr) )
{
/* short format address preferred but long format otherwise */
if (DRXDAP_FASI_LONG_FORMAT(addr)) {
#endif
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
#endif
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
} else {
} else {
#endif
#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] =
(u8_t) (((addr >> 16) & 0x0F) |
((addr >> 18) & 0xF0));
#endif
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
}
}
#endif
#if DRXDAP_SINGLE_MASTER
/*
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK)
{
rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data);
}
/*
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK) {
rc = DRXBSP_I2C_WriteRead(0, 0, 0, devAddr, todo, data);
}
#else
/* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data);
/* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, devAddr, todo,
data);
#endif
data += todo;
addr += (todo >> 1);
datasize -= todo;
} while (datasize && rc == DRX_STS_OK);
data += todo;
addr += (todo >> 1);
datasize -= todo;
} while (datasize && rc == DRX_STS_OK);
return rc;
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
......@@ -351,33 +325,27 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t waddr,
DRXaddr_t raddr,
u16_t wdata,
pu16_t rdata )
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr,
DRXaddr_t waddr,
DRXaddr_t raddr,
u16_t wdata, pu16_t rdata)
{
DRXStatus_t rc=DRX_STS_ERROR;
DRXStatus_t rc = DRX_STS_ERROR;
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
if (rdata == NULL)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK)
{
rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0);
}
if (rdata == NULL) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_WriteReg16(devAddr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK) {
rc = DRXDAP_FASI_ReadReg16(devAddr, raddr, rdata, 0);
}
#endif
return rc;
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadReg16 (
......@@ -396,26 +364,21 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu16_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu16_t data, DRXflags_t flags)
{
u8_t buf[sizeof (*data)];
DRXStatus_t rc;
if (!data)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
*data = buf[0] + (((u16_t) buf[1]) << 8);
return rc;
u8_t buf[sizeof(*data)];
DRXStatus_t rc;
if (!data) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags);
*data = buf[0] + (((u16_t) buf[1]) << 8);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadReg32 (
......@@ -434,29 +397,23 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu32_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu32_t data, DRXflags_t flags)
{
u8_t buf[sizeof (*data)];
DRXStatus_t rc;
if (!data)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
*data = (((u32_t) buf[0]) << 0) +
(((u32_t) buf[1]) << 8) +
(((u32_t) buf[2]) << 16) +
(((u32_t) buf[3]) << 24);
return rc;
u8_t buf[sizeof(*data)];
DRXStatus_t rc;
if (!data) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags);
*data = (((u32_t) buf[0]) << 0) +
(((u32_t) buf[1]) << 8) +
(((u32_t) buf[2]) << 16) + (((u32_t) buf[3]) << 24);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteBlock (
......@@ -479,136 +436,128 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data, DRXflags_t flags)
{
u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ];
DRXStatus_t st = DRX_STS_ERROR;
DRXStatus_t firstErr = DRX_STS_OK;
u16_t overheadSize = 0;
u16_t blockSize = 0;
/* Check parameters ********************************************************/
if ( devAddr == NULL )
{
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize!=0) && (data==NULL)) ||
((datasize & 1)==1 ) )
{
return DRX_STS_INVALID_ARG;
}
flags &= DRXDAP_FASI_FLAGS;
flags &= ~DRXDAP_FASI_MODEFLAGS;
u8_t buf[DRXDAP_MAX_WCHUNKSIZE];
DRXStatus_t st = DRX_STS_ERROR;
DRXStatus_t firstErr = DRX_STS_OK;
u16_t overheadSize = 0;
u16_t blockSize = 0;
/* Check parameters ******************************************************* */
if (devAddr == NULL) {
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG;
}
flags &= DRXDAP_FASI_FLAGS;
flags &= ~DRXDAP_FASI_MODEFLAGS;
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Write block to I2C ******************************************************/
blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
do
{
u16_t todo = 0;
u16_t bufx = 0;
/* Write block to I2C ***************************************************** */
blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
do {
u16_t todo = 0;
u16_t bufx = 0;
/* Buffer device address */
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
/* Buffer device address */
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
/* short format address preferred but long format otherwise */
if ( DRXDAP_FASI_LONG_FORMAT(addr) )
{
/* short format address preferred but long format otherwise */
if (DRXDAP_FASI_LONG_FORMAT(addr)) {
#endif
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 )
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
#endif
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
} else {
} else {
#endif
#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 )
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] =
(u8_t) (((addr >> 16) & 0x0F) |
((addr >> 18) & 0xF0));
#endif
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
}
}
#endif
/*
In single master mode blockSize can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and
expects an address.
*/
todo = (blockSize < datasize ? blockSize : datasize);
if (todo==0)
{
u16_t overheadSizeI2cAddr = 0;
u16_t dataBlockSize = 0;
overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1);
dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
/* write device address */
st = DRXBSP_I2C_WriteRead( devAddr,
(u16_t) (bufx),
buf,
(pI2CDeviceAddr_t)(NULL),
0,
(pu8_t)(NULL) );
if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
{
/* at the end, return the first error encountered */
firstErr = st;
}
bufx = 0;
todo = (dataBlockSize < datasize ? dataBlockSize : datasize);
}
DRXBSP_HST_Memcpy (&buf[bufx], data, todo);
/* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead( devAddr,
(u16_t)(bufx + todo),
buf,
(pI2CDeviceAddr_t)(NULL),
0,
(pu8_t)(NULL) );
if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
{
/* at the end, return the first error encountered */
firstErr = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
return firstErr;
/*
In single master mode blockSize can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and
expects an address.
*/
todo = (blockSize < datasize ? blockSize : datasize);
if (todo == 0) {
u16_t overheadSizeI2cAddr = 0;
u16_t dataBlockSize = 0;
overheadSizeI2cAddr =
(IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1);
dataBlockSize =
(DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
/* write device address */
st = DRXBSP_I2C_WriteRead(devAddr,
(u16_t) (bufx),
buf,
(pI2CDeviceAddr_t) (NULL),
0, (pu8_t) (NULL));
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
/* at the end, return the first error encountered */
firstErr = st;
}
bufx = 0;
todo =
(dataBlockSize <
datasize ? dataBlockSize : datasize);
}
DRXBSP_HST_Memcpy(&buf[bufx], data, todo);
/* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead(devAddr,
(u16_t) (bufx + todo),
buf,
(pI2CDeviceAddr_t) (NULL),
0, (pu8_t) (NULL));
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
/* at the end, return the first error encountered */
firstErr = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
return firstErr;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteReg16 (
......@@ -626,22 +575,18 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t data, DRXflags_t flags)
{
u8_t buf[sizeof (data)];
u8_t buf[sizeof(data)];
buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
buf[0] = (u8_t) ((data >> 0) & 0xFF);
buf[1] = (u8_t) ((data >> 8) & 0xFF);
return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags);
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteReg32 (
......@@ -659,17 +604,16 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u32_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u32_t data, DRXflags_t flags)
{
u8_t buf[sizeof (data)];
u8_t buf[sizeof(data)];
buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
buf[2] = (u8_t) ( (data >> 16) & 0xFF );
buf[3] = (u8_t) ( (data >> 24) & 0xFF );
buf[0] = (u8_t) ((data >> 0) & 0xFF);
buf[1] = (u8_t) ((data >> 8) & 0xFF);
buf[2] = (u8_t) ((data >> 16) & 0xFF);
buf[3] = (u8_t) ((data >> 24) & 0xFF);
return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags);
}
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h
View file @ 443f18d0
......@@ -96,10 +96,9 @@
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) )
#error At least one of short- or long-addressing format must be allowed.
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
/********************************************
* Single/master multi master setting
********************************************/
......@@ -200,18 +199,18 @@
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) )
#if DRXDAP_SINGLE_MASTER
#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#else
#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
#else
#if DRXDAP_SINGLE_MASTER
#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#else
#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
#endif
#endif
......@@ -224,13 +223,13 @@
/* check */
#if DRXDAP_MAX_RCHUNKSIZE < 2
#error DRXDAP_MAX_RCHUNKSIZE must be at least 2
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
/* check */
#if DRXDAP_MAX_RCHUNKSIZE & 1
#error DRXDAP_MAX_RCHUNKSIZE must be even
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
/*-------- Public API functions ----------------------------------------------*/
......@@ -239,15 +238,14 @@
extern "C" {
#endif
extern DRXAccessFunc_t drxDapFASIFunct_g;
extern DRXAccessFunc_t drxDapFASIFunct_g;
#define DRXDAP_FASI_RMW 0x10000000
#define DRXDAP_FASI_BROADCAST 0x20000000
#define DRXDAP_FASI_CLEARCRC 0x80000000
#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000
#define DRXDAP_FASI_MULTI_MASTER 0x40000000
#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */
#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */
#define DRXDAP_FASI_MODEFLAGS 0xC0000000
#define DRXDAP_FASI_FLAGS 0xF0000000
......@@ -259,10 +257,7 @@ extern DRXAccessFunc_t drxDapFASIFunct_g;
#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0)
#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0)
#ifdef __cplusplus
}
#endif
#endif /* __DRX_DAP_FASI_H__ */
#endif /* __DRX_DAP_FASI_H__ */
drivers/media/dvb-frontends/drx39xyj/drx_driver.c
View file @ 443f18d0
......@@ -119,14 +119,17 @@ STRUCTURES
------------------------------------------------------------------------------*/
/** \brief Structure of the microcode block headers */
typedef struct {
u32_t addr; /**< Destination address of the data in this block */
u16_t size; /**< Size of the block data following this header counted in
u32_t addr;
/**< Destination address of the data in this block */
u16_t size;
/**< Size of the block data following this header counted in
16 bits words */
u16_t flags; /**< Flags for this data block:
u16_t flags;
/**< Flags for this data block:
- bit[0]= CRC on/off
- bit[1]= compression on/off
- bit[15..2]=reserved */
u16_t CRC; /**< CRC value of the data block, only valid if CRC flag is
u16_t CRC;/**< CRC value of the data block, only valid if CRC flag is
set. */
} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t;
......@@ -144,33 +147,30 @@ FUNCTIONS
/* Prototype of default scanning function */
static DRXStatus_t
ScanFunctionDefault( void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
pBool_t getNextChannel );
ScanFunctionDefault(void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel, pBool_t getNextChannel);
/**
* \brief Get pointer to scanning function.
* \param demod: Pointer to demodulator instance.
* \return DRXScanFunc_t.
*/
static DRXScanFunc_t
GetScanFunction( pDRXDemodInstance_t demod )
static DRXScanFunc_t GetScanFunction(pDRXDemodInstance_t demod)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
DRXScanFunc_t scanFunc = (DRXScanFunc_t)(NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
scanFunc = commonAttr->scanFunction;
if ( scanFunc != NULL )
{
/* return device-specific scan function if it's not NULL */
return scanFunc;
}
/* otherwise return default scan function in core driver */
return &ScanFunctionDefault;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
DRXScanFunc_t scanFunc = (DRXScanFunc_t) (NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
scanFunc = commonAttr->scanFunction;
if (scanFunc != NULL) {
/* return device-specific scan function if it's not NULL */
return scanFunc;
}
/* otherwise return default scan function in core driver */
return &ScanFunctionDefault;
}
/**
......@@ -179,21 +179,19 @@ GetScanFunction( pDRXDemodInstance_t demod )
* \param scanContext: Context Pointer.
* \return DRXScanFunc_t.
*/
void *GetScanContext( pDRXDemodInstance_t demod,
void *scanContext)
void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
scanContext = commonAttr->scanContext;
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
scanContext = commonAttr->scanContext;
if ( scanContext == NULL )
{
scanContext = (void *) demod;
}
if (scanContext == NULL) {
scanContext = (void *)demod;
}
return scanContext;
return scanContext;
}
/**
......@@ -214,59 +212,50 @@ void *GetScanContext( pDRXDemodInstance_t demod,
* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted.
*
*/
static DRXStatus_t
ScanWaitForLock( pDRXDemodInstance_t demod,
pBool_t isLocked )
static DRXStatus_t ScanWaitForLock(pDRXDemodInstance_t demod, pBool_t isLocked)
{
Bool_t doneWaiting = FALSE;
DRXLockStatus_t lockState = DRX_NOT_LOCKED;
DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED;
u32_t timeoutValue = 0;
u32_t startTimeLockStage = 0;
u32_t currentTime = 0;
u32_t timerValue = 0;
*isLocked = FALSE;
timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout;
desiredLockState = demod->myCommonAttr->scanDesiredLock;
startTimeLockStage = DRXBSP_HST_Clock();
/* Start polling loop, checking for lock & timeout */
while ( doneWaiting == FALSE )
{
if ( DRX_Ctrl( demod, DRX_CTRL_LOCK_STATUS, &lockState ) != DRX_STS_OK )
{
return DRX_STS_ERROR;
}
currentTime = DRXBSP_HST_Clock();
timerValue = currentTime - startTimeLockStage;
if ( lockState >= desiredLockState )
{
*isLocked = TRUE;
doneWaiting = TRUE;
} /* if ( lockState >= desiredLockState ) .. */
else if ( lockState == DRX_NEVER_LOCK )
{
doneWaiting = TRUE;
} /* if ( lockState == DRX_NEVER_LOCK ) .. */
else if ( timerValue > timeoutValue )
{
/* lockState == DRX_NOT_LOCKED and timeout */
doneWaiting = TRUE;
}
else
{
if ( DRXBSP_HST_Sleep( 10 ) != DRX_STS_OK )
{
return DRX_STS_ERROR;
}
} /* if ( timerValue > timeoutValue ) .. */
} /* while */
return DRX_STS_OK;
Bool_t doneWaiting = FALSE;
DRXLockStatus_t lockState = DRX_NOT_LOCKED;
DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED;
u32_t timeoutValue = 0;
u32_t startTimeLockStage = 0;
u32_t currentTime = 0;
u32_t timerValue = 0;
*isLocked = FALSE;
timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout;
desiredLockState = demod->myCommonAttr->scanDesiredLock;
startTimeLockStage = DRXBSP_HST_Clock();
/* Start polling loop, checking for lock & timeout */
while (doneWaiting == FALSE) {
if (DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lockState) !=
DRX_STS_OK) {
return DRX_STS_ERROR;
}
currentTime = DRXBSP_HST_Clock();
timerValue = currentTime - startTimeLockStage;
if (lockState >= desiredLockState) {
*isLocked = TRUE;
doneWaiting = TRUE;
} /* if ( lockState >= desiredLockState ) .. */
else if (lockState == DRX_NEVER_LOCK) {
doneWaiting = TRUE;
} /* if ( lockState == DRX_NEVER_LOCK ) .. */
else if (timerValue > timeoutValue) {
/* lockState == DRX_NOT_LOCKED and timeout */
doneWaiting = TRUE;
} else {
if (DRXBSP_HST_Sleep(10) != DRX_STS_OK) {
return DRX_STS_ERROR;
}
} /* if ( timerValue > timeoutValue ) .. */
} /* while */
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -285,73 +274,66 @@ ScanWaitForLock( pDRXDemodInstance_t demod,
*
*/
static DRXStatus_t
ScanPrepareNextScan ( pDRXDemodInstance_t demod,
DRXFrequency_t skip )
ScanPrepareNextScan(pDRXDemodInstance_t demod, DRXFrequency_t skip)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
u16_t tableIndex = 0;
u16_t frequencyPlanSize = 0;
pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t)(NULL);
DRXFrequency_t nextFrequency = 0;
DRXFrequency_t tunerMinFrequency = 0;
DRXFrequency_t tunerMaxFrequency = 0;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
tableIndex = commonAttr->scanFreqPlanIndex;
frequencyPlan = commonAttr->scanParam->frequencyPlan;
nextFrequency = commonAttr->scanNextFrequency;
tunerMinFrequency = commonAttr->tunerMinFreqRF;
tunerMaxFrequency = commonAttr->tunerMaxFreqRF;
do
{
/* Search next frequency to scan */
/* always take at least one step */
(commonAttr->scanChannelsScanned) ++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
/* and then as many steps necessary to exceed 'skip'
without exceeding end of the band */
while ( ( skip > 0 ) &&
( nextFrequency <= frequencyPlan[tableIndex].last ) )
{
(commonAttr->scanChannelsScanned) ++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
}
/* reset skip, in case we move to the next band later */
skip = 0;
if ( nextFrequency > frequencyPlan[tableIndex].last )
{
/* reached end of this band */
tableIndex++;
frequencyPlanSize = commonAttr->scanParam->frequencyPlanSize;
if ( tableIndex >= frequencyPlanSize )
{
/* reached end of frequency plan */
commonAttr->scanReady = TRUE;
}
else
{
nextFrequency = frequencyPlan[tableIndex].first;
}
}
if ( nextFrequency > (tunerMaxFrequency) )
{
/* reached end of tuner range */
commonAttr->scanReady = TRUE;
}
} while( ( nextFrequency < tunerMinFrequency ) &&
( commonAttr->scanReady == FALSE ) );
/* Store new values */
commonAttr->scanFreqPlanIndex = tableIndex;
commonAttr->scanNextFrequency = nextFrequency;
return DRX_STS_OK;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
u16_t tableIndex = 0;
u16_t frequencyPlanSize = 0;
pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t) (NULL);
DRXFrequency_t nextFrequency = 0;
DRXFrequency_t tunerMinFrequency = 0;
DRXFrequency_t tunerMaxFrequency = 0;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
tableIndex = commonAttr->scanFreqPlanIndex;
frequencyPlan = commonAttr->scanParam->frequencyPlan;
nextFrequency = commonAttr->scanNextFrequency;
tunerMinFrequency = commonAttr->tunerMinFreqRF;
tunerMaxFrequency = commonAttr->tunerMaxFreqRF;
do {
/* Search next frequency to scan */
/* always take at least one step */
(commonAttr->scanChannelsScanned)++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
/* and then as many steps necessary to exceed 'skip'
without exceeding end of the band */
while ((skip > 0) &&
(nextFrequency <= frequencyPlan[tableIndex].last)) {
(commonAttr->scanChannelsScanned)++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
}
/* reset skip, in case we move to the next band later */
skip = 0;
if (nextFrequency > frequencyPlan[tableIndex].last) {
/* reached end of this band */
tableIndex++;
frequencyPlanSize =
commonAttr->scanParam->frequencyPlanSize;
if (tableIndex >= frequencyPlanSize) {
/* reached end of frequency plan */
commonAttr->scanReady = TRUE;
} else {
nextFrequency = frequencyPlan[tableIndex].first;
}
}
if (nextFrequency > (tunerMaxFrequency)) {
/* reached end of tuner range */
commonAttr->scanReady = TRUE;
}
} while ((nextFrequency < tunerMinFrequency) &&
(commonAttr->scanReady == FALSE));
/* Store new values */
commonAttr->scanFreqPlanIndex = tableIndex;
commonAttr->scanNextFrequency = nextFrequency;
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -373,47 +355,42 @@ ScanPrepareNextScan ( pDRXDemodInstance_t demod,
* scanChannel and getNextChannel will be NULL for INIT and STOP.
*/
static DRXStatus_t
ScanFunctionDefault ( void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
pBool_t getNextChannel )
ScanFunctionDefault(void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel, pBool_t getNextChannel)
{
pDRXDemodInstance_t demod = NULL;
DRXStatus_t status = DRX_STS_ERROR;
Bool_t isLocked = FALSE;
demod = (pDRXDemodInstance_t) scanContext;
if ( scanCommand != DRX_SCAN_COMMAND_NEXT )
{
/* just return OK if not doing "scan next" */
return DRX_STS_OK;
}
*getNextChannel = FALSE;
status = DRX_Ctrl ( demod, DRX_CTRL_SET_CHANNEL, scanChannel );
if ( status != DRX_STS_OK )
{
return (status);
}
status = ScanWaitForLock ( demod, &isLocked );
if ( status != DRX_STS_OK )
{
return status;
}
/* done with this channel, move to next one */
*getNextChannel = TRUE;
if ( isLocked == FALSE )
{
/* no channel found */
return DRX_STS_BUSY;
}
/* channel found */
return DRX_STS_OK;
pDRXDemodInstance_t demod = NULL;
DRXStatus_t status = DRX_STS_ERROR;
Bool_t isLocked = FALSE;
demod = (pDRXDemodInstance_t) scanContext;
if (scanCommand != DRX_SCAN_COMMAND_NEXT) {
/* just return OK if not doing "scan next" */
return DRX_STS_OK;
}
*getNextChannel = FALSE;
status = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, scanChannel);
if (status != DRX_STS_OK) {
return (status);
}
status = ScanWaitForLock(demod, &isLocked);
if (status != DRX_STS_OK) {
return status;
}
/* done with this channel, move to next one */
*getNextChannel = TRUE;
if (isLocked == FALSE) {
/* no channel found */
return DRX_STS_BUSY;
}
/* channel found */
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -436,150 +413,133 @@ ScanFunctionDefault ( void *scanContext,
*
*/
static DRXStatus_t
CtrlScanInit( pDRXDemodInstance_t demod,
pDRXScanParam_t scanParam )
CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam)
{
DRXStatus_t status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL);
DRXFrequency_t maxTunerFreq = 0;
DRXFrequency_t minTunerFreq = 0;
u16_t nrChannelsInPlan = 0;
u16_t i = 0;
void *scanContext = NULL;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
commonAttr->scanActive = TRUE;
/* invalidate a previous SCAN_INIT */
commonAttr->scanParam = (pDRXScanParam_t)(NULL);
commonAttr->scanNextFrequency = 0;
/* Check parameters */
if ( ( ( demod->myTuner == NULL ) &&
( scanParam->numTries !=1) ) ||
( scanParam == NULL) ||
( scanParam->numTries == 0) ||
( scanParam->frequencyPlan == NULL) ||
( scanParam->frequencyPlanSize == 0 )
)
{
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
/* Check frequency plan contents */
maxTunerFreq = commonAttr->tunerMaxFreqRF;
minTunerFreq = commonAttr->tunerMinFreqRF;
for( i = 0; i < (scanParam->frequencyPlanSize); i++ )
{
DRXFrequency_t width = 0;
DRXFrequency_t step = scanParam->frequencyPlan[i].step;
DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first;
DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last;
DRXFrequency_t minFreq = 0;
DRXFrequency_t maxFreq = 0;
if ( step <= 0 )
{
/* Step must be positive and non-zero */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
if ( firstFreq > lastFreq )
{
/* First center frequency is higher than last center frequency */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
width = lastFreq - firstFreq;
if ( ( width % step ) != 0 )
{
/* Difference between last and first center frequency is not
an integer number of steps */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
/* Check if frequency plan entry intersects with tuner range */
if ( lastFreq >= minTunerFreq )
{
if ( firstFreq <= maxTunerFreq )
{
if ( firstFreq >= minTunerFreq )
{
minFreq = firstFreq;
}
else
{
DRXFrequency_t n = 0;
n = ( minTunerFreq - firstFreq ) / step;
if ( ( ( minTunerFreq - firstFreq ) % step ) != 0 )
{
n++;
}
minFreq = firstFreq + n*step;
}
if ( lastFreq <= maxTunerFreq )
{
maxFreq = lastFreq;
}
else
{
DRXFrequency_t n=0;
n=( lastFreq - maxTunerFreq )/step;
if ( (( lastFreq - maxTunerFreq )%step) !=0 )
{
n++;
}
maxFreq = lastFreq - n*step;
}
}
}
/* Keep track of total number of channels within tuner range
in this frequency plan. */
if ( (minFreq !=0 ) && ( maxFreq != 0 ) )
{
nrChannelsInPlan += (u16_t)( ( ( maxFreq-minFreq ) / step ) +1 );
/* Determine first frequency (within tuner range) to scan */
if ( commonAttr->scanNextFrequency == 0 )
{
commonAttr->scanNextFrequency = minFreq;
commonAttr->scanFreqPlanIndex = i;
}
}
}/* for ( ... ) */
if ( nrChannelsInPlan == 0 )
{
/* Tuner range and frequency plan ranges do not overlap */
commonAttr->scanActive = FALSE;
return DRX_STS_ERROR;
}
/* Store parameters */
commonAttr->scanReady = FALSE;
commonAttr->scanMaxChannels = nrChannelsInPlan;
commonAttr->scanChannelsScanned = 0;
commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction( demod )))
( scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL );
commonAttr->scanActive = FALSE;
return DRX_STS_OK;
DRXStatus_t status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
DRXFrequency_t maxTunerFreq = 0;
DRXFrequency_t minTunerFreq = 0;
u16_t nrChannelsInPlan = 0;
u16_t i = 0;
void *scanContext = NULL;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
commonAttr->scanActive = TRUE;
/* invalidate a previous SCAN_INIT */
commonAttr->scanParam = (pDRXScanParam_t) (NULL);
commonAttr->scanNextFrequency = 0;
/* Check parameters */
if (((demod->myTuner == NULL) &&
(scanParam->numTries != 1)) ||
(scanParam == NULL) ||
(scanParam->numTries == 0) ||
(scanParam->frequencyPlan == NULL) ||
(scanParam->frequencyPlanSize == 0)
) {
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
/* Check frequency plan contents */
maxTunerFreq = commonAttr->tunerMaxFreqRF;
minTunerFreq = commonAttr->tunerMinFreqRF;
for (i = 0; i < (scanParam->frequencyPlanSize); i++) {
DRXFrequency_t width = 0;
DRXFrequency_t step = scanParam->frequencyPlan[i].step;
DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first;
DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last;
DRXFrequency_t minFreq = 0;
DRXFrequency_t maxFreq = 0;
if (step <= 0) {
/* Step must be positive and non-zero */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
if (firstFreq > lastFreq) {
/* First center frequency is higher than last center frequency */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
width = lastFreq - firstFreq;
if ((width % step) != 0) {
/* Difference between last and first center frequency is not
an integer number of steps */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
/* Check if frequency plan entry intersects with tuner range */
if (lastFreq >= minTunerFreq) {
if (firstFreq <= maxTunerFreq) {
if (firstFreq >= minTunerFreq) {
minFreq = firstFreq;
} else {
DRXFrequency_t n = 0;
n = (minTunerFreq - firstFreq) / step;
if (((minTunerFreq -
firstFreq) % step) != 0) {
n++;
}
minFreq = firstFreq + n * step;
}
if (lastFreq <= maxTunerFreq) {
maxFreq = lastFreq;
} else {
DRXFrequency_t n = 0;
n = (lastFreq - maxTunerFreq) / step;
if (((lastFreq -
maxTunerFreq) % step) != 0) {
n++;
}
maxFreq = lastFreq - n * step;
}
}
}
/* Keep track of total number of channels within tuner range
in this frequency plan. */
if ((minFreq != 0) && (maxFreq != 0)) {
nrChannelsInPlan +=
(u16_t) (((maxFreq - minFreq) / step) + 1);
/* Determine first frequency (within tuner range) to scan */
if (commonAttr->scanNextFrequency == 0) {
commonAttr->scanNextFrequency = minFreq;
commonAttr->scanFreqPlanIndex = i;
}
}
} /* for ( ... ) */
if (nrChannelsInPlan == 0) {
/* Tuner range and frequency plan ranges do not overlap */
commonAttr->scanActive = FALSE;
return DRX_STS_ERROR;
}
/* Store parameters */
commonAttr->scanReady = FALSE;
commonAttr->scanMaxChannels = nrChannelsInPlan;
commonAttr->scanChannelsScanned = 0;
commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction(demod)))
(scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL);
commonAttr->scanActive = FALSE;
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -592,36 +552,34 @@ CtrlScanInit( pDRXDemodInstance_t demod,
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*/
static DRXStatus_t
CtrlScanStop( pDRXDemodInstance_t demod )
static DRXStatus_t CtrlScanStop(pDRXDemodInstance_t demod)
{
DRXStatus_t status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
void *scanContext = NULL;
DRXStatus_t status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
void *scanContext = NULL;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
commonAttr->scanActive = TRUE;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
commonAttr->scanActive = TRUE;
if ( ( commonAttr->scanParam == NULL ) ||
( commonAttr->scanMaxChannels == 0 ) )
{
/* Scan was not running, just return OK */
commonAttr->scanActive = FALSE;
return DRX_STS_OK;
}
if ((commonAttr->scanParam == NULL) ||
(commonAttr->scanMaxChannels == 0)) {
/* Scan was not running, just return OK */
commonAttr->scanActive = FALSE;
return DRX_STS_OK;
}
/* Call default or device-specific scanning stop function */
scanContext = GetScanContext(demod, scanContext);
/* Call default or device-specific scanning stop function */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction( demod )))
( scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL );
status = (*(GetScanFunction(demod)))
(scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL);
/* All done, invalidate scan-init */
commonAttr->scanParam = NULL;
commonAttr->scanMaxChannels = 0;
commonAttr->scanActive = FALSE;
/* All done, invalidate scan-init */
commonAttr->scanParam = NULL;
commonAttr->scanMaxChannels = 0;
commonAttr->scanActive = FALSE;
return status;
return status;
}
/*============================================================================*/
......@@ -644,120 +602,113 @@ CtrlScanStop( pDRXDemodInstance_t demod )
* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan.
*
*/
static DRXStatus_t
CtrlScanNext ( pDRXDemodInstance_t demod,
pu16_t scanProgress )
static DRXStatus_t CtrlScanNext(pDRXDemodInstance_t demod, pu16_t scanProgress)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
pBool_t scanReady = (pBool_t)(NULL);
u16_t maxProgress = DRX_SCAN_MAX_PROGRESS;
u32_t numTries = 0;
u32_t i = 0;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
/* Check scan parameters */
if ( scanProgress == NULL )
{
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
*scanProgress = 0;
commonAttr->scanActive = TRUE;
if ( ( commonAttr->scanParam == NULL) ||
( commonAttr->scanMaxChannels == 0 ) )
{
/* CtrlScanInit() was not called succesfully before CtrlScanNext() */
commonAttr->scanActive = FALSE;
return DRX_STS_ERROR;
}
*scanProgress = (u16_t)( ( ( commonAttr->scanChannelsScanned)*
( (u32_t)(maxProgress) ) ) /
( commonAttr->scanMaxChannels ) );
/* Scan */
numTries = commonAttr->scanParam->numTries;
scanReady = &(commonAttr->scanReady);
for ( i = 0; ( (i < numTries) && ( (*scanReady) == FALSE) ); i++)
{
DRXChannel_t scanChannel = { 0 };
DRXStatus_t status = DRX_STS_ERROR;
pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL);
Bool_t nextChannel = FALSE;
void *scanContext = NULL;
/* Next channel to scan */
freqPlan =
&(commonAttr->scanParam->frequencyPlan[commonAttr->scanFreqPlanIndex]);
scanChannel.frequency = commonAttr->scanNextFrequency;
scanChannel.bandwidth = freqPlan->bandwidth;
scanChannel.mirror = DRX_MIRROR_AUTO;
scanChannel.constellation = DRX_CONSTELLATION_AUTO;
scanChannel.hierarchy = DRX_HIERARCHY_AUTO;
scanChannel.priority = DRX_PRIORITY_HIGH;
scanChannel.coderate = DRX_CODERATE_AUTO;
scanChannel.guard = DRX_GUARD_AUTO;
scanChannel.fftmode = DRX_FFTMODE_AUTO;
scanChannel.classification = DRX_CLASSIFICATION_AUTO;
scanChannel.symbolrate = 0;
scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO;
scanChannel.ldpc = DRX_LDPC_AUTO;
scanChannel.carrier = DRX_CARRIER_AUTO;
scanChannel.framemode = DRX_FRAMEMODE_AUTO;
scanChannel.pilot = DRX_PILOT_AUTO;
/* Call default or device-specific scanning function */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction( demod )))
( scanContext,DRX_SCAN_COMMAND_NEXT,&scanChannel,&nextChannel );
/* Proceed to next channel if requested */
if ( nextChannel == TRUE )
{
DRXStatus_t nextStatus = DRX_STS_ERROR;
DRXFrequency_t skip = 0;
if ( status == DRX_STS_OK )
{
/* a channel was found, so skip some frequency steps */
skip = commonAttr->scanParam->skip;
}
nextStatus = ScanPrepareNextScan( demod, skip );
/* keep track of progress */
*scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)*
((u32_t)(maxProgress)))/
(commonAttr->scanMaxChannels));
if ( nextStatus != DRX_STS_OK )
{
commonAttr->scanActive = FALSE;
return (nextStatus);
}
}
if ( status != DRX_STS_BUSY )
{
/* channel found or error */
commonAttr->scanActive = FALSE;
return status;
}
} /* for ( i = 0; i < ( ... numTries); i++) */
if ( (*scanReady) == TRUE )
{
/* End of scan reached: call stop-scan, ignore any error */
CtrlScanStop( demod );
commonAttr->scanActive = FALSE;
return (DRX_STS_READY);
}
commonAttr->scanActive = FALSE;
return DRX_STS_BUSY;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
pBool_t scanReady = (pBool_t) (NULL);
u16_t maxProgress = DRX_SCAN_MAX_PROGRESS;
u32_t numTries = 0;
u32_t i = 0;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
/* Check scan parameters */
if (scanProgress == NULL) {
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
*scanProgress = 0;
commonAttr->scanActive = TRUE;
if ((commonAttr->scanParam == NULL) ||
(commonAttr->scanMaxChannels == 0)) {
/* CtrlScanInit() was not called succesfully before CtrlScanNext() */
commonAttr->scanActive = FALSE;
return DRX_STS_ERROR;
}
*scanProgress = (u16_t) (((commonAttr->scanChannelsScanned) *
((u32_t) (maxProgress))) /
(commonAttr->scanMaxChannels));
/* Scan */
numTries = commonAttr->scanParam->numTries;
scanReady = &(commonAttr->scanReady);
for (i = 0; ((i < numTries) && ((*scanReady) == FALSE)); i++) {
DRXChannel_t scanChannel = { 0 };
DRXStatus_t status = DRX_STS_ERROR;
pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL);
Bool_t nextChannel = FALSE;
void *scanContext = NULL;
/* Next channel to scan */
freqPlan =
&(commonAttr->scanParam->
frequencyPlan[commonAttr->scanFreqPlanIndex]);
scanChannel.frequency = commonAttr->scanNextFrequency;
scanChannel.bandwidth = freqPlan->bandwidth;
scanChannel.mirror = DRX_MIRROR_AUTO;
scanChannel.constellation = DRX_CONSTELLATION_AUTO;
scanChannel.hierarchy = DRX_HIERARCHY_AUTO;
scanChannel.priority = DRX_PRIORITY_HIGH;
scanChannel.coderate = DRX_CODERATE_AUTO;
scanChannel.guard = DRX_GUARD_AUTO;
scanChannel.fftmode = DRX_FFTMODE_AUTO;
scanChannel.classification = DRX_CLASSIFICATION_AUTO;
scanChannel.symbolrate = 0;
scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO;
scanChannel.ldpc = DRX_LDPC_AUTO;
scanChannel.carrier = DRX_CARRIER_AUTO;
scanChannel.framemode = DRX_FRAMEMODE_AUTO;
scanChannel.pilot = DRX_PILOT_AUTO;
/* Call default or device-specific scanning function */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction(demod)))
(scanContext, DRX_SCAN_COMMAND_NEXT, &scanChannel,
&nextChannel);
/* Proceed to next channel if requested */
if (nextChannel == TRUE) {
DRXStatus_t nextStatus = DRX_STS_ERROR;
DRXFrequency_t skip = 0;
if (status == DRX_STS_OK) {
/* a channel was found, so skip some frequency steps */
skip = commonAttr->scanParam->skip;
}
nextStatus = ScanPrepareNextScan(demod, skip);
/* keep track of progress */
*scanProgress =
(u16_t) (((commonAttr->scanChannelsScanned) *
((u32_t) (maxProgress))) /
(commonAttr->scanMaxChannels));
if (nextStatus != DRX_STS_OK) {
commonAttr->scanActive = FALSE;
return (nextStatus);
}
}
if (status != DRX_STS_BUSY) {
/* channel found or error */
commonAttr->scanActive = FALSE;
return status;
}
} /* for ( i = 0; i < ( ... numTries); i++) */
if ((*scanReady) == TRUE) {
/* End of scan reached: call stop-scan, ignore any error */
CtrlScanStop(demod);
commonAttr->scanActive = FALSE;
return (DRX_STS_READY);
}
commonAttr->scanActive = FALSE;
return DRX_STS_BUSY;
}
#endif /* #ifndef DRX_EXCLUDE_SCAN */
......@@ -778,117 +729,103 @@ CtrlScanNext ( pDRXDemodInstance_t demod,
*
*/
static DRXStatus_t
CtrlProgramTuner( pDRXDemodInstance_t demod,
pDRXChannel_t channel )
CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
DRXStandard_t standard = DRX_STANDARD_UNKNOWN;
TUNERMode_t tunerMode = 0;
DRXStatus_t status = DRX_STS_ERROR;
DRXFrequency_t ifFrequency = 0;
Bool_t tunerSlowMode = FALSE;
/* can't tune without a tuner */
if ( demod->myTuner == NULL )
{
return DRX_STS_INVALID_ARG;
}
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
/* select analog or digital tuner mode based on current standard */
if ( DRX_Ctrl( demod, DRX_CTRL_GET_STANDARD, &standard ) != DRX_STS_OK )
{
return DRX_STS_ERROR;
}
if ( DRX_ISATVSTD( standard ) )
{
tunerMode |= TUNER_MODE_ANALOG;
}
else /* note: also for unknown standard */
{
tunerMode |= TUNER_MODE_DIGITAL;
}
/* select tuner bandwidth */
switch ( channel->bandwidth )
{
case DRX_BANDWIDTH_6MHZ:
tunerMode |= TUNER_MODE_6MHZ;
break;
case DRX_BANDWIDTH_7MHZ:
tunerMode |= TUNER_MODE_7MHZ;
break;
case DRX_BANDWIDTH_8MHZ:
tunerMode |= TUNER_MODE_8MHZ;
break;
default: /* note: also for unknown bandwidth */
return DRX_STS_INVALID_ARG;
}
DRX_GET_TUNERSLOWMODE (demod, tunerSlowMode);
/* select fast (switch) or slow (lock) tuner mode */
if ( tunerSlowMode )
{
tunerMode |= TUNER_MODE_LOCK;
}
else
{
tunerMode |= TUNER_MODE_SWITCH;
}
if ( commonAttr->tunerPortNr == 1 )
{
Bool_t bridgeClosed = TRUE;
DRXStatus_t statusBridge = DRX_STS_ERROR;
statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed );
if ( statusBridge != DRX_STS_OK )
{
return statusBridge;
}
}
status = DRXBSP_TUNER_SetFrequency( demod->myTuner,
tunerMode,
channel->frequency );
/* attempt restoring bridge before checking status of SetFrequency */
if ( commonAttr->tunerPortNr == 1 )
{
Bool_t bridgeClosed = FALSE;
DRXStatus_t statusBridge = DRX_STS_ERROR;
statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed );
if ( statusBridge != DRX_STS_OK )
{
return statusBridge;
}
}
/* now check status of DRXBSP_TUNER_SetFrequency */
if ( status != DRX_STS_OK )
{
return status;
}
/* get actual RF and IF frequencies from tuner */
status = DRXBSP_TUNER_GetFrequency( demod->myTuner,
tunerMode,
&(channel->frequency),
&(ifFrequency) );
if ( status != DRX_STS_OK )
{
return status;
}
/* update common attributes with information available from this function;
TODO: check if this is required and safe */
DRX_SET_INTERMEDIATEFREQ( demod, ifFrequency );
return DRX_STS_OK;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
DRXStandard_t standard = DRX_STANDARD_UNKNOWN;
TUNERMode_t tunerMode = 0;
DRXStatus_t status = DRX_STS_ERROR;
DRXFrequency_t ifFrequency = 0;
Bool_t tunerSlowMode = FALSE;
/* can't tune without a tuner */
if (demod->myTuner == NULL) {
return DRX_STS_INVALID_ARG;
}
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
/* select analog or digital tuner mode based on current standard */
if (DRX_Ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) {
return DRX_STS_ERROR;
}
if (DRX_ISATVSTD(standard)) {
tunerMode |= TUNER_MODE_ANALOG;
} else { /* note: also for unknown standard */
tunerMode |= TUNER_MODE_DIGITAL;
}
/* select tuner bandwidth */
switch (channel->bandwidth) {
case DRX_BANDWIDTH_6MHZ:
tunerMode |= TUNER_MODE_6MHZ;
break;
case DRX_BANDWIDTH_7MHZ:
tunerMode |= TUNER_MODE_7MHZ;
break;
case DRX_BANDWIDTH_8MHZ:
tunerMode |= TUNER_MODE_8MHZ;
break;
default: /* note: also for unknown bandwidth */
return DRX_STS_INVALID_ARG;
}
DRX_GET_TUNERSLOWMODE(demod, tunerSlowMode);
/* select fast (switch) or slow (lock) tuner mode */
if (tunerSlowMode) {
tunerMode |= TUNER_MODE_LOCK;
} else {
tunerMode |= TUNER_MODE_SWITCH;
}
if (commonAttr->tunerPortNr == 1) {
Bool_t bridgeClosed = TRUE;
DRXStatus_t statusBridge = DRX_STS_ERROR;
statusBridge =
DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed);
if (statusBridge != DRX_STS_OK) {
return statusBridge;
}
}
status = DRXBSP_TUNER_SetFrequency(demod->myTuner,
tunerMode, channel->frequency);
/* attempt restoring bridge before checking status of SetFrequency */
if (commonAttr->tunerPortNr == 1) {
Bool_t bridgeClosed = FALSE;
DRXStatus_t statusBridge = DRX_STS_ERROR;
statusBridge =
DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed);
if (statusBridge != DRX_STS_OK) {
return statusBridge;
}
}
/* now check status of DRXBSP_TUNER_SetFrequency */
if (status != DRX_STS_OK) {
return status;
}
/* get actual RF and IF frequencies from tuner */
status = DRXBSP_TUNER_GetFrequency(demod->myTuner,
tunerMode,
&(channel->frequency),
&(ifFrequency));
if (status != DRX_STS_OK) {
return status;
}
/* update common attributes with information available from this function;
TODO: check if this is required and safe */
DRX_SET_INTERMEDIATEFREQ(demod, ifFrequency);
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -903,41 +840,40 @@ CtrlProgramTuner( pDRXDemodInstance_t demod,
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*
*/
DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod,
pDRXRegDump_t registers )
DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod,
pDRXRegDump_t registers)
{
u16_t i = 0;
if ( registers == NULL )
{
/* registers not supplied */
return DRX_STS_INVALID_ARG;
}
/* start dumping registers */
while ( registers[i].address != 0 )
{
DRXStatus_t status = DRX_STS_ERROR;
u16_t value = 0;
u32_t data = 0;
status = demod->myAccessFunct->readReg16Func(
demod->myI2CDevAddr, registers[i].address, &value, 0 );
data = (u32_t)value;
if ( status != DRX_STS_OK )
{
/* no breakouts;
depending on device ID, some HW blocks might not be available */
data |= ( (u32_t)status ) << 16;
}
registers[i].data = data;
i++;
}
/* all done, all OK (any errors are saved inside data) */
return DRX_STS_OK;
u16_t i = 0;
if (registers == NULL) {
/* registers not supplied */
return DRX_STS_INVALID_ARG;
}
/* start dumping registers */
while (registers[i].address != 0) {
DRXStatus_t status = DRX_STS_ERROR;
u16_t value = 0;
u32_t data = 0;
status =
demod->myAccessFunct->readReg16Func(demod->myI2CDevAddr,
registers[i].address,
&value, 0);
data = (u32_t) value;
if (status != DRX_STS_OK) {
/* no breakouts;
depending on device ID, some HW blocks might not be available */
data |= ((u32_t) status) << 16;
}
registers[i].data = data;
i++;
}
/* all done, all OK (any errors are saved inside data) */
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -955,18 +891,17 @@ DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod,
* host and the data contained in the microcode image file.
*
*/
static u16_t
UCodeRead16( pu8_t addr)
static u16_t UCodeRead16(pu8_t addr)
{
/* Works fo any host processor */
/* Works fo any host processor */
u16_t word=0;
u16_t word = 0;
word = ((u16_t)addr[0]);
word <<= 8;
word |=((u16_t)addr[1]);
word = ((u16_t) addr[0]);
word <<= 8;
word |= ((u16_t) addr[1]);
return word;
return word;
}
/*============================================================================*/
......@@ -980,22 +915,21 @@ UCodeRead16( pu8_t addr)
* host and the data contained in the microcode image file.
*
*/
static u32_t
UCodeRead32( pu8_t addr)
static u32_t UCodeRead32(pu8_t addr)
{
/* Works fo any host processor */
/* Works fo any host processor */
u32_t word=0;
u32_t word = 0;
word = ((u16_t)addr[0]);
word <<= 8;
word |= ((u16_t)addr[1]);
word <<= 8;
word |= ((u16_t)addr[2]);
word <<= 8;
word |= ((u16_t)addr[3]);
word = ((u16_t) addr[0]);
word <<= 8;
word |= ((u16_t) addr[1]);
word <<= 8;
word |= ((u16_t) addr[2]);
word <<= 8;
word |= ((u16_t) addr[3]);
return word ;
return word;
}
/*============================================================================*/
......@@ -1006,30 +940,26 @@ UCodeRead32( pu8_t addr)
* \param nrWords: Size of microcode block (number of 16 bits words).
* \return u16_t The computed CRC residu.
*/
static u16_t
UCodeComputeCRC (pu8_t blockData, u16_t nrWords)
static u16_t UCodeComputeCRC(pu8_t blockData, u16_t nrWords)
{
u16_t i = 0;
u16_t j = 0;
u32_t CRCWord = 0;
u32_t carry = 0;
while ( i < nrWords )
{
CRCWord |= (u32_t) UCodeRead16(blockData);
for (j = 0; j < 16; j++)
{
CRCWord <<= 1;
if (carry != 0)
{
CRCWord ^= 0x80050000UL;
}
carry = CRCWord & 0x80000000UL;
}
i++;
blockData+=(sizeof(u16_t));
}
return ((u16_t) (CRCWord >> 16));
u16_t i = 0;
u16_t j = 0;
u32_t CRCWord = 0;
u32_t carry = 0;
while (i < nrWords) {
CRCWord |= (u32_t) UCodeRead16(blockData);
for (j = 0; j < 16; j++) {
CRCWord <<= 1;
if (carry != 0) {
CRCWord ^= 0x80050000UL;
}
carry = CRCWord & 0x80000000UL;
}
i++;
blockData += (sizeof(u16_t));
}
return ((u16_t) (CRCWord >> 16));
}
/*============================================================================*/
......@@ -1053,213 +983,213 @@ UCodeComputeCRC (pu8_t blockData, u16_t nrWords)
* - Provided image is corrupt
*/
static DRXStatus_t
CtrlUCode( pDRXDemodInstance_t demod,
pDRXUCodeInfo_t mcInfo,
DRXUCodeAction_t action)
CtrlUCode(pDRXDemodInstance_t demod,
pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action)
{
DRXStatus_t rc;
u16_t i = 0;
u16_t mcNrOfBlks = 0;
u16_t mcMagicWord = 0;
pu8_t mcData = (pu8_t)(NULL);
pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL);
devAddr = demod -> myI2CDevAddr;
/* Check arguments */
if ( ( mcInfo == NULL ) ||
( mcInfo->mcData == NULL ) )
{
return DRX_STS_INVALID_ARG;
}
mcData = mcInfo->mcData;
/* Check data */
mcMagicWord = UCodeRead16( mcData );
mcData += sizeof( u16_t );
mcNrOfBlks = UCodeRead16( mcData );
mcData += sizeof( u16_t );
if ( ( mcMagicWord != DRX_UCODE_MAGIC_WORD ) ||
( mcNrOfBlks == 0 ) )
{
/* wrong endianess or wrong data ? */
return DRX_STS_INVALID_ARG;
}
/* Scan microcode blocks first for version info if uploading */
if (action == UCODE_UPLOAD)
{
/* Clear version block */
DRX_SET_MCVERTYPE (demod, 0);
DRX_SET_MCDEV (demod, 0);
DRX_SET_MCVERSION (demod, 0);
DRX_SET_MCPATCH (demod, 0);
for (i = 0; i < mcNrOfBlks; i++)
{
DRXUCodeBlockHdr_t blockHdr;
/* Process block header */
blockHdr.addr = UCodeRead32( mcData );
mcData += sizeof(u32_t);
blockHdr.size = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.flags = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.CRC = UCodeRead16( mcData );
mcData += sizeof(u16_t);
if (blockHdr.flags & 0x8)
{
/* Aux block. Check type */
pu8_t auxblk = mcInfo->mcData + blockHdr.addr;
u16_t auxtype = UCodeRead16 (auxblk);
if (DRX_ISMCVERTYPE (auxtype))
{
DRX_SET_MCVERTYPE (demod, UCodeRead16 (auxblk));
auxblk += sizeof (u16_t);
DRX_SET_MCDEV (demod, UCodeRead32 (auxblk));
auxblk += sizeof (u32_t);
DRX_SET_MCVERSION (demod, UCodeRead32 (auxblk));
auxblk += sizeof (u32_t);
DRX_SET_MCPATCH (demod, UCodeRead32 (auxblk));
}
}
/* Next block */
mcData += blockHdr.size * sizeof (u16_t);
}
/* After scanning, validate the microcode.
It is also valid if no validation control exists.
*/
rc = DRX_Ctrl (demod, DRX_CTRL_VALIDATE_UCODE, NULL);
if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE)
{
return rc;
}
/* Restore data pointer */
mcData = mcInfo->mcData + 2 * sizeof( u16_t );
}
/* Process microcode blocks */
for( i = 0 ; i<mcNrOfBlks ; i++ )
{
DRXUCodeBlockHdr_t blockHdr;
u16_t mcBlockNrBytes = 0;
/* Process block header */
blockHdr.addr = UCodeRead32( mcData );
mcData += sizeof(u32_t);
blockHdr.size = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.flags = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.CRC = UCodeRead16( mcData );
mcData += sizeof(u16_t);
/* Check block header on:
- data larger than 64Kb
- if CRC enabled check CRC
*/
if ( ( blockHdr.size > 0x7FFF ) ||
( ( ( blockHdr.flags & DRX_UCODE_CRC_FLAG ) != 0 ) &&
( blockHdr.CRC != UCodeComputeCRC ( mcData, blockHdr.size) ) )
)
{
/* Wrong data ! */
return DRX_STS_INVALID_ARG;
}
mcBlockNrBytes = blockHdr.size * ((u16_t)sizeof( u16_t ));
if ( blockHdr.size != 0 )
{
/* Perform the desired action */
switch ( action ) {
DRXStatus_t rc;
u16_t i = 0;
u16_t mcNrOfBlks = 0;
u16_t mcMagicWord = 0;
pu8_t mcData = (pu8_t) (NULL);
pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t) (NULL);
devAddr = demod->myI2CDevAddr;
/* Check arguments */
if ((mcInfo == NULL) || (mcInfo->mcData == NULL)) {
return DRX_STS_INVALID_ARG;
}
mcData = mcInfo->mcData;
/* Check data */
mcMagicWord = UCodeRead16(mcData);
mcData += sizeof(u16_t);
mcNrOfBlks = UCodeRead16(mcData);
mcData += sizeof(u16_t);
if ((mcMagicWord != DRX_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) {
/* wrong endianess or wrong data ? */
return DRX_STS_INVALID_ARG;
}
/* Scan microcode blocks first for version info if uploading */
if (action == UCODE_UPLOAD) {
/* Clear version block */
DRX_SET_MCVERTYPE(demod, 0);
DRX_SET_MCDEV(demod, 0);
DRX_SET_MCVERSION(demod, 0);
DRX_SET_MCPATCH(demod, 0);
for (i = 0; i < mcNrOfBlks; i++) {
DRXUCodeBlockHdr_t blockHdr;
/* Process block header */
blockHdr.addr = UCodeRead32(mcData);
mcData += sizeof(u32_t);
blockHdr.size = UCodeRead16(mcData);
mcData += sizeof(u16_t);
blockHdr.flags = UCodeRead16(mcData);
mcData += sizeof(u16_t);
blockHdr.CRC = UCodeRead16(mcData);
mcData += sizeof(u16_t);
if (blockHdr.flags & 0x8) {
/* Aux block. Check type */
pu8_t auxblk = mcInfo->mcData + blockHdr.addr;
u16_t auxtype = UCodeRead16(auxblk);
if (DRX_ISMCVERTYPE(auxtype)) {
DRX_SET_MCVERTYPE(demod,
UCodeRead16(auxblk));
auxblk += sizeof(u16_t);
DRX_SET_MCDEV(demod,
UCodeRead32(auxblk));
auxblk += sizeof(u32_t);
DRX_SET_MCVERSION(demod,
UCodeRead32(auxblk));
auxblk += sizeof(u32_t);
DRX_SET_MCPATCH(demod,
UCodeRead32(auxblk));
}
}
/* Next block */
mcData += blockHdr.size * sizeof(u16_t);
}
/* After scanning, validate the microcode.
It is also valid if no validation control exists.
*/
rc = DRX_Ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL);
if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) {
return rc;
}
/* Restore data pointer */
mcData = mcInfo->mcData + 2 * sizeof(u16_t);
}
/* Process microcode blocks */
for (i = 0; i < mcNrOfBlks; i++) {
DRXUCodeBlockHdr_t blockHdr;
u16_t mcBlockNrBytes = 0;
/* Process block header */
blockHdr.addr = UCodeRead32(mcData);
mcData += sizeof(u32_t);
blockHdr.size = UCodeRead16(mcData);
mcData += sizeof(u16_t);
blockHdr.flags = UCodeRead16(mcData);
mcData += sizeof(u16_t);
blockHdr.CRC = UCodeRead16(mcData);
mcData += sizeof(u16_t);
/* Check block header on:
- data larger than 64Kb
- if CRC enabled check CRC
*/
if ((blockHdr.size > 0x7FFF) ||
(((blockHdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
(blockHdr.CRC != UCodeComputeCRC(mcData, blockHdr.size)))
) {
/* Wrong data ! */
return DRX_STS_INVALID_ARG;
}
mcBlockNrBytes = blockHdr.size * ((u16_t) sizeof(u16_t));
if (blockHdr.size != 0) {
/* Perform the desired action */
switch (action) {
/*================================================================*/
case UCODE_UPLOAD :
{
/* Upload microcode */
if ( demod->myAccessFunct->writeBlockFunc(
devAddr,
(DRXaddr_t) blockHdr.addr,
mcBlockNrBytes,
mcData,
0x0000) != DRX_STS_OK)
{
return (DRX_STS_ERROR);
} /* if */
};
break;
case UCODE_UPLOAD:
{
/* Upload microcode */
if (demod->myAccessFunct->
writeBlockFunc(devAddr,
(DRXaddr_t) blockHdr.
addr, mcBlockNrBytes,
mcData,
0x0000) !=
DRX_STS_OK) {
return (DRX_STS_ERROR);
} /* if */
};
break;
/*================================================================*/
case UCODE_VERIFY :
{
int result = 0;
u8_t mcDataBuffer[DRX_UCODE_MAX_BUF_SIZE];
u32_t bytesToCompare=0;
u32_t bytesLeftToCompare=0;
DRXaddr_t currAddr = (DRXaddr_t)0;
pu8_t currPtr =NULL;
bytesLeftToCompare = mcBlockNrBytes;
currAddr = blockHdr.addr;
currPtr = mcData;
while( bytesLeftToCompare != 0 )
{
if (bytesLeftToCompare > ( (u32_t)DRX_UCODE_MAX_BUF_SIZE) )
{
bytesToCompare = ( (u32_t)DRX_UCODE_MAX_BUF_SIZE );
}
else
{
bytesToCompare = bytesLeftToCompare;
}
if ( demod->myAccessFunct->readBlockFunc(
devAddr,
currAddr,
(u16_t)bytesToCompare,
(pu8_t)mcDataBuffer,
0x0000) != DRX_STS_OK)
{
return (DRX_STS_ERROR);
}
result = DRXBSP_HST_Memcmp( currPtr,
mcDataBuffer,
bytesToCompare);
if ( result != 0 )
{
return DRX_STS_ERROR;
}
currAddr += ((DRXaddr_t)(bytesToCompare/2));
currPtr = &(currPtr[bytesToCompare]);
bytesLeftToCompare -= ((u32_t)bytesToCompare);
} /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */
};
break;
case UCODE_VERIFY:
{
int result = 0;
u8_t mcDataBuffer
[DRX_UCODE_MAX_BUF_SIZE];
u32_t bytesToCompare = 0;
u32_t bytesLeftToCompare = 0;
DRXaddr_t currAddr = (DRXaddr_t) 0;
pu8_t currPtr = NULL;
bytesLeftToCompare = mcBlockNrBytes;
currAddr = blockHdr.addr;
currPtr = mcData;
while (bytesLeftToCompare != 0) {
if (bytesLeftToCompare >
((u32_t)
DRX_UCODE_MAX_BUF_SIZE)) {
bytesToCompare =
((u32_t)
DRX_UCODE_MAX_BUF_SIZE);
} else {
bytesToCompare =
bytesLeftToCompare;
}
if (demod->myAccessFunct->
readBlockFunc(devAddr,
currAddr,
(u16_t)
bytesToCompare,
(pu8_t)
mcDataBuffer,
0x0000) !=
DRX_STS_OK) {
return (DRX_STS_ERROR);
}
result =
DRXBSP_HST_Memcmp(currPtr,
mcDataBuffer,
bytesToCompare);
if (result != 0) {
return DRX_STS_ERROR;
}
currAddr +=
((DRXaddr_t)
(bytesToCompare / 2));
currPtr =
&(currPtr[bytesToCompare]);
bytesLeftToCompare -=
((u32_t) bytesToCompare);
} /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */
};
break;
/*================================================================*/
default:
return DRX_STS_INVALID_ARG;
break;
default:
return DRX_STS_INVALID_ARG;
break;
} /* switch ( action ) */
} /* if (blockHdr.size != 0 ) */
} /* switch ( action ) */
}
/* Next block */
mcData += mcBlockNrBytes;
/* if (blockHdr.size != 0 ) */
/* Next block */
mcData += mcBlockNrBytes;
} /* for( i = 0 ; i<mcNrOfBlks ; i++ ) */
} /* for( i = 0 ; i<mcNrOfBlks ; i++ ) */
return DRX_STS_OK;
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -1273,63 +1203,57 @@ CtrlUCode( pDRXDemodInstance_t demod,
* \retval DRX_STS_INVALID_ARG: Invalid arguments.
*/
static DRXStatus_t
CtrlVersion( pDRXDemodInstance_t demod,
pDRXVersionList_t *versionList )
CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t * versionList)
{
static char drxDriverCoreModuleName[] = "Core driver";
static char drxDriverCoreVersionText[] =
DRX_VERSIONSTRING( VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH );
static DRXVersion_t drxDriverCoreVersion;
static DRXVersionList_t drxDriverCoreVersionList;
pDRXVersionList_t demodVersionList = (pDRXVersionList_t)(NULL);
DRXStatus_t returnStatus = DRX_STS_ERROR;
/* Check arguments */
if ( versionList == NULL )
{
return DRX_STS_INVALID_ARG;
}
/* Get version info list from demod */
returnStatus = (*(demod->myDemodFunct->ctrlFunc))(
demod,
DRX_CTRL_VERSION,
(void *) &demodVersionList );
/* Always fill in the information of the driver SW . */
drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE;
drxDriverCoreVersion.moduleName = drxDriverCoreModuleName;
drxDriverCoreVersion.vMajor = VERSION_MAJOR;
drxDriverCoreVersion.vMinor = VERSION_MINOR;
drxDriverCoreVersion.vPatch = VERSION_PATCH;
drxDriverCoreVersion.vString = drxDriverCoreVersionText;
drxDriverCoreVersionList.version = &drxDriverCoreVersion;
drxDriverCoreVersionList.next = (pDRXVersionList_t)(NULL);
if ( ( returnStatus == DRX_STS_OK ) && ( demodVersionList != NULL ) )
{
/* Append versioninfo from driver to versioninfo from demod */
/* Return version info in "bottom-up" order. This way, multiple
devices can be handled without using malloc. */
pDRXVersionList_t currentListElement = demodVersionList;
while ( currentListElement->next != NULL )
{
currentListElement = currentListElement->next;
}
currentListElement->next = &drxDriverCoreVersionList;
*versionList = demodVersionList;
}
else
{
/* Just return versioninfo from driver */
*versionList = &drxDriverCoreVersionList;
}
return DRX_STS_OK;
static char drxDriverCoreModuleName[] = "Core driver";
static char drxDriverCoreVersionText[] =
DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH);
static DRXVersion_t drxDriverCoreVersion;
static DRXVersionList_t drxDriverCoreVersionList;
pDRXVersionList_t demodVersionList = (pDRXVersionList_t) (NULL);
DRXStatus_t returnStatus = DRX_STS_ERROR;
/* Check arguments */
if (versionList == NULL) {
return DRX_STS_INVALID_ARG;
}
/* Get version info list from demod */
returnStatus = (*(demod->myDemodFunct->ctrlFunc)) (demod,
DRX_CTRL_VERSION,
(void *)
&demodVersionList);
/* Always fill in the information of the driver SW . */
drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE;
drxDriverCoreVersion.moduleName = drxDriverCoreModuleName;
drxDriverCoreVersion.vMajor = VERSION_MAJOR;
drxDriverCoreVersion.vMinor = VERSION_MINOR;
drxDriverCoreVersion.vPatch = VERSION_PATCH;
drxDriverCoreVersion.vString = drxDriverCoreVersionText;
drxDriverCoreVersionList.version = &drxDriverCoreVersion;
drxDriverCoreVersionList.next = (pDRXVersionList_t) (NULL);
if ((returnStatus == DRX_STS_OK) && (demodVersionList != NULL)) {
/* Append versioninfo from driver to versioninfo from demod */
/* Return version info in "bottom-up" order. This way, multiple
devices can be handled without using malloc. */
pDRXVersionList_t currentListElement = demodVersionList;
while (currentListElement->next != NULL) {
currentListElement = currentListElement->next;
}
currentListElement->next = &drxDriverCoreVersionList;
*versionList = demodVersionList;
} else {
/* Just return versioninfo from driver */
*versionList = &drxDriverCoreVersionList;
}
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -1338,8 +1262,6 @@ CtrlVersion( pDRXDemodInstance_t demod,
/*============================================================================*/
/*============================================================================*/
/**
* \brief This function is obsolete.
* \param demods: Don't care, parameter is ignored.
......@@ -1350,10 +1272,9 @@ CtrlVersion( pDRXDemodInstance_t demod,
*
*/
DRXStatus_t
DRX_Init( pDRXDemodInstance_t demods[] )
DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[])
{
return DRX_STS_OK;
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -1367,10 +1288,9 @@ DRX_Init( pDRXDemodInstance_t demods[] )
*
*/
DRXStatus_t
DRX_Term( void )
DRXStatus_t DRX_Term(void)
{
return DRX_STS_OK;
return DRX_STS_OK;
}
/*============================================================================*/
......@@ -1386,29 +1306,26 @@ DRX_Term( void )
*
*/
DRXStatus_t
DRX_Open(pDRXDemodInstance_t demod)
DRXStatus_t DRX_Open(pDRXDemodInstance_t demod)
{
DRXStatus_t status = DRX_STS_OK;
if ( ( demod == NULL ) ||
( demod->myDemodFunct == NULL ) ||
( demod->myCommonAttr == NULL ) ||
( demod->myExtAttr == NULL ) ||
( demod->myI2CDevAddr == NULL ) ||
( demod->myCommonAttr->isOpened == TRUE ))
{
return (DRX_STS_INVALID_ARG);
}
status = (*(demod->myDemodFunct->openFunc))( demod );
if ( status == DRX_STS_OK )
{
demod->myCommonAttr->isOpened = TRUE;
}
return status;
DRXStatus_t status = DRX_STS_OK;
if ((demod == NULL) ||
(demod->myDemodFunct == NULL) ||
(demod->myCommonAttr == NULL) ||
(demod->myExtAttr == NULL) ||
(demod->myI2CDevAddr == NULL) ||
(demod->myCommonAttr->isOpened == TRUE)) {
return (DRX_STS_INVALID_ARG);
}
status = (*(demod->myDemodFunct->openFunc)) (demod);
if (status == DRX_STS_OK) {
demod->myCommonAttr->isOpened = TRUE;
}
return status;
}
/*============================================================================*/
......@@ -1426,26 +1343,24 @@ DRX_Open(pDRXDemodInstance_t demod)
* Put device into sleep mode.
*/
DRXStatus_t
DRX_Close(pDRXDemodInstance_t demod)
DRXStatus_t DRX_Close(pDRXDemodInstance_t demod)
{
DRXStatus_t status = DRX_STS_OK;
DRXStatus_t status = DRX_STS_OK;
if ( ( demod == NULL ) ||
( demod->myDemodFunct == NULL ) ||
( demod->myCommonAttr == NULL ) ||
( demod->myExtAttr == NULL ) ||
( demod->myI2CDevAddr == NULL ) ||
( demod->myCommonAttr->isOpened == FALSE ))
{
return DRX_STS_INVALID_ARG;
}
if ((demod == NULL) ||
(demod->myDemodFunct == NULL) ||
(demod->myCommonAttr == NULL) ||
(demod->myExtAttr == NULL) ||
(demod->myI2CDevAddr == NULL) ||
(demod->myCommonAttr->isOpened == FALSE)) {
return DRX_STS_INVALID_ARG;
}
status = (*(demod->myDemodFunct->closeFunc))( demod );
status = (*(demod->myDemodFunct->closeFunc)) (demod);
DRX_SET_ISOPENED (demod, FALSE);
DRX_SET_ISOPENED(demod, FALSE);
return status;
return status;
}
/*============================================================================*/
......@@ -1471,130 +1386,125 @@ DRX_Close(pDRXDemodInstance_t demod)
DRXStatus_t
DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData)
{
DRXStatus_t status = DRX_STS_ERROR;
if ( ( demod == NULL ) ||
( demod->myDemodFunct == NULL ) ||
( demod->myCommonAttr == NULL ) ||
( demod->myExtAttr == NULL ) ||
( demod->myI2CDevAddr == NULL )
)
{
return (DRX_STS_INVALID_ARG);
}
if ( ( ( demod->myCommonAttr->isOpened == FALSE ) &&
( ctrl != DRX_CTRL_PROBE_DEVICE ) &&
( ctrl != DRX_CTRL_VERSION) )
)
{
return (DRX_STS_INVALID_ARG);
}
if ( ( DRX_ISPOWERDOWNMODE( demod->myCommonAttr->currentPowerMode ) &&
( ctrl != DRX_CTRL_POWER_MODE ) &&
( ctrl != DRX_CTRL_PROBE_DEVICE ) &&
( ctrl != DRX_CTRL_NOP ) &&
( ctrl != DRX_CTRL_VERSION)
)
)
{
return DRX_STS_FUNC_NOT_AVAILABLE;
}
/* Fixed control functions */
switch ( ctrl ) {
DRXStatus_t status = DRX_STS_ERROR;
if ((demod == NULL) ||
(demod->myDemodFunct == NULL) ||
(demod->myCommonAttr == NULL) ||
(demod->myExtAttr == NULL) || (demod->myI2CDevAddr == NULL)
) {
return (DRX_STS_INVALID_ARG);
}
if (((demod->myCommonAttr->isOpened == FALSE) &&
(ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION))
) {
return (DRX_STS_INVALID_ARG);
}
if ((DRX_ISPOWERDOWNMODE(demod->myCommonAttr->currentPowerMode) &&
(ctrl != DRX_CTRL_POWER_MODE) &&
(ctrl != DRX_CTRL_PROBE_DEVICE) &&
(ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION)
)
) {
return DRX_STS_FUNC_NOT_AVAILABLE;
}
/* Fixed control functions */
switch (ctrl) {
/*======================================================================*/
case DRX_CTRL_NOP:
/* No operation */
return DRX_STS_OK;
break;
case DRX_CTRL_NOP:
/* No operation */
return DRX_STS_OK;
break;
/*======================================================================*/
case DRX_CTRL_VERSION:
return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData );
break;
case DRX_CTRL_VERSION:
return CtrlVersion(demod, (pDRXVersionList_t *) ctrlData);
break;
/*======================================================================*/
default :
/* Do nothing */
break;
}
/* Virtual functions */
/* First try calling function from derived class */
status = (*(demod->myDemodFunct->ctrlFunc))( demod, ctrl, ctrlData );
if (status == DRX_STS_FUNC_NOT_AVAILABLE)
{
/* Now try calling a the base class function */
switch ( ctrl ) {
default:
/* Do nothing */
break;
}
/* Virtual functions */
/* First try calling function from derived class */
status = (*(demod->myDemodFunct->ctrlFunc)) (demod, ctrl, ctrlData);
if (status == DRX_STS_FUNC_NOT_AVAILABLE) {
/* Now try calling a the base class function */
switch (ctrl) {
/*===================================================================*/
case DRX_CTRL_LOAD_UCODE:
return CtrlUCode ( demod,
(pDRXUCodeInfo_t) ctrlData,
UCODE_UPLOAD );
break;
case DRX_CTRL_LOAD_UCODE:
return CtrlUCode(demod,
(pDRXUCodeInfo_t) ctrlData,
UCODE_UPLOAD);
break;
/*===================================================================*/
case DRX_CTRL_VERIFY_UCODE:
{
return CtrlUCode ( demod,
(pDRXUCodeInfo_t) ctrlData,
UCODE_VERIFY);
}
break;
case DRX_CTRL_VERIFY_UCODE:
{
return CtrlUCode(demod,
(pDRXUCodeInfo_t) ctrlData,
UCODE_VERIFY);
}
break;
#ifndef DRX_EXCLUDE_SCAN
/*===================================================================*/
case DRX_CTRL_SCAN_INIT:
{
return CtrlScanInit( demod, (pDRXScanParam_t) ctrlData );
}
break;
case DRX_CTRL_SCAN_INIT:
{
return CtrlScanInit(demod,
(pDRXScanParam_t) ctrlData);
}
break;
/*===================================================================*/
case DRX_CTRL_SCAN_NEXT:
{
return CtrlScanNext( demod, (pu16_t) ctrlData );
}
break;
case DRX_CTRL_SCAN_NEXT:
{
return CtrlScanNext(demod, (pu16_t) ctrlData);
}
break;
/*===================================================================*/
case DRX_CTRL_SCAN_STOP:
{
return CtrlScanStop( demod );
}
break;
case DRX_CTRL_SCAN_STOP:
{
return CtrlScanStop(demod);
}
break;
#endif /* #ifndef DRX_EXCLUDE_SCAN */
/*===================================================================*/
case DRX_CTRL_PROGRAM_TUNER:
{
return CtrlProgramTuner( demod, (pDRXChannel_t) ctrlData );
}
break;
case DRX_CTRL_PROGRAM_TUNER:
{
return CtrlProgramTuner(demod,
(pDRXChannel_t)
ctrlData);
}
break;
/*===================================================================*/
case DRX_CTRL_DUMP_REGISTERS:
{
return CtrlDumpRegisters( demod, (pDRXRegDump_t) ctrlData );
}
break;
case DRX_CTRL_DUMP_REGISTERS:
{
return CtrlDumpRegisters(demod,
(pDRXRegDump_t)
ctrlData);
}
break;
/*===================================================================*/
default :
return DRX_STS_FUNC_NOT_AVAILABLE;
}
}
else
{
return (status);
}
return DRX_STS_OK;
default:
return DRX_STS_FUNC_NOT_AVAILABLE;
}
} else {
return (status);
}
return DRX_STS_OK;
}
/*============================================================================*/
/* END OF FILE */
drivers/media/dvb-frontends/drx39xyj/drx_driver.h
View file @ 443f18d0
......@@ -140,7 +140,6 @@ DEFINES
#define DRX_AUTO (255)
#endif
/**************
*
* This section describes flag definitions for the device capbilities.
......@@ -295,258 +294,292 @@ ENUM
* \enum DRXStandard_t
* \brief Modulation standards.
*/
typedef enum {
DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
DRX_STANDARD_PAL_SECAM_BG, /**< Terrestrial analog PAL/SECAM B/G */
DRX_STANDARD_PAL_SECAM_DK, /**< Terrestrial analog PAL/SECAM D/K */
DRX_STANDARD_PAL_SECAM_I, /**< Terrestrial analog PAL/SECAM I */
DRX_STANDARD_PAL_SECAM_L, /**< Terrestrial analog PAL/SECAM L
typedef enum {
DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
DRX_STANDARD_PAL_SECAM_BG,
/**< Terrestrial analog PAL/SECAM B/G */
DRX_STANDARD_PAL_SECAM_DK,
/**< Terrestrial analog PAL/SECAM D/K */
DRX_STANDARD_PAL_SECAM_I,
/**< Terrestrial analog PAL/SECAM I */
DRX_STANDARD_PAL_SECAM_L,
/**< Terrestrial analog PAL/SECAM L
with negative modulation */
DRX_STANDARD_PAL_SECAM_LP, /**< Terrestrial analog PAL/SECAM L
DRX_STANDARD_PAL_SECAM_LP,
/**< Terrestrial analog PAL/SECAM L
with positive modulation */
DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, /**< Standard unknown. */
DRX_STANDARD_AUTO = DRX_AUTO /**< Autodetect standard. */
} DRXStandard_t, *pDRXStandard_t;
DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
DRX_STANDARD_UNKNOWN = DRX_UNKNOWN,
/**< Standard unknown. */
DRX_STANDARD_AUTO = DRX_AUTO
/**< Autodetect standard. */
} DRXStandard_t, *pDRXStandard_t;
/**
* \enum DRXStandard_t
* \brief Modulation sub-standards.
*/
typedef enum {
DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
DRX_SUBSTANDARD_ATV_DK_POLAND,
DRX_SUBSTANDARD_ATV_DK_CHINA,
DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, /**< Sub-standard unknown. */
DRX_SUBSTANDARD_AUTO = DRX_AUTO /**< Auto (default) sub-standard */
} DRXSubstandard_t, *pDRXSubstandard_t;
typedef enum {
DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
DRX_SUBSTANDARD_ATV_DK_POLAND,
DRX_SUBSTANDARD_ATV_DK_CHINA,
DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN,
/**< Sub-standard unknown. */
DRX_SUBSTANDARD_AUTO = DRX_AUTO
/**< Auto (default) sub-standard */
} DRXSubstandard_t, *pDRXSubstandard_t;
/**
* \enum DRXBandwidth_t
* \brief Channel bandwidth or channel spacing.
*/
typedef enum {
DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, /**< Bandwidth unknown. */
DRX_BANDWIDTH_AUTO = DRX_AUTO /**< Auto Set Bandwidth */
} DRXBandwidth_t, *pDRXBandwidth_t;
typedef enum {
DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN,
/**< Bandwidth unknown. */
DRX_BANDWIDTH_AUTO = DRX_AUTO
/**< Auto Set Bandwidth */
} DRXBandwidth_t, *pDRXBandwidth_t;
/**
* \enum DRXMirror_t
* \brief Indicate if channel spectrum is mirrored or not.
*/
typedef enum {
DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
DRX_MIRROR_YES, /**< Spectrum is mirrored. */
DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, /**< Unknown if spectrum is mirrored. */
DRX_MIRROR_AUTO = DRX_AUTO /**< Autodetect if spectrum is mirrored. */
} DRXMirror_t, *pDRXMirror_t;
typedef enum {
DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
DRX_MIRROR_YES, /**< Spectrum is mirrored. */
DRX_MIRROR_UNKNOWN = DRX_UNKNOWN,
/**< Unknown if spectrum is mirrored. */
DRX_MIRROR_AUTO = DRX_AUTO
/**< Autodetect if spectrum is mirrored. */
} DRXMirror_t, *pDRXMirror_t;
/**
* \enum DRXConstellation_t
* \brief Constellation type of the channel.
*/
typedef enum {
DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, /**< Constellation unknown. */
DRX_CONSTELLATION_AUTO = DRX_AUTO /**< Autodetect constellation. */
} DRXConstellation_t, *pDRXConstellation_t;
typedef enum {
DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
/**< Constellation unknown. */
DRX_CONSTELLATION_AUTO = DRX_AUTO
/**< Autodetect constellation. */
} DRXConstellation_t, *pDRXConstellation_t;
/**
* \enum DRXHierarchy_t
* \brief Hierarchy of the channel.
*/
typedef enum {
DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, /**< Hierarchy unknown. */
DRX_HIERARCHY_AUTO = DRX_AUTO /**< Autodetect hierarchy. */
} DRXHierarchy_t, *pDRXHierarchy_t;
typedef enum {
DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN,
/**< Hierarchy unknown. */
DRX_HIERARCHY_AUTO = DRX_AUTO
/**< Autodetect hierarchy. */
} DRXHierarchy_t, *pDRXHierarchy_t;
/**
* \enum DRXPriority_t
* \brief Channel priority in case of hierarchical transmission.
*/
typedef enum {
DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
DRX_PRIORITY_HIGH, /**< High priority channel. */
DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN /**< Priority unknown. */
} DRXPriority_t, *pDRXPriority_t;
typedef enum {
DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
DRX_PRIORITY_HIGH, /**< High priority channel. */
DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN
/**< Priority unknown. */
} DRXPriority_t, *pDRXPriority_t;
/**
* \enum DRXCoderate_t
* \brief Channel priority in case of hierarchical transmission.
*/
typedef enum {
DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, /**< Code rate unknown. */
DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */
} DRXCoderate_t, *pDRXCoderate_t;
typedef enum {
DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
DRX_CODERATE_UNKNOWN = DRX_UNKNOWN,
/**< Code rate unknown. */
DRX_CODERATE_AUTO = DRX_AUTO
/**< Autodetect code rate. */
} DRXCoderate_t, *pDRXCoderate_t;
/**
* \enum DRXGuard_t
* \brief Guard interval of a channel.
*/
typedef enum {
DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
DRX_GUARD_UNKNOWN = DRX_UNKNOWN, /**< Guard interval unknown. */
DRX_GUARD_AUTO = DRX_AUTO /**< Autodetect guard interval. */
} DRXGuard_t, *pDRXGuard_t;
typedef enum {
DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
DRX_GUARD_UNKNOWN = DRX_UNKNOWN,
/**< Guard interval unknown. */
DRX_GUARD_AUTO = DRX_AUTO
/**< Autodetect guard interval. */
} DRXGuard_t, *pDRXGuard_t;
/**
* \enum DRXFftmode_t
* \brief FFT mode.
*/
typedef enum {
DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
DRX_FFTMODE_4K, /**< 4K FFT mode. */
DRX_FFTMODE_8K, /**< 8K FFT mode. */
DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, /**< FFT mode unknown. */
DRX_FFTMODE_AUTO = DRX_AUTO /**< Autodetect FFT mode. */
} DRXFftmode_t, *pDRXFftmode_t;
typedef enum {
DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
DRX_FFTMODE_4K, /**< 4K FFT mode. */
DRX_FFTMODE_8K, /**< 8K FFT mode. */
DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
/**< FFT mode unknown. */
DRX_FFTMODE_AUTO = DRX_AUTO
/**< Autodetect FFT mode. */
} DRXFftmode_t, *pDRXFftmode_t;
/**
* \enum DRXClassification_t
* \brief Channel classification.
*/
typedef enum {
DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
DRX_CLASSIFICATION_STATIC, /**< Static echo. */
DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, /**< Unknown classification */
DRX_CLASSIFICATION_AUTO = DRX_AUTO /**< Autodetect classification. */
} DRXClassification_t, *pDRXClassification_t;
typedef enum {
DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
DRX_CLASSIFICATION_STATIC, /**< Static echo. */
DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN,
/**< Unknown classification */
DRX_CLASSIFICATION_AUTO = DRX_AUTO
/**< Autodetect classification. */
} DRXClassification_t, *pDRXClassification_t;
/**
* /enum DRXInterleaveModes_t
* /brief Interleave modes
*/
typedef enum {
DRX_INTERLEAVEMODE_I128_J1 = 0,
DRX_INTERLEAVEMODE_I128_J1_V2,
DRX_INTERLEAVEMODE_I128_J2,
DRX_INTERLEAVEMODE_I64_J2,
DRX_INTERLEAVEMODE_I128_J3,
DRX_INTERLEAVEMODE_I32_J4,
DRX_INTERLEAVEMODE_I128_J4,
DRX_INTERLEAVEMODE_I16_J8,
DRX_INTERLEAVEMODE_I128_J5,
DRX_INTERLEAVEMODE_I8_J16,
DRX_INTERLEAVEMODE_I128_J6,
DRX_INTERLEAVEMODE_RESERVED_11,
DRX_INTERLEAVEMODE_I128_J7,
DRX_INTERLEAVEMODE_RESERVED_13,
DRX_INTERLEAVEMODE_I128_J8,
DRX_INTERLEAVEMODE_RESERVED_15,
DRX_INTERLEAVEMODE_I12_J17,
DRX_INTERLEAVEMODE_I5_J4,
DRX_INTERLEAVEMODE_B52_M240,
DRX_INTERLEAVEMODE_B52_M720,
DRX_INTERLEAVEMODE_B52_M48,
DRX_INTERLEAVEMODE_B52_M0,
DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, /**< Unknown interleave mode */
DRX_INTERLEAVEMODE_AUTO = DRX_AUTO /**< Autodetect interleave mode */
} DRXInterleaveModes_t, *pDRXInterleaveModes_t;
typedef enum {
DRX_INTERLEAVEMODE_I128_J1 = 0,
DRX_INTERLEAVEMODE_I128_J1_V2,
DRX_INTERLEAVEMODE_I128_J2,
DRX_INTERLEAVEMODE_I64_J2,
DRX_INTERLEAVEMODE_I128_J3,
DRX_INTERLEAVEMODE_I32_J4,
DRX_INTERLEAVEMODE_I128_J4,
DRX_INTERLEAVEMODE_I16_J8,
DRX_INTERLEAVEMODE_I128_J5,
DRX_INTERLEAVEMODE_I8_J16,
DRX_INTERLEAVEMODE_I128_J6,
DRX_INTERLEAVEMODE_RESERVED_11,
DRX_INTERLEAVEMODE_I128_J7,
DRX_INTERLEAVEMODE_RESERVED_13,
DRX_INTERLEAVEMODE_I128_J8,
DRX_INTERLEAVEMODE_RESERVED_15,
DRX_INTERLEAVEMODE_I12_J17,
DRX_INTERLEAVEMODE_I5_J4,
DRX_INTERLEAVEMODE_B52_M240,
DRX_INTERLEAVEMODE_B52_M720,
DRX_INTERLEAVEMODE_B52_M48,
DRX_INTERLEAVEMODE_B52_M0,
DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN,
/**< Unknown interleave mode */
DRX_INTERLEAVEMODE_AUTO = DRX_AUTO
/**< Autodetect interleave mode */
} DRXInterleaveModes_t, *pDRXInterleaveModes_t;
/**
* \enum DRXCarrier_t
* \brief Channel Carrier Mode.
*/
typedef enum {
DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
DRX_CARRIER_SINGLE, /**< Single carrier mode */
DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, /**< Carrier mode unknown. */
DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
} DRXCarrier_t, *pDRXCarrier_t;
typedef enum {
DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
DRX_CARRIER_SINGLE, /**< Single carrier mode */
DRX_CARRIER_UNKNOWN = DRX_UNKNOWN,
/**< Carrier mode unknown. */
DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
} DRXCarrier_t, *pDRXCarrier_t;
/**
* \enum DRXFramemode_t
* \brief Channel Frame Mode.
*/
typedef enum {
DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
DRX_FRAMEMODE_595, /**< 595 */
DRX_FRAMEMODE_945, /**< 945 with variable PN */
DRX_FRAMEMODE_420_FIXED_PN, /**< 420 with fixed PN */
DRX_FRAMEMODE_945_FIXED_PN, /**< 945 with fixed PN */
DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, /**< Frame mode unknown. */
DRX_FRAMEMODE_AUTO = DRX_AUTO /**< Autodetect frame mode */
} DRXFramemode_t, *pDRXFramemode_t;
typedef enum {
DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
DRX_FRAMEMODE_595, /**< 595 */
DRX_FRAMEMODE_945, /**< 945 with variable PN */
DRX_FRAMEMODE_420_FIXED_PN,
/**< 420 with fixed PN */
DRX_FRAMEMODE_945_FIXED_PN,
/**< 945 with fixed PN */
DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN,
/**< Frame mode unknown. */
DRX_FRAMEMODE_AUTO = DRX_AUTO
/**< Autodetect frame mode */
} DRXFramemode_t, *pDRXFramemode_t;
/**
* \enum DRXTPSFrame_t
* \brief Frame number in current super-frame.
*/
typedef enum {
DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
DRX_TPS_FRAME2, /**< TPS frame 2. */
DRX_TPS_FRAME3, /**< TPS frame 3. */
DRX_TPS_FRAME4, /**< TPS frame 4. */
DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN /**< TPS frame unknown. */
} DRXTPSFrame_t, *pDRXTPSFrame_t;
typedef enum {
DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
DRX_TPS_FRAME2, /**< TPS frame 2. */
DRX_TPS_FRAME3, /**< TPS frame 3. */
DRX_TPS_FRAME4, /**< TPS frame 4. */
DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN
/**< TPS frame unknown. */
} DRXTPSFrame_t, *pDRXTPSFrame_t;
/**
* \enum DRXLDPC_t
* \brief TPS LDPC .
*/
typedef enum {
DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
DRX_LDPC_0_6, /**< LDPC 0.6 */
DRX_LDPC_0_8, /**< LDPC 0.8 */
DRX_LDPC_UNKNOWN = DRX_UNKNOWN, /**< LDPC unknown. */
DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
} DRXLDPC_t, *pDRXLDPC_t;
typedef enum {
DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
DRX_LDPC_0_6, /**< LDPC 0.6 */
DRX_LDPC_0_8, /**< LDPC 0.8 */
DRX_LDPC_UNKNOWN = DRX_UNKNOWN,
/**< LDPC unknown. */
DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
} DRXLDPC_t, *pDRXLDPC_t;
/**
* \enum DRXPilotMode_t
* \brief Pilot modes in DTMB.
*/
typedef enum {
DRX_PILOT_ON = 0, /**< Pilot On */
DRX_PILOT_OFF, /**< Pilot Off */
DRX_PILOT_UNKNOWN = DRX_UNKNOWN, /**< Pilot unknown. */
DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
} DRXPilotMode_t, *pDRXPilotMode_t;
typedef enum {
DRX_PILOT_ON = 0, /**< Pilot On */
DRX_PILOT_OFF, /**< Pilot Off */
DRX_PILOT_UNKNOWN = DRX_UNKNOWN,
/**< Pilot unknown. */
DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
} DRXPilotMode_t, *pDRXPilotMode_t;
/**
* \enum DRXCtrlIndex_t
* \brief Indices of the control functions.
*/
typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t;
typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t;
#ifndef DRX_CTRL_BASE
#define DRX_CTRL_BASE ((DRXCtrlIndex_t)0)
......@@ -583,14 +616,14 @@ typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t;
#define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */
#define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */
/* Professional */
/* Professional */
#define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */
#define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */
#define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */
#define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */
#define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */
/* Misc */
/* Misc */
#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */
#define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */
#define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */
......@@ -603,18 +636,19 @@ typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t;
#define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */
#define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */
#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */
#define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */
/**
* \enum DRXUCodeAction_t
* \brief Used to indicate if firmware has to be uploaded or verified.
*/
typedef enum {
UCODE_UPLOAD, /**< Upload the microcode image to device */
UCODE_VERIFY /**< Compare microcode image with code on device */
} DRXUCodeAction_t, *pDRXUCodeAction_t;
typedef enum {
UCODE_UPLOAD,
/**< Upload the microcode image to device */
UCODE_VERIFY
/**< Compare microcode image with code on device */
} DRXUCodeAction_t, *pDRXUCodeAction_t;
/**
* \enum DRXLockStatus_t
......@@ -622,60 +656,71 @@ typedef enum {
*
* The generic lock states have device dependent semantics.
*/
typedef enum{
DRX_NEVER_LOCK = 0, /**< Device will never lock on this signal */
DRX_NOT_LOCKED, /**< Device has no lock at all */
DRX_LOCK_STATE_1, /**< Generic lock state */
DRX_LOCK_STATE_2, /**< Generic lock state */
DRX_LOCK_STATE_3, /**< Generic lock state */
DRX_LOCK_STATE_4, /**< Generic lock state */
DRX_LOCK_STATE_5, /**< Generic lock state */
DRX_LOCK_STATE_6, /**< Generic lock state */
DRX_LOCK_STATE_7, /**< Generic lock state */
DRX_LOCK_STATE_8, /**< Generic lock state */
DRX_LOCK_STATE_9, /**< Generic lock state */
DRX_LOCKED /**< Device is in lock */
} DRXLockStatus_t, *pDRXLockStatus_t;
typedef enum {
DRX_NEVER_LOCK = 0,
/**< Device will never lock on this signal */
DRX_NOT_LOCKED,
/**< Device has no lock at all */
DRX_LOCK_STATE_1,
/**< Generic lock state */
DRX_LOCK_STATE_2,
/**< Generic lock state */
DRX_LOCK_STATE_3,
/**< Generic lock state */
DRX_LOCK_STATE_4,
/**< Generic lock state */
DRX_LOCK_STATE_5,
/**< Generic lock state */
DRX_LOCK_STATE_6,
/**< Generic lock state */
DRX_LOCK_STATE_7,
/**< Generic lock state */
DRX_LOCK_STATE_8,
/**< Generic lock state */
DRX_LOCK_STATE_9,
/**< Generic lock state */
DRX_LOCKED /**< Device is in lock */
} DRXLockStatus_t, *pDRXLockStatus_t;
/**
* \enum DRXUIO_t
* \brief Used to address a User IO (UIO).
*/
typedef enum{
DRX_UIO1 ,
DRX_UIO2 ,
DRX_UIO3 ,
DRX_UIO4 ,
DRX_UIO5 ,
DRX_UIO6 ,
DRX_UIO7 ,
DRX_UIO8 ,
DRX_UIO9 ,
DRX_UIO10 ,
DRX_UIO11 ,
DRX_UIO12 ,
DRX_UIO13 ,
DRX_UIO14 ,
DRX_UIO15 ,
DRX_UIO16 ,
DRX_UIO17 ,
DRX_UIO18 ,
DRX_UIO19 ,
DRX_UIO20 ,
DRX_UIO21 ,
DRX_UIO22 ,
DRX_UIO23 ,
DRX_UIO24 ,
DRX_UIO25 ,
DRX_UIO26 ,
DRX_UIO27 ,
DRX_UIO28 ,
DRX_UIO29 ,
DRX_UIO30 ,
DRX_UIO31 ,
DRX_UIO32 ,
DRX_UIO_MAX = DRX_UIO32
} DRXUIO_t, *pDRXUIO_t;
typedef enum {
DRX_UIO1,
DRX_UIO2,
DRX_UIO3,
DRX_UIO4,
DRX_UIO5,
DRX_UIO6,
DRX_UIO7,
DRX_UIO8,
DRX_UIO9,
DRX_UIO10,
DRX_UIO11,
DRX_UIO12,
DRX_UIO13,
DRX_UIO14,
DRX_UIO15,
DRX_UIO16,
DRX_UIO17,
DRX_UIO18,
DRX_UIO19,
DRX_UIO20,
DRX_UIO21,
DRX_UIO22,
DRX_UIO23,
DRX_UIO24,
DRX_UIO25,
DRX_UIO26,
DRX_UIO27,
DRX_UIO28,
DRX_UIO29,
DRX_UIO30,
DRX_UIO31,
DRX_UIO32,
DRX_UIO_MAX = DRX_UIO32
} DRXUIO_t, *pDRXUIO_t;
/**
* \enum DRXUIOMode_t
......@@ -686,17 +731,26 @@ typedef enum{
* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
* DRX_UIO_MODE_FIRMWARE0.
*/
typedef enum{
DRX_UIO_MODE_DISABLE = 0x01, /**< not used, pin is configured as input */
DRX_UIO_MODE_READWRITE = 0x02, /**< used for read/write by application */
DRX_UIO_MODE_FIRMWARE = 0x04, /**< controlled by firmware, function 0 */
DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE , /**< same as above */
DRX_UIO_MODE_FIRMWARE1 = 0x08, /**< controlled by firmware, function 1 */
DRX_UIO_MODE_FIRMWARE2 = 0x10, /**< controlled by firmware, function 2 */
DRX_UIO_MODE_FIRMWARE3 = 0x20, /**< controlled by firmware, function 3 */
DRX_UIO_MODE_FIRMWARE4 = 0x40, /**< controlled by firmware, function 4 */
DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */
} DRXUIOMode_t, *pDRXUIOMode_t;
typedef enum {
DRX_UIO_MODE_DISABLE = 0x01,
/**< not used, pin is configured as input */
DRX_UIO_MODE_READWRITE = 0x02,
/**< used for read/write by application */
DRX_UIO_MODE_FIRMWARE = 0x04,
/**< controlled by firmware, function 0 */
DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE,
/**< same as above */
DRX_UIO_MODE_FIRMWARE1 = 0x08,
/**< controlled by firmware, function 1 */
DRX_UIO_MODE_FIRMWARE2 = 0x10,
/**< controlled by firmware, function 2 */
DRX_UIO_MODE_FIRMWARE3 = 0x20,
/**< controlled by firmware, function 3 */
DRX_UIO_MODE_FIRMWARE4 = 0x40,
/**< controlled by firmware, function 4 */
DRX_UIO_MODE_FIRMWARE5 = 0x80
/**< controlled by firmware, function 5 */
} DRXUIOMode_t, *pDRXUIOMode_t;
/**
* \enum DRXOOBDownstreamStandard_t
......@@ -704,12 +758,14 @@ typedef enum{
*
* Based on ANSI 55-1 and 55-2
*/
typedef enum {
DRX_OOB_MODE_A = 0, /**< ANSI 55-1 */
DRX_OOB_MODE_B_GRADE_A, /**< ANSI 55-2 A */
DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */
} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t;
typedef enum {
DRX_OOB_MODE_A = 0,
/**< ANSI 55-1 */
DRX_OOB_MODE_B_GRADE_A,
/**< ANSI 55-2 A */
DRX_OOB_MODE_B_GRADE_B
/**< ANSI 55-2 B */
} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t;
/*-------------------------------------------------------------------------
STRUCTS
......@@ -725,31 +781,31 @@ STRUCTS
* \enum DRXCfgType_t
* \brief Generic configuration function identifiers.
*/
typedef u32_t DRXCfgType_t, *pDRXCfgType_t;
typedef u32_t DRXCfgType_t, *pDRXCfgType_t;
#ifndef DRX_CFG_BASE
#define DRX_CFG_BASE ((DRXCfgType_t)0)
#endif
#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */
#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */
#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */
#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */
#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */
#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */
#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */
#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */
#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */
#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */
#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */
#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */
#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */
#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */
#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */
#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */
#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */
#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */
#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */
#define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */
#define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */
#define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */
#define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */
#define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */
#define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */
#define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */
#define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */
#define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */
#define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */
#define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */
#define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */
#define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */
#define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */
#define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */
#define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */
#define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */
#define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */
#define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */
#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
/*============================================================================*/
......@@ -764,10 +820,12 @@ typedef u32_t DRXCfgType_t, *pDRXCfgType_t;
*
* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
*/
typedef struct {
pu8_t mcData; /**< Pointer to microcode image. */
u16_t mcSize; /**< Microcode image size. */
} DRXUCodeInfo_t, *pDRXUCodeInfo_t;
typedef struct {
pu8_t mcData;
/**< Pointer to microcode image. */
u16_t mcSize;
/**< Microcode image size. */
} DRXUCodeInfo_t, *pDRXUCodeInfo_t;
/**
* \struct DRXMcVersionRec_t
......@@ -788,12 +846,12 @@ typedef struct {
*/
#define AUX_VER_RECORD 0x8000
typedef struct {
u16_t auxType; /* type of aux data - 0x8000 for version record */
u32_t mcDevType; /* device type, based on JTAG ID */
u32_t mcVersion; /* version of microcode */
u32_t mcBaseVersion; /* in case of patch: the original microcode version */
} DRXMcVersionRec_t, *pDRXMcVersionRec_t;
typedef struct {
u16_t auxType; /* type of aux data - 0x8000 for version record */
u32_t mcDevType; /* device type, based on JTAG ID */
u32_t mcVersion; /* version of microcode */
u32_t mcBaseVersion; /* in case of patch: the original microcode version */
} DRXMcVersionRec_t, *pDRXMcVersionRec_t;
/*========================================*/
......@@ -803,14 +861,16 @@ typedef struct {
*
* Used by DRX_CTRL_LOAD_FILTER
*/
typedef struct {
pu8_t dataRe; /**< pointer to coefficients for RE */
pu8_t dataIm; /**< pointer to coefficients for IM */
u16_t sizeRe; /**< size of coefficients for RE */
u16_t sizeIm; /**< size of coefficients for IM */
} DRXFilterInfo_t, *pDRXFilterInfo_t;
typedef struct {
pu8_t dataRe;
/**< pointer to coefficients for RE */
pu8_t dataIm;
/**< pointer to coefficients for IM */
u16_t sizeRe;
/**< size of coefficients for RE */
u16_t sizeIm;
/**< size of coefficients for IM */
} DRXFilterInfo_t, *pDRXFilterInfo_t;
/*========================================*/
......@@ -822,24 +882,32 @@ typedef struct {
* Only certain fields need to be used for a specfic standard.
*
*/
typedef struct {
DRXFrequency_t frequency; /**< frequency in kHz */
DRXBandwidth_t bandwidth; /**< bandwidth */
DRXMirror_t mirror; /**< mirrored or not on RF */
DRXConstellation_t constellation; /**< constellation */
DRXHierarchy_t hierarchy; /**< hierarchy */
DRXPriority_t priority; /**< priority */
DRXCoderate_t coderate; /**< coderate */
DRXGuard_t guard; /**< guard interval */
DRXFftmode_t fftmode; /**< fftmode */
DRXClassification_t classification; /**< classification */
DRXSymbolrate_t symbolrate; /**< symbolrate in symbols/sec */
DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */
DRXLDPC_t ldpc; /**< ldpc */
DRXCarrier_t carrier; /**< carrier */
DRXFramemode_t framemode; /**< frame mode */
DRXPilotMode_t pilot; /**< pilot mode */
} DRXChannel_t, *pDRXChannel_t;
typedef struct {
DRXFrequency_t frequency;
/**< frequency in kHz */
DRXBandwidth_t bandwidth;
/**< bandwidth */
DRXMirror_t mirror; /**< mirrored or not on RF */
DRXConstellation_t constellation;
/**< constellation */
DRXHierarchy_t hierarchy;
/**< hierarchy */
DRXPriority_t priority; /**< priority */
DRXCoderate_t coderate; /**< coderate */
DRXGuard_t guard; /**< guard interval */
DRXFftmode_t fftmode; /**< fftmode */
DRXClassification_t classification;
/**< classification */
DRXSymbolrate_t symbolrate;
/**< symbolrate in symbols/sec */
DRXInterleaveModes_t interleavemode;
/**< interleaveMode QAM */
DRXLDPC_t ldpc; /**< ldpc */
DRXCarrier_t carrier; /**< carrier */
DRXFramemode_t framemode;
/**< frame mode */
DRXPilotMode_t pilot; /**< pilot mode */
} DRXChannel_t, *pDRXChannel_t;
/*========================================*/
......@@ -849,25 +917,31 @@ typedef struct {
*
* Used by DRX_CTRL_SIG_QUALITY.
*/
typedef struct {
u16_t MER; /**< in steps of 0.1 dB */
u32_t preViterbiBER ; /**< in steps of 1/scaleFactorBER */
u32_t postViterbiBER ; /**< in steps of 1/scaleFactorBER */
u32_t scaleFactorBER; /**< scale factor for BER */
u16_t packetError ; /**< number of packet errors */
u32_t postReedSolomonBER ; /**< in steps of 1/scaleFactorBER */
u32_t preLdpcBER; /**< in steps of 1/scaleFactorBER */
u32_t averIter; /**< in steps of 0.01 */
u16_t indicator; /**< indicative signal quality low=0..100=high */
}DRXSigQuality_t, *pDRXSigQuality_t;
typedef enum {
DRX_SQI_SPEED_FAST = 0,
DRX_SQI_SPEED_MEDIUM,
DRX_SQI_SPEED_SLOW,
DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t;
typedef struct {
u16_t MER; /**< in steps of 0.1 dB */
u32_t preViterbiBER;
/**< in steps of 1/scaleFactorBER */
u32_t postViterbiBER;
/**< in steps of 1/scaleFactorBER */
u32_t scaleFactorBER;
/**< scale factor for BER */
u16_t packetError;
/**< number of packet errors */
u32_t postReedSolomonBER;
/**< in steps of 1/scaleFactorBER */
u32_t preLdpcBER;
/**< in steps of 1/scaleFactorBER */
u32_t averIter;/**< in steps of 0.01 */
u16_t indicator;
/**< indicative signal quality low=0..100=high */
} DRXSigQuality_t, *pDRXSigQuality_t;
typedef enum {
DRX_SQI_SPEED_FAST = 0,
DRX_SQI_SPEED_MEDIUM,
DRX_SQI_SPEED_SLOW,
DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t;
/*========================================*/
......@@ -877,11 +951,12 @@ typedef enum {
*
* Used by DRX_CTRL_CONSTEL.
*/
typedef struct {
s16_t im; /**< Imaginary part. */
s16_t re; /**< Real part. */
} DRXComplex_t, *pDRXComplex_t;
typedef struct {
s16_t im;
/**< Imaginary part. */
s16_t re;
/**< Real part. */
} DRXComplex_t, *pDRXComplex_t;
/*========================================*/
......@@ -891,16 +966,22 @@ typedef struct {
*
* Used by DRX_CTRL_SCAN_INIT.
*/
typedef struct {
DRXFrequency_t first; /**< First centre frequency in this band */
DRXFrequency_t last; /**< Last centre frequency in this band */
DRXFrequency_t step; /**< Stepping frequency in this band */
DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */
u16_t chNumber; /**< First channel number in this band, or first
typedef struct {
DRXFrequency_t first;
/**< First centre frequency in this band */
DRXFrequency_t last;
/**< Last centre frequency in this band */
DRXFrequency_t step;
/**< Stepping frequency in this band */
DRXBandwidth_t bandwidth;
/**< Bandwidth within this frequency band */
u16_t chNumber;
/**< First channel number in this band, or first
index in chNames */
char **chNames; /**< Optional list of channel names in this
char **chNames;
/**< Optional list of channel names in this
band */
} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t;
} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t;
/*========================================*/
......@@ -910,11 +991,11 @@ typedef struct {
*
* Used by frequency_plan.h
*/
typedef struct{
pDRXFrequencyPlan_t freqPlan;
int freqPlanSize;
char *freqPlanName;
}DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t;
typedef struct {
pDRXFrequencyPlan_t freqPlan;
int freqPlanSize;
char *freqPlanName;
} DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t;
/*========================================*/
......@@ -922,14 +1003,15 @@ typedef struct{
* /struct DRXScanDataQam_t
* QAM specific scanning variables
*/
typedef struct {
pu32_t symbolrate; /**< list of symbolrates to scan */
u16_t symbolrateSize; /**< size of symbolrate array */
pDRXConstellation_t constellation; /**< list of constellations */
u16_t constellationSize; /**< size of constellation array */
u16_t ifAgcThreshold; /**< thresholf for IF-AGC based
typedef struct {
pu32_t symbolrate; /**< list of symbolrates to scan */
u16_t symbolrateSize; /**< size of symbolrate array */
pDRXConstellation_t constellation;
/**< list of constellations */
u16_t constellationSize; /**< size of constellation array */
u16_t ifAgcThreshold; /**< thresholf for IF-AGC based
scanning filter */
} DRXScanDataQam_t, *pDRXScanDataQam_t;
} DRXScanDataQam_t, *pDRXScanDataQam_t;
/*========================================*/
......@@ -937,9 +1019,10 @@ typedef struct {
* /struct DRXScanDataAtv_t
* ATV specific scanning variables
*/
typedef struct {
s16_t svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */
} DRXScanDataAtv_t, *pDRXScanDataAtv_t;
typedef struct {
s16_t svrThreshold;
/**< threshold of Sound/Video ratio in 0.1dB steps */
} DRXScanDataAtv_t, *pDRXScanDataAtv_t;
/*========================================*/
......@@ -949,14 +1032,15 @@ typedef struct {
*
* Used by DRX_CTRL_SCAN_INIT.
*/
typedef struct {
pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/
u16_t frequencyPlanSize; /**< Number of bands */
u32_t numTries; /**< Max channels tried */
DRXFrequency_t skip; /**< Minimum frequency step to take
typedef struct {
pDRXFrequencyPlan_t frequencyPlan;
/**< Frequency plan (array)*/
u16_t frequencyPlanSize; /**< Number of bands */
u32_t numTries; /**< Max channels tried */
DRXFrequency_t skip; /**< Minimum frequency step to take
after a channel is found */
void *extParams; /**< Standard specific params */
} DRXScanParam_t, *pDRXScanParam_t;
void *extParams; /**< Standard specific params */
} DRXScanParam_t, *pDRXScanParam_t;
/*========================================*/
......@@ -964,21 +1048,21 @@ typedef struct {
* \brief Scan commands.
* Used by scanning algorithms.
*/
typedef enum {
DRX_SCAN_COMMAND_INIT = 0, /**< Initialize scanning */
DRX_SCAN_COMMAND_NEXT, /**< Next scan */
DRX_SCAN_COMMAND_STOP /**< Stop scanning */
}DRXScanCommand_t, *pDRXScanCommand_t;
typedef enum {
DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */
DRX_SCAN_COMMAND_NEXT, /**< Next scan */
DRX_SCAN_COMMAND_STOP /**< Stop scanning */
} DRXScanCommand_t, *pDRXScanCommand_t;
/*========================================*/
/**
* \brief Inner scan function prototype.
*/
typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
pBool_t getNextChannel );
typedef DRXStatus_t(*DRXScanFunc_t) (void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
pBool_t getNextChannel);
/*========================================*/
......@@ -988,17 +1072,21 @@ typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext,
*
* Used by DRX_CTRL_TPS_INFO.
*/
typedef struct {
DRXFftmode_t fftmode; /**< Fft mode */
DRXGuard_t guard; /**< Guard interval */
DRXConstellation_t constellation; /**< Constellation */
DRXHierarchy_t hierarchy; /**< Hierarchy */
DRXCoderate_t highCoderate; /**< High code rate */
DRXCoderate_t lowCoderate; /**< Low cod rate */
DRXTPSFrame_t frame; /**< Tps frame */
u8_t length; /**< Length */
u16_t cellId; /**< Cell id */
}DRXTPSInfo_t, *pDRXTPSInfo_t;
typedef struct {
DRXFftmode_t fftmode; /**< Fft mode */
DRXGuard_t guard; /**< Guard interval */
DRXConstellation_t constellation;
/**< Constellation */
DRXHierarchy_t hierarchy;
/**< Hierarchy */
DRXCoderate_t highCoderate;
/**< High code rate */
DRXCoderate_t lowCoderate;
/**< Low cod rate */
DRXTPSFrame_t frame; /**< Tps frame */
u8_t length; /**< Length */
u16_t cellId; /**< Cell id */
} DRXTPSInfo_t, *pDRXTPSInfo_t;
/*========================================*/
......@@ -1007,27 +1095,45 @@ typedef struct {
*
* Used by DRX_CTRL_SET_POWER_MODE.
*/
typedef enum {
DRX_POWER_UP = 0, /**< Generic , Power Up Mode */
DRX_POWER_MODE_1, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_2, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_3, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_4, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_5, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_6, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_7, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_8, /**< Device specific , Power Up Mode */
DRX_POWER_MODE_9, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_10, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_11, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_12, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_13, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_14, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_15, /**< Device specific , Power Down Mode */
DRX_POWER_MODE_16, /**< Device specific , Power Down Mode */
DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */
}DRXPowerMode_t, *pDRXPowerMode_t;
typedef enum {
DRX_POWER_UP = 0,
/**< Generic , Power Up Mode */
DRX_POWER_MODE_1,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_2,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_3,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_4,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_5,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_6,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_7,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_8,
/**< Device specific , Power Up Mode */
DRX_POWER_MODE_9,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_10,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_11,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_12,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_13,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_14,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_15,
/**< Device specific , Power Down Mode */
DRX_POWER_MODE_16,
/**< Device specific , Power Down Mode */
DRX_POWER_DOWN = 255
/**< Generic , Power Down Mode */
} DRXPowerMode_t, *pDRXPowerMode_t;
/*========================================*/
......@@ -1037,18 +1143,17 @@ typedef enum {
*
* Used by DRX_CTRL_VERSION.
*/
typedef enum {
DRX_MODULE_DEVICE,
DRX_MODULE_MICROCODE,
DRX_MODULE_DRIVERCORE,
DRX_MODULE_DEVICEDRIVER,
DRX_MODULE_DAP,
DRX_MODULE_BSP_I2C,
DRX_MODULE_BSP_TUNER,
DRX_MODULE_BSP_HOST,
DRX_MODULE_UNKNOWN
} DRXModule_t, *pDRXModule_t;
typedef enum {
DRX_MODULE_DEVICE,
DRX_MODULE_MICROCODE,
DRX_MODULE_DRIVERCORE,
DRX_MODULE_DEVICEDRIVER,
DRX_MODULE_DAP,
DRX_MODULE_BSP_I2C,
DRX_MODULE_BSP_TUNER,
DRX_MODULE_BSP_HOST,
DRX_MODULE_UNKNOWN
} DRXModule_t, *pDRXModule_t;
/**
* \enum DRXVersion_t
......@@ -1056,14 +1161,16 @@ typedef enum {
*
* Used by DRX_CTRL_VERSION.
*/
typedef struct {
DRXModule_t moduleType; /**< Type identifier of the module */
char *moduleName; /**< Name or description of module */
u16_t vMajor; /**< Major version number */
u16_t vMinor; /**< Minor version number */
u16_t vPatch; /**< Patch version number */
char *vString; /**< Version as text string */
} DRXVersion_t, *pDRXVersion_t;
typedef struct {
DRXModule_t moduleType;
/**< Type identifier of the module */
char *moduleName;
/**< Name or description of module */
u16_t vMajor; /**< Major version number */
u16_t vMinor; /**< Minor version number */
u16_t vPatch; /**< Patch version number */
char *vString; /**< Version as text string */
} DRXVersion_t, *pDRXVersion_t;
/**
* \enum DRXVersionList_t
......@@ -1071,10 +1178,11 @@ typedef struct {
*
* Used by DRX_CTRL_VERSION.
*/
typedef struct DRXVersionList_s {
pDRXVersion_t version; /**< Version information */
struct DRXVersionList_s *next; /**< Next list element */
} DRXVersionList_t, *pDRXVersionList_t;
typedef struct DRXVersionList_s {
pDRXVersion_t version;/**< Version information */
struct DRXVersionList_s *next;
/**< Next list element */
} DRXVersionList_t, *pDRXVersionList_t;
/*========================================*/
......@@ -1083,10 +1191,12 @@ typedef struct DRXVersionList_s {
*
* Used by DRX_CTRL_UIO_CFG.
*/
typedef struct {
DRXUIO_t uio; /**< UIO identifier */
DRXUIOMode_t mode; /**< UIO operational mode */
} DRXUIOCfg_t, *pDRXUIOCfg_t;
typedef struct {
DRXUIO_t uio;
/**< UIO identifier */
DRXUIOMode_t mode;
/**< UIO operational mode */
} DRXUIOCfg_t, *pDRXUIOCfg_t;
/*========================================*/
......@@ -1095,10 +1205,12 @@ typedef struct {
*
* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
*/
typedef struct {
DRXUIO_t uio; /**< UIO identifier */
Bool_t value; /**< UIO value (TRUE=1, FALSE=0) */
} DRXUIOData_t, *pDRXUIOData_t;
typedef struct {
DRXUIO_t uio;
/**< UIO identifier */
Bool_t value;
/**< UIO value (TRUE=1, FALSE=0) */
} DRXUIOData_t, *pDRXUIOData_t;
/*========================================*/
......@@ -1107,13 +1219,13 @@ typedef struct {
*
* Used by DRX_CTRL_SET_OOB.
*/
typedef struct {
DRXFrequency_t frequency; /**< Frequency in kHz */
DRXOOBDownstreamStandard_t standard; /**< OOB standard */
Bool_t spectrumInverted; /**< If TRUE, then spectrum
typedef struct {
DRXFrequency_t frequency; /**< Frequency in kHz */
DRXOOBDownstreamStandard_t standard;
/**< OOB standard */
Bool_t spectrumInverted; /**< If TRUE, then spectrum
is inverted */
} DRXOOB_t, *pDRXOOB_t;
} DRXOOB_t, *pDRXOOB_t;
/*========================================*/
......@@ -1122,13 +1234,12 @@ typedef struct {
*
* Used by DRX_CTRL_GET_OOB.
*/
typedef struct {
DRXFrequency_t frequency; /**< Frequency in Khz */
DRXLockStatus_t lock; /**< Lock status */
u32_t mer; /**< MER */
s32_t symbolRateOffset; /**< Symbolrate offset in ppm */
} DRXOOBStatus_t, *pDRXOOBStatus_t;
typedef struct {
DRXFrequency_t frequency; /**< Frequency in Khz */
DRXLockStatus_t lock; /**< Lock status */
u32_t mer; /**< MER */
s32_t symbolRateOffset; /**< Symbolrate offset in ppm */
} DRXOOBStatus_t, *pDRXOOBStatus_t;
/*========================================*/
......@@ -1138,10 +1249,12 @@ typedef struct {
* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
* A sort of nested DRX_Ctrl() functionality for device specific controls.
*/
typedef struct {
DRXCfgType_t cfgType ; /**< Function identifier */
void* cfgData ; /**< Function data */
} DRXCfg_t, *pDRXCfg_t;
typedef struct {
DRXCfgType_t cfgType;
/**< Function identifier */
void *cfgData;
/**< Function data */
} DRXCfg_t, *pDRXCfg_t;
/*========================================*/
......@@ -1150,11 +1263,10 @@ typedef struct {
* MStart width [nr MCLK cycles] for serial MPEG output.
*/
typedef enum {
DRX_MPEG_STR_WIDTH_1,
DRX_MPEG_STR_WIDTH_8
} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t;
typedef enum {
DRX_MPEG_STR_WIDTH_1,
DRX_MPEG_STR_WIDTH_8
} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t;
/* CTRL CFG MPEG ouput */
/**
......@@ -1165,44 +1277,45 @@ typedef enum {
* DRX_CTRL_GET_CFG.
*/
typedef struct {
Bool_t enableMPEGOutput; /**< If TRUE, enable MPEG output */
Bool_t insertRSByte; /**< If TRUE, insert RS byte */
Bool_t enableParallel; /**< If TRUE, parallel out otherwise
typedef struct {
Bool_t enableMPEGOutput;/**< If TRUE, enable MPEG output */
Bool_t insertRSByte; /**< If TRUE, insert RS byte */
Bool_t enableParallel; /**< If TRUE, parallel out otherwise
serial */
Bool_t invertDATA; /**< If TRUE, invert DATA signals */
Bool_t invertERR; /**< If TRUE, invert ERR signal */
Bool_t invertSTR; /**< If TRUE, invert STR signals */
Bool_t invertVAL; /**< If TRUE, invert VAL signals */
Bool_t invertCLK; /**< If TRUE, invert CLK signals */
Bool_t staticCLK; /**< If TRUE, static MPEG clockrate
Bool_t invertDATA; /**< If TRUE, invert DATA signals */
Bool_t invertERR; /**< If TRUE, invert ERR signal */
Bool_t invertSTR; /**< If TRUE, invert STR signals */
Bool_t invertVAL; /**< If TRUE, invert VAL signals */
Bool_t invertCLK; /**< If TRUE, invert CLK signals */
Bool_t staticCLK; /**< If TRUE, static MPEG clockrate
will be used, otherwise clockrate
will adapt to the bitrate of the
TS */
u32_t bitrate; /**< Maximum bitrate in b/s in case
u32_t bitrate; /**< Maximum bitrate in b/s in case
static clockrate is selected */
DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */
} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t;
DRXMPEGStrWidth_t widthSTR;
/**< MPEG start width */
} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t;
/* CTRL CFG SMA */
/**
* /struct DRXCfgSMAIO_t
* smart antenna i/o.
*/
typedef enum DRXCfgSMAIO_t {
DRX_SMA_OUTPUT = 0,
DRX_SMA_INPUT
} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t;
typedef enum DRXCfgSMAIO_t {
DRX_SMA_OUTPUT = 0,
DRX_SMA_INPUT
} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t;
/**
* /struct DRXCfgSMA_t
* Set smart antenna.
*/
typedef struct {
DRXCfgSMAIO_t io;
u16_t ctrlData;
Bool_t smartAntInverted;
} DRXCfgSMA_t, *pDRXCfgSMA_t;
typedef struct {
DRXCfgSMAIO_t io;
u16_t ctrlData;
Bool_t smartAntInverted;
} DRXCfgSMA_t, *pDRXCfgSMA_t;
/*========================================*/
......@@ -1214,15 +1327,17 @@ typedef struct {
* If portNr is equal to primairy portNr BSPI2C will be used.
*
*/
typedef struct {
u16_t portNr; /**< I2C port number */
pI2CDeviceAddr_t wDevAddr; /**< Write device address */
u16_t wCount; /**< Size of write data in bytes */
pu8_t wData; /**< Pointer to write data */
pI2CDeviceAddr_t rDevAddr; /**< Read device address */
u16_t rCount; /**< Size of data to read in bytes */
pu8_t rData; /**< Pointer to read buffer */
} DRXI2CData_t, *pDRXI2CData_t;
typedef struct {
u16_t portNr; /**< I2C port number */
pI2CDeviceAddr_t wDevAddr;
/**< Write device address */
u16_t wCount; /**< Size of write data in bytes */
pu8_t wData; /**< Pointer to write data */
pI2CDeviceAddr_t rDevAddr;
/**< Read device address */
u16_t rCount; /**< Size of data to read in bytes */
pu8_t rData; /**< Pointer to read buffer */
} DRXI2CData_t, *pDRXI2CData_t;
/*========================================*/
......@@ -1232,50 +1347,59 @@ typedef struct {
*
* Used by DRX_CTRL_SET_AUD.
*/
typedef enum {
DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
DRX_AUD_STANDARD_FM_STEREO, /**< set to FM-Stereo Radio */
DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
DRX_AUD_STANDARD_BG_NICAM_FM, /**< set BG_NICAM_FM standard */
DRX_AUD_STANDARD_L_NICAM_AM, /**< set L_NICAM_AM standard */
DRX_AUD_STANDARD_I_NICAM_FM, /**< set I_NICAM_FM standard */
DRX_AUD_STANDARD_D_K_NICAM_FM, /**< set D_K_NICAM_FM standard */
DRX_AUD_STANDARD_NOT_READY, /**< used to detect audio standard */
DRX_AUD_STANDARD_AUTO = DRX_AUTO, /**< Automatic Standard Detection */
DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */
} DRXAudStandard_t, *pDRXAudStandard_t;
typedef enum {
DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */
DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
DRX_AUD_STANDARD_BG_NICAM_FM,
/**< set BG_NICAM_FM standard */
DRX_AUD_STANDARD_L_NICAM_AM,
/**< set L_NICAM_AM standard */
DRX_AUD_STANDARD_I_NICAM_FM,
/**< set I_NICAM_FM standard */
DRX_AUD_STANDARD_D_K_NICAM_FM,
/**< set D_K_NICAM_FM standard */
DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */
DRX_AUD_STANDARD_AUTO = DRX_AUTO,
/**< Automatic Standard Detection */
DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
/**< used as auto and for readback */
} DRXAudStandard_t, *pDRXAudStandard_t;
/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */
/**
* \enum DRXAudNICAMStatus_t
* \brief Status of NICAM carrier.
*/
typedef enum {
DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */
DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */
DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t;
typedef enum {
DRX_AUD_NICAM_DETECTED = 0,
/**< NICAM carrier detected */
DRX_AUD_NICAM_NOT_DETECTED,
/**< NICAM carrier not detected */
DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t;
/**
* \struct DRXAudStatus_t
* \brief Audio status characteristics.
*/
typedef struct {
Bool_t stereo; /**< stereo detection */
Bool_t carrierA; /**< carrier A detected */
Bool_t carrierB; /**< carrier B detected */
Bool_t sap; /**< sap / bilingual detection */
Bool_t rds; /**< RDS data array present */
DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */
s8_t fmIdent; /**< FM Identification value */
} DRXAudStatus_t, *pDRXAudStatus_t;
typedef struct {
Bool_t stereo; /**< stereo detection */
Bool_t carrierA; /**< carrier A detected */
Bool_t carrierB; /**< carrier B detected */
Bool_t sap; /**< sap / bilingual detection */
Bool_t rds; /**< RDS data array present */
DRXAudNICAMStatus_t nicamStatus;
/**< status of NICAM carrier */
s8_t fmIdent; /**< FM Identification value */
} DRXAudStatus_t, *pDRXAudStatus_t;
/* CTRL_AUD_READ_RDS - DRXRDSdata_t */
......@@ -1283,110 +1407,114 @@ typedef struct {
* \struct DRXRDSdata_t
* \brief Raw RDS data array.
*/
typedef struct {
Bool_t valid; /**< RDS data validation */
u16_t data[18]; /**< data from one RDS data array */
} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t;
typedef struct {
Bool_t valid; /**< RDS data validation */
u16_t data[18]; /**< data from one RDS data array */
} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t;
/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */
/**
* \enum DRXAudAVCDecayTime_t
* \brief Automatic volume control configuration.
*/
typedef enum {
DRX_AUD_AVC_OFF, /**< Automatic volume control off */
DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
DRX_AUD_AVC_DECAYTIME_20MS /**< level volume in 20 millisec */
} DRXAudAVCMode_t, *pDRXAudAVCMode_t;
typedef enum {
DRX_AUD_AVC_OFF, /**< Automatic volume control off */
DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */
} DRXAudAVCMode_t, *pDRXAudAVCMode_t;
/**
* /enum DRXAudMaxAVCGain_t
* /brief Automatic volume control max gain in audio baseband.
*/
typedef enum {
DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t;
typedef enum {
DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t;
/**
* /enum DRXAudMaxAVCAtten_t
* /brief Automatic volume control max attenuation in audio baseband.
*/
typedef enum {
DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */
DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */
DRX_AUD_AVC_MAX_ATTEN_24DB /**< maximum AVC attenuation 24 dB */
} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t;
typedef enum {
DRX_AUD_AVC_MAX_ATTEN_12DB,
/**< maximum AVC attenuation 12 dB */
DRX_AUD_AVC_MAX_ATTEN_18DB,
/**< maximum AVC attenuation 18 dB */
DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */
} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t;
/**
* \struct DRXCfgAudVolume_t
* \brief Audio volume configuration.
*/
typedef struct {
Bool_t mute; /**< mute overrides volume setting */
s16_t volume; /**< volume, range -114 to 12 dB */
DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */
u16_t avcRefLevel; /**< AVC reference level */
DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */
DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */
s16_t strengthLeft; /**< quasi-peak, left speaker */
s16_t strengthRight; /**< quasi-peak, right speaker */
} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t;
typedef struct {
Bool_t mute; /**< mute overrides volume setting */
s16_t volume; /**< volume, range -114 to 12 dB */
DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */
u16_t avcRefLevel; /**< AVC reference level */
DRXAudAVCMaxGain_t avcMaxGain;
/**< AVC max gain selection */
DRXAudAVCMaxAtten_t avcMaxAtten;
/**< AVC max attenuation selection */
s16_t strengthLeft; /**< quasi-peak, left speaker */
s16_t strengthRight; /**< quasi-peak, right speaker */
} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t;
/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */
/**
* \enum DRXI2SMode_t
* \brief I2S output mode.
*/
typedef enum {
DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
} DRXI2SMode_t, *pDRXI2SMode_t;
typedef enum {
DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
} DRXI2SMode_t, *pDRXI2SMode_t;
/**
* \enum DRXI2SWordLength_t
* \brief Width of I2S data.
*/
typedef enum {
DRX_I2S_WORDLENGTH_32 = 0, /**< I2S data is 32 bit wide */
DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
} DRXI2SWordLength_t, *pDRXI2SWordLength_t;
typedef enum {
DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */
DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
} DRXI2SWordLength_t, *pDRXI2SWordLength_t;
/**
* \enum DRXI2SFormat_t
* \brief Data wordstrobe alignment for I2S.
*/
typedef enum {
DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */
DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */
} DRXI2SFormat_t, *pDRXI2SFormat_t;
typedef enum {
DRX_I2S_FORMAT_WS_WITH_DATA,
/**< I2S data and wordstrobe are aligned */
DRX_I2S_FORMAT_WS_ADVANCED
/**< I2S data one cycle after wordstrobe */
} DRXI2SFormat_t, *pDRXI2SFormat_t;
/**
* \enum DRXI2SPolarity_t
* \brief Polarity of I2S data.
*/
typedef enum {
DRX_I2S_POLARITY_RIGHT, /**< wordstrobe - right high, left low */
DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
} DRXI2SPolarity_t, *pDRXI2SPolarity_t;
typedef enum {
DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */
DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
} DRXI2SPolarity_t, *pDRXI2SPolarity_t;
/**
* \struct DRXCfgI2SOutput_t
* \brief I2S output configuration.
*/
typedef struct {
Bool_t outputEnable; /**< I2S output enable */
u32_t frequency; /**< range from 8000-48000 Hz */
DRXI2SMode_t mode; /**< I2S mode, master or slave */
DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */
DRXI2SPolarity_t polarity; /**< I2S wordstrobe polarity */
DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */
} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t;
typedef struct {
Bool_t outputEnable; /**< I2S output enable */
u32_t frequency; /**< range from 8000-48000 Hz */
DRXI2SMode_t mode; /**< I2S mode, master or slave */
DRXI2SWordLength_t wordLength;
/**< I2S wordlength, 16 or 32 bits */
DRXI2SPolarity_t polarity;/**< I2S wordstrobe polarity */
DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */
} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t;
/* ------------------------------expert interface-----------------------------*/
/**
......@@ -1394,119 +1522,119 @@ typedef struct {
* setting for FM-Deemphasis in audio demodulator.
*
*/
typedef enum {
DRX_AUD_FM_DEEMPH_50US,
DRX_AUD_FM_DEEMPH_75US,
DRX_AUD_FM_DEEMPH_OFF
} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t;
typedef enum {
DRX_AUD_FM_DEEMPH_50US,
DRX_AUD_FM_DEEMPH_75US,
DRX_AUD_FM_DEEMPH_OFF
} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t;
/**
* /enum DRXAudDeviation_t
* setting for deviation mode in audio demodulator.
*
*/
typedef enum {
DRX_AUD_DEVIATION_NORMAL,
DRX_AUD_DEVIATION_HIGH
} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t;
typedef enum {
DRX_AUD_DEVIATION_NORMAL,
DRX_AUD_DEVIATION_HIGH
} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t;
/**
* /enum DRXNoCarrierOption_t
* setting for carrier, mute/noise.
*
*/
typedef enum {
DRX_NO_CARRIER_MUTE,
DRX_NO_CARRIER_NOISE
} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t;
typedef enum {
DRX_NO_CARRIER_MUTE,
DRX_NO_CARRIER_NOISE
} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t;
/**
* \enum DRXAudAutoSound_t
* \brief Automatic Sound
*/
typedef enum {
DRX_AUD_AUTO_SOUND_OFF = 0,
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t;
typedef enum {
DRX_AUD_AUTO_SOUND_OFF = 0,
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t;
/**
* \enum DRXAudASSThres_t
* \brief Automatic Sound Select Thresholds
*/
typedef struct {
u16_t a2; /* A2 Threshold for ASS configuration */
u16_t btsc; /* BTSC Threshold for ASS configuration */
u16_t nicam; /* Nicam Threshold for ASS configuration */
} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t;
typedef struct {
u16_t a2; /* A2 Threshold for ASS configuration */
u16_t btsc; /* BTSC Threshold for ASS configuration */
u16_t nicam; /* Nicam Threshold for ASS configuration */
} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t;
/**
* \struct DRXAudCarrier_t
* \brief Carrier detection related parameters
*/
typedef struct {
u16_t thres; /* carrier detetcion threshold for primary carrier (A) */
DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */
DRXFrequency_t shift; /* DC level of incoming signal (A) */
DRXFrequency_t dco; /* frequency adjustment (A) */
} DRXAudCarrier_t, *pDRXCfgAudCarrier_t;
typedef struct {
u16_t thres; /* carrier detetcion threshold for primary carrier (A) */
DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */
DRXFrequency_t shift; /* DC level of incoming signal (A) */
DRXFrequency_t dco; /* frequency adjustment (A) */
} DRXAudCarrier_t, *pDRXCfgAudCarrier_t;
/**
* \struct DRXCfgAudCarriers_t
* \brief combining carrier A & B to one struct
*/
typedef struct {
DRXAudCarrier_t a;
DRXAudCarrier_t b;
} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t;
typedef struct {
DRXAudCarrier_t a;
DRXAudCarrier_t b;
} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t;
/**
* /enum DRXAudI2SSrc_t
* Selection of audio source
*/
typedef enum {
DRX_AUD_SRC_MONO,
DRX_AUD_SRC_STEREO_OR_AB,
DRX_AUD_SRC_STEREO_OR_A,
DRX_AUD_SRC_STEREO_OR_B
} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t;
typedef enum {
DRX_AUD_SRC_MONO,
DRX_AUD_SRC_STEREO_OR_AB,
DRX_AUD_SRC_STEREO_OR_A,
DRX_AUD_SRC_STEREO_OR_B
} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t;
/**
* \enum DRXAudI2SMatrix_t
* \brief Used for selecting I2S output.
*/
typedef enum {
DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */
DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */
DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */
DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t;
typedef enum {
DRX_AUD_I2S_MATRIX_A_MONO,
/**< A sound only, stereo or mono */
DRX_AUD_I2S_MATRIX_B_MONO,
/**< B sound only, stereo or mono */
DRX_AUD_I2S_MATRIX_STEREO,
/**< A+B sound, transparant */
DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t;
/**
* /enum DRXAudFMMatrix_t
* setting for FM-Matrix in audio demodulator.
*
*/
typedef enum {
DRX_AUD_FM_MATRIX_NO_MATRIX,
DRX_AUD_FM_MATRIX_GERMAN,
DRX_AUD_FM_MATRIX_KOREAN,
DRX_AUD_FM_MATRIX_SOUND_A,
DRX_AUD_FM_MATRIX_SOUND_B
} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t;
typedef enum {
DRX_AUD_FM_MATRIX_NO_MATRIX,
DRX_AUD_FM_MATRIX_GERMAN,
DRX_AUD_FM_MATRIX_KOREAN,
DRX_AUD_FM_MATRIX_SOUND_A,
DRX_AUD_FM_MATRIX_SOUND_B
} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t;
/**
* \struct DRXAudMatrices_t
* \brief Mixer settings
*/
typedef struct {
DRXAudI2SSrc_t sourceI2S;
DRXAudI2SMatrix_t matrixI2S;
DRXAudFMMatrix_t matrixFm;
} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t;
typedef struct {
DRXAudI2SSrc_t sourceI2S;
DRXAudI2SMatrix_t matrixI2S;
DRXAudFMMatrix_t matrixFm;
} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t;
/**
* \enum DRXI2SVidSync_t
......@@ -1514,77 +1642,76 @@ typedef struct {
* AUTO_1 and AUTO_2 are for automatic video standard detection with preference
* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
*/
typedef enum {
DRX_AUD_AVSYNC_OFF, /**< audio/video synchronization is off */
DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */
DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */
DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */
} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t;
typedef enum {
DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */
DRX_AUD_AVSYNC_NTSC,
/**< it is an NTSC system */
DRX_AUD_AVSYNC_MONOCHROME,
/**< it is a MONOCHROME system */
DRX_AUD_AVSYNC_PAL_SECAM
/**< it is a PAL/SECAM system */
} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t;
/**
* \struct DRXCfgAudPrescale_t
* \brief Prescalers
*/
typedef struct {
u16_t fmDeviation;
s16_t nicamGain;
} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t;
typedef struct {
u16_t fmDeviation;
s16_t nicamGain;
} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t;
/**
* \struct DRXAudBeep_t
* \brief Beep
*/
typedef struct {
s16_t volume; /* dB */
u16_t frequency; /* Hz */
Bool_t mute;
} DRXAudBeep_t, *pDRXAudBeep_t;
typedef struct {
s16_t volume; /* dB */
u16_t frequency; /* Hz */
Bool_t mute;
} DRXAudBeep_t, *pDRXAudBeep_t;
/**
* \enum DRXAudBtscDetect_t
* \brief BTSC detetcion mode
*/
typedef enum {
DRX_BTSC_STEREO,
DRX_BTSC_MONO_AND_SAP
} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t;
typedef enum {
DRX_BTSC_STEREO,
DRX_BTSC_MONO_AND_SAP
} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t;
/**
* \struct DRXAudData_t
* \brief Audio data structure
*/
typedef struct
{
/* audio storage */
Bool_t audioIsActive;
DRXAudStandard_t audioStandard;
DRXCfgI2SOutput_t i2sdata;
DRXCfgAudVolume_t volume;
DRXCfgAudAutoSound_t autoSound;
DRXCfgAudASSThres_t assThresholds;
DRXCfgAudCarriers_t carriers;
DRXCfgAudMixer_t mixer;
DRXCfgAudDeviation_t deviation;
DRXCfgAudAVSync_t avSync;
DRXCfgAudPrescale_t prescale;
DRXAudFMDeemphasis_t deemph;
DRXAudBtscDetect_t btscDetect;
/* rds */
u16_t rdsDataCounter;
Bool_t rdsDataPresent;
} DRXAudData_t, *pDRXAudData_t;
typedef struct {
/* audio storage */
Bool_t audioIsActive;
DRXAudStandard_t audioStandard;
DRXCfgI2SOutput_t i2sdata;
DRXCfgAudVolume_t volume;
DRXCfgAudAutoSound_t autoSound;
DRXCfgAudASSThres_t assThresholds;
DRXCfgAudCarriers_t carriers;
DRXCfgAudMixer_t mixer;
DRXCfgAudDeviation_t deviation;
DRXCfgAudAVSync_t avSync;
DRXCfgAudPrescale_t prescale;
DRXAudFMDeemphasis_t deemph;
DRXAudBtscDetect_t btscDetect;
/* rds */
u16_t rdsDataCounter;
Bool_t rdsDataPresent;
} DRXAudData_t, *pDRXAudData_t;
/**
* \enum DRXQamLockRange_t
* \brief QAM lock range mode
*/
typedef enum
{
DRX_QAM_LOCKRANGE_NORMAL,
DRX_QAM_LOCKRANGE_EXTENDED
}DRXQamLockRange_t, *pDRXQamLockRange_t;
typedef enum {
DRX_QAM_LOCKRANGE_NORMAL,
DRX_QAM_LOCKRANGE_EXTENDED
} DRXQamLockRange_t, *pDRXQamLockRange_t;
/*============================================================================*/
/*============================================================================*/
......@@ -1593,119 +1720,108 @@ typedef enum
/*============================================================================*/
/* Address on device */
typedef u32_t DRXaddr_t, *pDRXaddr_t;
typedef u32_t DRXaddr_t, *pDRXaddr_t;
/* Protocol specific flags */
typedef u32_t DRXflags_t, *pDRXflags_t;
typedef u32_t DRXflags_t, *pDRXflags_t;
/* Write block of data to device */
typedef DRXStatus_t (*DRXWriteBlockFunc_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data in bytes */
pu8_t data, /* data to send */
DRXflags_t flags);
typedef DRXStatus_t(*DRXWriteBlockFunc_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data in bytes */
pu8_t data, /* data to send */
DRXflags_t flags);
/* Read block of data from device */
typedef DRXStatus_t (*DRXReadBlockFunc_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data in bytes */
pu8_t data, /* receive buffer */
DRXflags_t flags);
typedef DRXStatus_t(*DRXReadBlockFunc_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data in bytes */
pu8_t data, /* receive buffer */
DRXflags_t flags);
/* Write 8-bits value to device */
typedef DRXStatus_t (*DRXWriteReg8Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u8_t data, /* data to send */
DRXflags_t flags);
typedef DRXStatus_t(*DRXWriteReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u8_t data, /* data to send */
DRXflags_t flags);
/* Read 8-bits value to device */
typedef DRXStatus_t (*DRXReadReg8Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
pu8_t data, /* receive buffer */
DRXflags_t flags);
typedef DRXStatus_t(*DRXReadReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
pu8_t data, /* receive buffer */
DRXflags_t flags);
/* Read modify write 8-bits value to device */
typedef DRXStatus_t (*DRXReadModifyWriteReg8Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
u8_t wdata, /* data to write */
pu8_t rdata); /* data to read */
typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
u8_t wdata, /* data to write */
pu8_t rdata); /* data to read */
/* Write 16-bits value to device */
typedef DRXStatus_t (*DRXWriteReg16Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t data, /* data to send */
DRXflags_t flags);
typedef DRXStatus_t(*DRXWriteReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t data, /* data to send */
DRXflags_t flags);
/* Read 16-bits value to device */
typedef DRXStatus_t (*DRXReadReg16Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
pu16_t data, /* receive buffer */
DRXflags_t flags);
typedef DRXStatus_t(*DRXReadReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
pu16_t data, /* receive buffer */
DRXflags_t flags);
/* Read modify write 16-bits value to device */
typedef DRXStatus_t (*DRXReadModifyWriteReg16Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
u16_t wdata, /* data to write */
pu16_t rdata); /* data to read */
typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
u16_t wdata, /* data to write */
pu16_t rdata); /* data to read */
/* Write 32-bits value to device */
typedef DRXStatus_t (*DRXWriteReg32Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u32_t data, /* data to send */
DRXflags_t flags);
typedef DRXStatus_t(*DRXWriteReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u32_t data, /* data to send */
DRXflags_t flags);
/* Read 32-bits value to device */
typedef DRXStatus_t (*DRXReadReg32Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
pu32_t data, /* receive buffer */
DRXflags_t flags);
typedef DRXStatus_t(*DRXReadReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
pu32_t data, /* receive buffer */
DRXflags_t flags);
/* Read modify write 32-bits value to device */
typedef DRXStatus_t (*DRXReadModifyWriteReg32Func_t) (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
u32_t wdata, /* data to write */
pu32_t rdata); /* data to read */
typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
u32_t wdata, /* data to write */
pu32_t rdata); /* data to read */
/**
* \struct DRXAccessFunc_t
* \brief Interface to an access protocol.
*/
typedef struct {
pDRXVersion_t protocolVersion;
DRXWriteBlockFunc_t writeBlockFunc;
DRXReadBlockFunc_t readBlockFunc;
DRXWriteReg8Func_t writeReg8Func;
DRXReadReg8Func_t readReg8Func;
DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func;
DRXWriteReg16Func_t writeReg16Func;
DRXReadReg16Func_t readReg16Func;
DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func;
DRXWriteReg32Func_t writeReg32Func;
DRXReadReg32Func_t readReg32Func;
DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func;
} DRXAccessFunc_t, *pDRXAccessFunc_t;
typedef struct {
pDRXVersion_t protocolVersion;
DRXWriteBlockFunc_t writeBlockFunc;
DRXReadBlockFunc_t readBlockFunc;
DRXWriteReg8Func_t writeReg8Func;
DRXReadReg8Func_t readReg8Func;
DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func;
DRXWriteReg16Func_t writeReg16Func;
DRXReadReg16Func_t readReg16Func;
DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func;
DRXWriteReg32Func_t writeReg32Func;
DRXReadReg32Func_t readReg32Func;
DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func;
} DRXAccessFunc_t, *pDRXAccessFunc_t;
/* Register address and data for register dump function */
typedef struct {
typedef struct {
DRXaddr_t address;
u32_t data;
DRXaddr_t address;
u32_t data;
} DRXRegDump_t, *pDRXRegDump_t ;
} DRXRegDump_t, *pDRXRegDump_t;
/*============================================================================*/
/*============================================================================*/
......@@ -1717,103 +1833,128 @@ typedef struct {
* \struct DRXCommonAttr_t
* \brief Set of common attributes, shared by all DRX devices.
*/
typedef struct {
/* Microcode (firmware) attributes */
pu8_t microcode; /**< Pointer to microcode image. */
u16_t microcodeSize; /**< Size of microcode image in bytes. */
Bool_t verifyMicrocode; /**< Use microcode verify or not. */
DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */
/* Clocks and tuner attributes */
DRXFrequency_t intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/
DRXFrequency_t sysClockFreq; /**< Systemclock frequency. (kHz) */
DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */
s16_t oscClockDeviation; /**< Oscillator clock deviation. (ppm) */
Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/
/* Initial MPEG output attributes */
DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */
Bool_t isOpened; /**< if TRUE instance is already opened. */
/* Channel scan */
pDRXScanParam_t scanParam; /**< scan parameters */
u16_t scanFreqPlanIndex; /**< next index in freq plan */
DRXFrequency_t scanNextFrequency; /**< next freq to scan */
Bool_t scanReady; /**< scan ready flag */
u32_t scanMaxChannels; /**< number of channels in freqplan */
u32_t scanChannelsScanned; /**< number of channels scanned */
/* Channel scan - inner loop: demod related */
DRXScanFunc_t scanFunction; /**< function to check channel */
/* Channel scan - inner loop: SYSObj related */
void* scanContext; /**< Context Pointer of SYSObj */
/* Channel scan - parameters for default DTV scan function in core driver */
u16_t scanDemodLockTimeout; /**< millisecs to wait for lock */
DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */
/* scanActive can be used by SetChannel to decide how to program the tuner,
fast or slow (but stable). Usually fast during scan. */
Bool_t scanActive; /**< TRUE when scan routines are active */
/* Power management */
DRXPowerMode_t currentPowerMode; /**< current power management mode */
/* Tuner */
u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */
DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */
DRXFrequency_t tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */
Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */
Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */
Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */
DRXChannel_t currentChannel; /**< current channel parameters */
DRXStandard_t currentStandard; /**< current standard selection */
DRXStandard_t prevStandard; /**< previous standard selection */
DRXStandard_t diCacheStandard; /**< standard in DI cache if available */
Bool_t useBootloader; /**< use bootloader in open */
u32_t capabilities; /**< capabilities flags */
u32_t productId; /**< product ID inc. metal fix number */
} DRXCommonAttr_t, *pDRXCommonAttr_t;
typedef struct {
/* Microcode (firmware) attributes */
pu8_t microcode; /**< Pointer to microcode image. */
u16_t microcodeSize;
/**< Size of microcode image in bytes. */
Bool_t verifyMicrocode;
/**< Use microcode verify or not. */
DRXMcVersionRec_t mcversion;
/**< Version record of microcode from file */
/* Clocks and tuner attributes */
DRXFrequency_t intermediateFreq;
/**< IF,if tuner instance not used. (kHz)*/
DRXFrequency_t sysClockFreq;
/**< Systemclock frequency. (kHz) */
DRXFrequency_t oscClockFreq;
/**< Oscillator clock frequency. (kHz) */
s16_t oscClockDeviation;
/**< Oscillator clock deviation. (ppm) */
Bool_t mirrorFreqSpect;
/**< Mirror IF frequency spectrum or not.*/
/* Initial MPEG output attributes */
DRXCfgMPEGOutput_t mpegCfg;
/**< MPEG configuration */
Bool_t isOpened; /**< if TRUE instance is already opened. */
/* Channel scan */
pDRXScanParam_t scanParam;
/**< scan parameters */
u16_t scanFreqPlanIndex;
/**< next index in freq plan */
DRXFrequency_t scanNextFrequency;
/**< next freq to scan */
Bool_t scanReady; /**< scan ready flag */
u32_t scanMaxChannels;/**< number of channels in freqplan */
u32_t scanChannelsScanned;
/**< number of channels scanned */
/* Channel scan - inner loop: demod related */
DRXScanFunc_t scanFunction;
/**< function to check channel */
/* Channel scan - inner loop: SYSObj related */
void *scanContext; /**< Context Pointer of SYSObj */
/* Channel scan - parameters for default DTV scan function in core driver */
u16_t scanDemodLockTimeout;
/**< millisecs to wait for lock */
DRXLockStatus_t scanDesiredLock;
/**< lock requirement for channel found */
/* scanActive can be used by SetChannel to decide how to program the tuner,
fast or slow (but stable). Usually fast during scan. */
Bool_t scanActive; /**< TRUE when scan routines are active */
/* Power management */
DRXPowerMode_t currentPowerMode;
/**< current power management mode */
/* Tuner */
u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */
DRXFrequency_t tunerMinFreqRF;
/**< minimum RF input frequency, in kHz */
DRXFrequency_t tunerMaxFreqRF;
/**< maximum RF input frequency, in kHz */
Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */
Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */
Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */
DRXChannel_t currentChannel;
/**< current channel parameters */
DRXStandard_t currentStandard;
/**< current standard selection */
DRXStandard_t prevStandard;
/**< previous standard selection */
DRXStandard_t diCacheStandard;
/**< standard in DI cache if available */
Bool_t useBootloader; /**< use bootloader in open */
u32_t capabilities; /**< capabilities flags */
u32_t productId; /**< product ID inc. metal fix number */
} DRXCommonAttr_t, *pDRXCommonAttr_t;
/*
* Generic functions for DRX devices.
*/
typedef struct DRXDemodInstance_s *pDRXDemodInstance_t;
typedef struct DRXDemodInstance_s *pDRXDemodInstance_t;
typedef DRXStatus_t (*DRXOpenFunc_t) (pDRXDemodInstance_t demod);
typedef DRXStatus_t (*DRXCloseFunc_t) (pDRXDemodInstance_t demod);
typedef DRXStatus_t (*DRXCtrlFunc_t) (pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl,
void *ctrlData);
typedef DRXStatus_t(*DRXOpenFunc_t) (pDRXDemodInstance_t demod);
typedef DRXStatus_t(*DRXCloseFunc_t) (pDRXDemodInstance_t demod);
typedef DRXStatus_t(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl,
void *ctrlData);
/**
* \struct DRXDemodFunc_t
* \brief A stucture containing all functions of a demodulator.
*/
typedef struct {
u32_t typeId; /**< Device type identifier. */
DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */
DRXCloseFunc_t closeFunc; /**< Pointer to Close() function. */
DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */
} DRXDemodFunc_t, *pDRXDemodFunc_t;
typedef struct {
u32_t typeId; /**< Device type identifier. */
DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */
DRXCloseFunc_t closeFunc;/**< Pointer to Close() function. */
DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */
} DRXDemodFunc_t, *pDRXDemodFunc_t;
/**
* \struct DRXDemodInstance_t
* \brief Top structure of demodulator instance.
*/
typedef struct DRXDemodInstance_s {
/* type specific demodulator data */
pDRXDemodFunc_t myDemodFunct; /**< demodulator functions */
pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */
pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */
pI2CDeviceAddr_t myI2CDevAddr; /**< i2c address and device identifier */
pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */
void* myExtAttr; /**< device specific attributes */
/* generic demodulator data */
} DRXDemodInstance_t;
typedef struct DRXDemodInstance_s {
/* type specific demodulator data */
pDRXDemodFunc_t myDemodFunct;
/**< demodulator functions */
pDRXAccessFunc_t myAccessFunct;
/**< data access protocol functions */
pTUNERInstance_t myTuner;
/**< tuner instance,if NULL then baseband */
pI2CDeviceAddr_t myI2CDevAddr;
/**< i2c address and device identifier */
pDRXCommonAttr_t myCommonAttr;
/**< common DRX attributes */
void *myExtAttr; /**< device specific attributes */
/* generic demodulator data */
} DRXDemodInstance_t;
/*-------------------------------------------------------------------------
MACROS
......@@ -2097,7 +2238,6 @@ Conversion from enum values to human readable form.
Access macros
-------------------------------------------------------------------------*/
/**
* \brief Create a compilable reference to the microcode attribute
* \param d pointer to demod instance
......@@ -2494,7 +2634,6 @@ Access macros
} \
} while ( 0 )
/* Configuration functions for usage by Access (XS) Macros */
#ifndef DRX_XS_CFG_BASE
......@@ -2522,7 +2661,6 @@ Access macros
#define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \
DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN )
/**
* \brief Macro to check if std is an ATV standard
* \retval TRUE std is an ATV standard
......@@ -2560,24 +2698,20 @@ Access macros
*/
#define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT )
/*-------------------------------------------------------------------------
Exported FUNCTIONS
-------------------------------------------------------------------------*/
DRXStatus_t DRX_Init( pDRXDemodInstance_t demods[] );
DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]);
DRXStatus_t DRX_Term( void );
DRXStatus_t DRX_Term(void);
DRXStatus_t DRX_Open(pDRXDemodInstance_t demod);
DRXStatus_t DRX_Open(pDRXDemodInstance_t demod);
DRXStatus_t DRX_Close(pDRXDemodInstance_t demod);
DRXStatus_t DRX_Close(pDRXDemodInstance_t demod);
DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl,
void *ctrlData);
DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl, void *ctrlData);
/*-------------------------------------------------------------------------
THE END
......@@ -2585,4 +2719,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXDRIVER_H__ */
#endif /* __DRXDRIVER_H__ */
drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h
View file @ 443f18d0
......@@ -53,10 +53,9 @@ extern "C" {
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */
extern RegisterTable_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */
/*
*==============================================================================
......@@ -73,9 +72,7 @@ extern RegisterTableInfo_t drx_driver_version_info[];
#ifdef __cplusplus
}
#endif
#endif /* __DRX_DRIVER_VERSION__H__ */
#endif /* __DRX_DRIVER_VERSION__H__ */
/*
* End of file (drx_driver_version.h)
*******************************************************************************
......
drivers/media/dvb-frontends/drx39xyj/drxj.c
View file @ 443f18d0
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/media/dvb-frontends/drx39xyj/drxj.h
View file @ 443f18d0
......@@ -55,8 +55,8 @@ extern "C" {
cannot be done with short addr only in multi master mode. */
#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0))
#error "Multi master mode and short addressing only is an illegal combination"
*; /* Generate a fatal compiler error to make sure it stops here,
this is necesarry because not all compilers stop after a #error. */
*; /* Generate a fatal compiler error to make sure it stops here,
this is necesarry because not all compilers stop after a #error. */
#endif
/*-------------------------------------------------------------------------
......@@ -74,14 +74,18 @@ TYPEDEFS
/*============================================================================*/
/*============================================================================*/
typedef struct {
u16_t command; /**< Command number */
u16_t parameterLen; /**< Data length in byte */
u16_t resultLen; /**< result length in byte */
u16_t *parameter; /**< General purpous param */
u16_t *result; /**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
typedef struct {
u16_t command;
/**< Command number */
u16_t parameterLen;
/**< Data length in byte */
u16_t resultLen;
/**< result length in byte */
u16_t *parameter;
/**< General purpous param */
u16_t *result;
/**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
/*============================================================================*/
/*============================================================================*/
......@@ -93,8 +97,8 @@ typedef struct {
#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
/* OOB lock states */
#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
/* Intermediate powermodes for DRXJ */
#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
......@@ -107,62 +111,61 @@ typedef struct {
/*#define DRX_CTRL_BASE (0x0000)*/
#define DRXJ_CTRL_CFG_BASE (0x1000)
typedef enum {
DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
DRXJ_CFG_AGC_IF,
DRXJ_CFG_AGC_INTERNAL,
DRXJ_CFG_PRE_SAW,
DRXJ_CFG_AFE_GAIN,
DRXJ_CFG_SYMBOL_CLK_OFFSET,
DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
DRXJ_CFG_FEC_MERS_SEQ_COUNT,
DRXJ_CFG_OOB_MISC,
DRXJ_CFG_SMART_ANT,
DRXJ_CFG_OOB_PRE_SAW,
DRXJ_CFG_VSB_MISC,
DRXJ_CFG_RESET_PACKET_ERR,
/* ATV (FM) */
DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
DRXJ_CFG_ATV_MISC,
DRXJ_CFG_ATV_EQU_COEF,
DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
DRXJ_CFG_MPEG_OUTPUT_MISC,
DRXJ_CFG_HW_CFG,
DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t;
typedef enum {
DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
DRXJ_CFG_AGC_IF,
DRXJ_CFG_AGC_INTERNAL,
DRXJ_CFG_PRE_SAW,
DRXJ_CFG_AFE_GAIN,
DRXJ_CFG_SYMBOL_CLK_OFFSET,
DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
DRXJ_CFG_FEC_MERS_SEQ_COUNT,
DRXJ_CFG_OOB_MISC,
DRXJ_CFG_SMART_ANT,
DRXJ_CFG_OOB_PRE_SAW,
DRXJ_CFG_VSB_MISC,
DRXJ_CFG_RESET_PACKET_ERR,
/* ATV (FM) */
DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
DRXJ_CFG_ATV_MISC,
DRXJ_CFG_ATV_EQU_COEF,
DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
DRXJ_CFG_MPEG_OUTPUT_MISC,
DRXJ_CFG_HW_CFG,
DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t;
/**
* /struct DRXJCfgSmartAntIO_t
* smart antenna i/o.
*/
typedef enum DRXJCfgSmartAntIO_t {
DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
typedef enum DRXJCfgSmartAntIO_t {
DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
/**
* /struct DRXJCfgSmartAnt_t
* Set smart antenna.
*/
typedef struct {
DRXJCfgSmartAntIO_t io;
u16_t ctrlData;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
typedef struct {
DRXJCfgSmartAntIO_t io;
u16_t ctrlData;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
/**
* /struct DRXJAGCSTATUS_t
* AGC status information from the DRXJ-IQM-AF.
*/
typedef struct {
u16_t IFAGC;
u16_t RFAGC;
u16_t DigitalAGC;
}DRXJAgcStatus_t, *pDRXJAgcStatus_t;
typedef struct {
u16_t IFAGC;
u16_t RFAGC;
u16_t DigitalAGC;
} DRXJAgcStatus_t, *pDRXJAgcStatus_t;
/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
......@@ -170,27 +173,27 @@ typedef struct {
* /struct DRXJAgcCtrlMode_t
* Available AGCs modes in the DRXJ.
*/
typedef enum {
DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
typedef enum {
DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
/**
* /struct DRXJCfgAgc_t
* Generic interface for all AGCs present on the DRXJ.
*/
typedef struct {
DRXStandard_t standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
u16_t outputLevel; /* range dependent on AGC */
u16_t minOutputLevel; /* range dependent on AGC */
u16_t maxOutputLevel; /* range dependent on AGC */
u16_t speed; /* range dependent on AGC */
u16_t top; /* rf-agc take over point */
u16_t cutOffCurrent; /* rf-agc is accelerated if output current
is below cut-off current */
}DRXJCfgAgc_t, *pDRXJCfgAgc_t;
typedef struct {
DRXStandard_t standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
u16_t outputLevel; /* range dependent on AGC */
u16_t minOutputLevel; /* range dependent on AGC */
u16_t maxOutputLevel; /* range dependent on AGC */
u16_t speed; /* range dependent on AGC */
u16_t top; /* rf-agc take over point */
u16_t cutOffCurrent; /* rf-agc is accelerated if output current
is below cut-off current */
} DRXJCfgAgc_t, *pDRXJCfgAgc_t;
/* DRXJ_CFG_PRE_SAW */
......@@ -198,11 +201,11 @@ typedef struct {
* /struct DRXJCfgPreSaw_t
* Interface to configure pre SAW sense.
*/
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t reference; /* pre SAW reference value, range 0 .. 31 */
Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t reference; /* pre SAW reference value, range 0 .. 31 */
Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
/* DRXJ_CFG_AFE_GAIN */
......@@ -210,10 +213,10 @@ typedef struct {
* /struct DRXJCfgAfeGain_t
* Interface to configure gain of AFE (LNA + PGA).
*/
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
/**
* /struct DRXJRSErrors_t
......@@ -222,46 +225,52 @@ typedef struct {
* Container for errors that are received in the most recently finished measurment period
*
*/
typedef struct {
u16_t nrBitErrors; /**< no of pre RS bit errors */
u16_t nrSymbolErrors; /**< no of pre RS symbol errors */
u16_t nrPacketErrors; /**< no of pre RS packet errors */
u16_t nrFailures; /**< no of post RS failures to decode */
u16_t nrSncParFailCount; /**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t;
typedef struct {
u16_t nrBitErrors;
/**< no of pre RS bit errors */
u16_t nrSymbolErrors;
/**< no of pre RS symbol errors */
u16_t nrPacketErrors;
/**< no of pre RS packet errors */
u16_t nrFailures;
/**< no of post RS failures to decode */
u16_t nrSncParFailCount;
/**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t;
/**
* /struct DRXJCfgVSBMisc_t
* symbol error rate
*/
typedef struct{
u32_t symbError; /**< symbol error rate sps */
}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
typedef struct {
u32_t symbError;
/**< symbol error rate sps */
} DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
/**
* /enum DRXJMpegOutputClockRate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
/**
* /enum DRXJMpegOutputClockRate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
typedef enum {
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
/**
* /struct DRXJCfgMisc_t
......@@ -269,49 +278,52 @@ typedef enum {
* reverse MPEG output bit order
* set MPEG output clock rate
*/
typedef struct{
Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */
Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
typedef struct {
Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */
Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate;
/**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
} DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
/**
* /enum DRXJXtalFreq_t
* Supported external crystal reference frequency.
*/
typedef enum{
DRXJ_XTAL_FREQ_RSVD,
DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ
}DRXJXtalFreq_t, *pDRXJXtalFreq_t;
typedef enum {
DRXJ_XTAL_FREQ_RSVD,
DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ
} DRXJXtalFreq_t, *pDRXJXtalFreq_t;
/**
* /enum DRXJXtalFreq_t
* Supported external crystal reference frequency.
*/
typedef enum{
DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS
}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
typedef enum {
DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS
} DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
/**
* /struct DRXJCfgHwCfg_t
* Get hw configuration, such as crystal reference frequency, I2C speed, etc...
*/
typedef struct{
DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */
}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
typedef struct {
DRXJXtalFreq_t xtalFreq;
/**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed;
/**< 100 or 400 kbps */
} DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
/*
* DRXJ_CFG_ATV_MISC
*/
typedef struct{
s16_t peakFilter; /* -8 .. 15 */
u16_t noiseFilter; /* 0 .. 15 */
}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
typedef struct {
s16_t peakFilter; /* -8 .. 15 */
u16_t noiseFilter; /* 0 .. 15 */
} DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
/*
* DRXJCfgOOBMisc_t
......@@ -327,51 +339,51 @@ typedef struct{
#define DRXJ_OOB_STATE_EQT_HUNT 0x30
#define DRXJ_OOB_STATE_SYNC 0x40
typedef struct{
DRXJAgcStatus_t agc;
Bool_t eqLock;
Bool_t symTimingLock;
Bool_t phaseLock;
Bool_t freqLock;
Bool_t digGainLock;
Bool_t anaGainLock;
u8_t state;
}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
typedef struct {
DRXJAgcStatus_t agc;
Bool_t eqLock;
Bool_t symTimingLock;
Bool_t phaseLock;
Bool_t freqLock;
Bool_t digGainLock;
Bool_t anaGainLock;
u8_t state;
} DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
/*
* Index of in array of coef
*/
typedef enum {
DRXJ_OOB_LO_POW_MINUS0DB = 0,
DRXJ_OOB_LO_POW_MINUS5DB,
DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
typedef enum {
DRXJ_OOB_LO_POW_MINUS0DB = 0,
DRXJ_OOB_LO_POW_MINUS5DB,
DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
/*
* DRXJ_CFG_ATV_EQU_COEF
*/
typedef struct {
s16_t coef0; /* -256 .. 255 */
s16_t coef1; /* -256 .. 255 */
s16_t coef2; /* -256 .. 255 */
s16_t coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
typedef struct {
s16_t coef0; /* -256 .. 255 */
s16_t coef1; /* -256 .. 255 */
s16_t coef2; /* -256 .. 255 */
s16_t coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
/*
* Index of in array of coef
*/
typedef enum {
DRXJ_COEF_IDX_MN = 0,
DRXJ_COEF_IDX_FM ,
DRXJ_COEF_IDX_L ,
DRXJ_COEF_IDX_LP ,
DRXJ_COEF_IDX_BG ,
DRXJ_COEF_IDX_DK ,
DRXJ_COEF_IDX_I ,
DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
typedef enum {
DRXJ_COEF_IDX_MN = 0,
DRXJ_COEF_IDX_FM,
DRXJ_COEF_IDX_L,
DRXJ_COEF_IDX_LP,
DRXJ_COEF_IDX_BG,
DRXJ_COEF_IDX_DK,
DRXJ_COEF_IDX_I,
DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
/*
* DRXJ_CFG_ATV_OUTPUT
......@@ -382,37 +394,37 @@ typedef enum {
* Attenuation setting for SIF AGC.
*
*/
typedef enum {
DRXJ_SIF_ATTENUATION_0DB,
DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
typedef enum {
DRXJ_SIF_ATTENUATION_0DB,
DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
/**
* /struct DRXJCfgAtvOutput_t
* SIF attenuation setting.
*
*/
typedef struct {
Bool_t enableCVBSOutput; /* TRUE= enabled */
Bool_t enableSIFOutput; /* TRUE= enabled */
DRXJSIFAttenuation_t sifAttenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
typedef struct {
Bool_t enableCVBSOutput; /* TRUE= enabled */
Bool_t enableSIFOutput; /* TRUE= enabled */
DRXJSIFAttenuation_t sifAttenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
/*
DRXJ_CFG_ATV_AGC_STATUS (get only)
*/
/* TODO : AFE interface not yet finished, subject to change */
typedef struct {
u16_t rfAgcGain ; /* 0 .. 877 uA */
u16_t ifAgcGain ; /* 0 .. 877 uA */
s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */
s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */
u16_t rfAgcLoopGain ; /* 0 .. 7 */
u16_t ifAgcLoopGain ; /* 0 .. 7 */
u16_t videoAgcLoopGain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
typedef struct {
u16_t rfAgcGain; /* 0 .. 877 uA */
u16_t ifAgcGain; /* 0 .. 877 uA */
s16_t videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */
s16_t audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */
u16_t rfAgcLoopGain; /* 0 .. 7 */
u16_t ifAgcLoopGain; /* 0 .. 7 */
u16_t videoAgcLoopGain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
/*============================================================================*/
/*============================================================================*/
......@@ -433,129 +445,136 @@ typedef struct {
* Global data container for DRXJ specific data.
*
*/
typedef struct {
/* device capabilties (determined during DRX_Open()) */
Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
Bool_t hasOOB; /**< TRUE if OOB supported */
Bool_t hasNTSC; /**< TRUE if NTSC supported */
Bool_t hasBTSC; /**< TRUE if BTSC supported */
Bool_t hasSMATX; /**< TRUE if mat_tx is available */
Bool_t hasSMARX; /**< TRUE if mat_rx is available */
Bool_t hasGPIO; /**< TRUE if GPIO is available */
Bool_t hasIRQN; /**< TRUE if IRQN is available */
/* A1/A2/A... */
u8_t mfx; /**< metal fix */
/* tuner settings */
Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */
/* standard/channel settings */
DRXStandard_t standard; /**< current standard information */
DRXConstellation_t constellation; /**< current constellation */
DRXFrequency_t frequency; /**< center signal frequency in KHz */
DRXBandwidth_t currBandwidth; /**< current channel bandwidth */
DRXMirror_t mirror; /**< current channel mirror */
/* signal quality information */
u32_t fecBitsDesired; /**< BER accounting period */
u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
u16_t qamVdPeriod; /**< Viterbi Measurement period */
u16_t fecRsPlen; /**< defines RS BER measurement period */
u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
/* HI configuration */
u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
/* UIO configuartion */
DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
/* IQM fs frequecy shift and inversion */
u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
Bool_t posImage; /**< Ture: positive image */
/* IQM RC frequecy shift */
u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
/* ATV configuartion */
u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */
s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
Bool_t enableSIFOutput; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t
sifAttenuation; /**< current SIF att setting */
/* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
/* PGA gain configuration for QAM and VSB */
u16_t qamPgaCfg; /**< qam PGA config */
u16_t vsbPgaCfg; /**< vsb PGA config */
/* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */
/* Version information */
char vText[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2]; /**< allocated version list */
/* smart antenna configuration */
Bool_t smartAntInverted;
/* Tracking filter setting for OOB */
u16_t oobTrkFilterCfg[8];
Bool_t oobPowerOn;
/* MPEG static bitrate setting */
u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
Bool_t bitReverseMpegOutout; /**< MPEG output bit order */
DRXJMpegOutputClockRate_t
mpegOutputClockRate; /**< MPEG output clock rate */
DRXJMpegStartWidth_t
mpegStartWidth; /**< MPEG Start width */
/* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
u16_t atvPgaCfg; /**< atv pga config */
u32_t currSymbolRate;
/* pin-safe mode */
Bool_t pdrSafeMode; /**< PDR safe mode activated */
u16_t pdrSafeRestoreValGpio;
u16_t pdrSafeRestoreValVSync;
u16_t pdrSafeRestoreValSmaRx;
u16_t pdrSafeRestoreValSmaTx;
/* OOB pre-saw value */
u16_t oobPreSaw;
DRXJCfgOobLoPower_t oobLoPow;
DRXAudData_t audData; /**< audio storage */
} DRXJData_t, *pDRXJData_t;
typedef struct {
/* device capabilties (determined during DRX_Open()) */
Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
Bool_t hasOOB; /**< TRUE if OOB supported */
Bool_t hasNTSC; /**< TRUE if NTSC supported */
Bool_t hasBTSC; /**< TRUE if BTSC supported */
Bool_t hasSMATX; /**< TRUE if mat_tx is available */
Bool_t hasSMARX; /**< TRUE if mat_rx is available */
Bool_t hasGPIO; /**< TRUE if GPIO is available */
Bool_t hasIRQN; /**< TRUE if IRQN is available */
/* A1/A2/A... */
u8_t mfx; /**< metal fix */
/* tuner settings */
Bool_t mirrorFreqSpectOOB;/**< tuner inversion (TRUE = tuner mirrors the signal */
/* standard/channel settings */
DRXStandard_t standard; /**< current standard information */
DRXConstellation_t constellation;
/**< current constellation */
DRXFrequency_t frequency; /**< center signal frequency in KHz */
DRXBandwidth_t currBandwidth;
/**< current channel bandwidth */
DRXMirror_t mirror; /**< current channel mirror */
/* signal quality information */
u32_t fecBitsDesired; /**< BER accounting period */
u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
u16_t qamVdPeriod; /**< Viterbi Measurement period */
u16_t fecRsPlen; /**< defines RS BER measurement period */
u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
/* HI configuration */
u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
/* UIO configuartion */
DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
/* IQM fs frequecy shift and inversion */
u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
Bool_t posImage; /**< Ture: positive image */
/* IQM RC frequecy shift */
u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
/* ATV configuartion */
u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
Bool_t phaseCorrectionBypass;/**< flag: TRUE=bypass */
s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
Bool_t enableSIFOutput; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t sifAttenuation;
/**< current SIF att setting */
/* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
/* PGA gain configuration for QAM and VSB */
u16_t qamPgaCfg; /**< qam PGA config */
u16_t vsbPgaCfg; /**< vsb PGA config */
/* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg;
/**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg;
/**< qam pre SAW config */
/* Version information */
char vText[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2];
/**< allocated version list */
/* smart antenna configuration */
Bool_t smartAntInverted;
/* Tracking filter setting for OOB */
u16_t oobTrkFilterCfg[8];
Bool_t oobPowerOn;
/* MPEG static bitrate setting */
u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
Bool_t bitReverseMpegOutout;/**< MPEG output bit order */
DRXJMpegOutputClockRate_t mpegOutputClockRate;
/**< MPEG output clock rate */
DRXJMpegStartWidth_t mpegStartWidth;
/**< MPEG Start width */
/* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg;
/**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
u16_t atvPgaCfg; /**< atv pga config */
u32_t currSymbolRate;
/* pin-safe mode */
Bool_t pdrSafeMode; /**< PDR safe mode activated */
u16_t pdrSafeRestoreValGpio;
u16_t pdrSafeRestoreValVSync;
u16_t pdrSafeRestoreValSmaRx;
u16_t pdrSafeRestoreValSmaTx;
/* OOB pre-saw value */
u16_t oobPreSaw;
DRXJCfgOobLoPower_t oobLoPow;
DRXAudData_t audData;
/**< audio storage */
} DRXJData_t, *pDRXJData_t;
/*-------------------------------------------------------------------------
Access MACROS
......@@ -595,7 +614,6 @@ Access MACROS
DRXJ_ATTR_BTSC_DETECT( d ) = (x); \
} while(0)
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
......@@ -705,21 +723,20 @@ STRUCTS
Exported FUNCTIONS
-------------------------------------------------------------------------*/
extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl,
void *ctrlData);
extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl, void *ctrlData);
/*-------------------------------------------------------------------------
Exported GLOBAL VARIABLES
-------------------------------------------------------------------------*/
extern DRXAccessFunc_t drxDapDRXJFunct_g;
extern DRXDemodFunc_t DRXJFunctions_g;
extern DRXJData_t DRXJData_g;
extern I2CDeviceAddr_t DRXJDefaultAddr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g;
extern DRXAccessFunc_t drxDapDRXJFunct_g;
extern DRXDemodFunc_t DRXJFunctions_g;
extern DRXJData_t DRXJData_g;
extern I2CDeviceAddr_t DRXJDefaultAddr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g;
/*-------------------------------------------------------------------------
THE END
......@@ -727,4 +744,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXJ_H__ */
#endif /* __DRXJ_H__ */
drivers/media/dvb-frontends/drx39xyj/drxj_map.h
View file @ 443f18d0
......@@ -53,15 +53,10 @@ extern "C" {
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drxj_map[];
extern RegisterTableInfo_t drxj_map_info[];
extern RegisterTable_t drxj_map[];
extern RegisterTableInfo_t drxj_map_info[];
#endif
#define ATV_COMM_EXEC__A 0xC00000
#define ATV_COMM_EXEC__W 2
#define ATV_COMM_EXEC__M 0x3
......@@ -108,8 +103,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_COMM_KEY_MIN 0x0
#define ATV_COMM_KEY_MAX 0xFFFF
#define ATV_TOP_COMM_EXEC__A 0xC10000
#define ATV_TOP_COMM_EXEC__W 2
#define ATV_TOP_COMM_EXEC__M 0x3
......@@ -168,7 +161,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0
#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200
#define ATV_TOP_COMM_INT_REQ__A 0xC10003
#define ATV_TOP_COMM_INT_REQ__W 16
#define ATV_TOP_COMM_INT_REQ__M 0xFFFF
......@@ -246,7 +238,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_COMM_KEY_KEY_MIN 0x0
#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF
#define ATV_TOP_CR_AMP_TH__A 0xC10010
#define ATV_TOP_CR_AMP_TH__W 8
#define ATV_TOP_CR_AMP_TH__M 0xFF
......@@ -279,7 +270,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_CR_CONT_CR_I_MN 0x80
#define ATV_TOP_CR_CONT_CR_I_FM 0x0
#define ATV_TOP_CR_OVM_TH__A 0xC10012
#define ATV_TOP_CR_OVM_TH__W 8
#define ATV_TOP_CR_OVM_TH__M 0xFF
......@@ -287,7 +277,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_CR_OVM_TH_MN 0xA0
#define ATV_TOP_CR_OVM_TH_FM 0x0
#define ATV_TOP_NOISE_TH__A 0xC10013
#define ATV_TOP_NOISE_TH__W 4
#define ATV_TOP_NOISE_TH__M 0xF
......@@ -338,7 +327,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_EQU3_EQU_C3__PRE 0x160
#define ATV_TOP_EQU3_EQU_C3_MN 0x60
#define ATV_TOP_ROT_MODE__A 0xC10018
#define ATV_TOP_ROT_MODE__W 1
#define ATV_TOP_ROT_MODE__M 0x1
......@@ -398,7 +386,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_STD_VID_POL_NEG 0x0
#define ATV_TOP_STD_VID_POL_POS 0x2
#define ATV_TOP_VID_AMP__A 0xC1001B
#define ATV_TOP_VID_AMP__W 12
#define ATV_TOP_VID_AMP__M 0xFFF
......@@ -406,7 +393,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_VID_AMP_MN 0x380
#define ATV_TOP_VID_AMP_FM 0x0
#define ATV_TOP_VID_PEAK__A 0xC1001C
#define ATV_TOP_VID_PEAK__W 5
#define ATV_TOP_VID_PEAK__M 0x1F
......@@ -418,14 +404,12 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_FAGC_TH__PRE 0x2B2
#define ATV_TOP_FAGC_TH_MN 0x2B2
#define ATV_TOP_SYNC_SLICE__A 0xC1001E
#define ATV_TOP_SYNC_SLICE__W 11
#define ATV_TOP_SYNC_SLICE__M 0x7FF
#define ATV_TOP_SYNC_SLICE__PRE 0x243
#define ATV_TOP_SYNC_SLICE_MN 0x243
#define ATV_TOP_SIF_GAIN__A 0xC1001F
#define ATV_TOP_SIF_GAIN__W 11
#define ATV_TOP_SIF_GAIN__M 0x7FF
......@@ -481,7 +465,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2
#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0
#define ATV_TOP_OVERRIDE_SFR__A 0xC10026
#define ATV_TOP_OVERRIDE_SFR__W 1
#define ATV_TOP_OVERRIDE_SFR__M 0x1
......@@ -489,7 +472,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0
#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1
#define ATV_TOP_SFR_VID_GAIN__A 0xC10027
#define ATV_TOP_SFR_VID_GAIN__W 16
#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF
......@@ -544,8 +526,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0
#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10
#define ATV_AFT_COMM_EXEC__A 0xFF0000
#define ATV_AFT_COMM_EXEC__W 2
#define ATV_AFT_COMM_EXEC__M 0x3
......@@ -554,16 +534,11 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ATV_AFT_COMM_EXEC_ACTIVE 0x1
#define ATV_AFT_COMM_EXEC_HOLD 0x2
#define ATV_AFT_TST__A 0xFF0010
#define ATV_AFT_TST__W 4
#define ATV_AFT_TST__M 0xF
#define ATV_AFT_TST__PRE 0x0
#define AUD_COMM_EXEC__A 0x1000000
#define AUD_COMM_EXEC__W 2
#define AUD_COMM_EXEC__M 0x3
......@@ -576,8 +551,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_COMM_MB__M 0xFFFF
#define AUD_COMM_MB__PRE 0x0
#define AUD_TOP_COMM_EXEC__A 0x1010000
#define AUD_TOP_COMM_EXEC__W 2
#define AUD_TOP_COMM_EXEC__M 0x3
......@@ -694,14 +667,11 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF
#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0
#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014
#define AUD_TOP_DEMOD_TBO_SEL__W 5
#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F
#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0
#define AUD_DEM_WR_MODUS__A 0x1030030
#define AUD_DEM_WR_MODUS__W 16
#define AUD_DEM_WR_MODUS__M 0xFFFF
......@@ -803,8 +773,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30
#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40
#define AUD_DEM_RD_STANDARD_RES__A 0x102007E
#define AUD_DEM_RD_STANDARD_RES__W 16
#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF
......@@ -902,14 +870,11 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0
#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF
#define AUD_DEM_RD_RDS_DATA__A 0x1020210
#define AUD_DEM_RD_RDS_DATA__W 12
#define AUD_DEM_RD_RDS_DATA__M 0xFFF
#define AUD_DEM_RD_RDS_DATA__PRE 0x0
#define AUD_DSP_WR_FM_PRESC__A 0x105000E
#define AUD_DSP_WR_FM_PRESC__W 16
#define AUD_DSP_WR_FM_PRESC__M 0xFFFF
......@@ -927,7 +892,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300
#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900
#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010
#define AUD_DSP_WR_NICAM_PRESC__W 16
#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF
......@@ -1030,9 +994,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20
#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30
#define AUD_DSP_RD_QPEAK_L__A 0x1040019
#define AUD_DSP_RD_QPEAK_L__W 16
#define AUD_DSP_RD_QPEAK_L__M 0xFFFF
......@@ -1043,8 +1004,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_RD_QPEAK_R__M 0xFFFF
#define AUD_DSP_RD_QPEAK_R__PRE 0x0
#define AUD_DSP_WR_BEEPER__A 0x1050014
#define AUD_DSP_WR_BEEPER__W 16
#define AUD_DSP_WR_BEEPER__M 0xFFFF
......@@ -1060,8 +1019,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F
#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x0
#define AUD_DEM_WR_I2S_CONFIG2__A 0x1030050
#define AUD_DEM_WR_I2S_CONFIG2__W 16
#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF
......@@ -1109,8 +1066,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x0
#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x1
#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A
#define AUD_DSP_WR_I2S_OUT_FS__W 16
#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF
......@@ -1149,8 +1104,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x2
#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x3
#define AUD_DSP_RD_STATUS2__A 0x104007B
#define AUD_DSP_RD_STATUS2__W 16
#define AUD_DSP_RD_STATUS2__M 0xFFFF
......@@ -1183,9 +1136,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF
#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x42
#define AUD_DEM_WR_DCO_B_HI__A 0x103009B
#define AUD_DEM_WR_DCO_B_HI__W 16
#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF
......@@ -1255,8 +1205,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF
#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A
#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x1020023
#define AUD_DEM_RD_NIC_C_AD_BITS__W 16
#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF
......@@ -1314,9 +1262,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF
#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x0
#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F
#define AUD_DEM_WR_FM_DEEMPH__W 16
#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF
......@@ -1325,7 +1270,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_WR_FM_DEEMPH_75US 0x1
#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F
#define AUD_DEM_WR_FM_MATRIX__A 0x103006F
#define AUD_DEM_WR_FM_MATRIX__W 16
#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF
......@@ -1336,8 +1280,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x3
#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x4
#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x1040018
#define AUD_DSP_RD_FM_IDENT_VALUE__W 16
#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF
......@@ -1368,8 +1310,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x0
#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x1030017
#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 16
#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF
......@@ -1382,9 +1322,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x0
#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F
#define AUD_DSP_WR_SYNC_OUT__A 0x1050026
#define AUD_DSP_WR_SYNC_OUT__W 16
#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF
......@@ -1392,8 +1329,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_DSP_WR_SYNC_OUT_OFF 0x0
#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x1
#define AUD_XFP_DRAM_1K__A 0x1060000
#define AUD_XFP_DRAM_1K__W 16
#define AUD_XFP_DRAM_1K__M 0xFFFF
......@@ -1403,8 +1338,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_XFP_DRAM_1K_D__M 0xFFFF
#define AUD_XFP_DRAM_1K_D__PRE 0x0
#define AUD_XFP_PRAM_4K__A 0x1070000
#define AUD_XFP_PRAM_4K__W 16
#define AUD_XFP_PRAM_4K__M 0xFFFF
......@@ -1414,8 +1347,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_XFP_PRAM_4K_D__M 0xFFFF
#define AUD_XFP_PRAM_4K_D__PRE 0x0
#define AUD_XDFP_DRAM_1K__A 0x1080000
#define AUD_XDFP_DRAM_1K__W 16
#define AUD_XDFP_DRAM_1K__M 0xFFFF
......@@ -1425,8 +1356,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_XDFP_DRAM_1K_D__M 0xFFFF
#define AUD_XDFP_DRAM_1K_D__PRE 0x0
#define AUD_XDFP_PRAM_4K__A 0x1090000
#define AUD_XDFP_PRAM_4K__W 16
#define AUD_XDFP_PRAM_4K__M 0xFFFF
......@@ -1436,10 +1365,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define AUD_XDFP_PRAM_4K_D__M 0xFFFF
#define AUD_XDFP_PRAM_4K_D__PRE 0x0
#define FEC_COMM_EXEC__A 0x2400000
#define FEC_COMM_EXEC__W 2
#define FEC_COMM_EXEC__M 0x3
......@@ -1482,8 +1407,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_COMM_INT_STM__M 0xFFFF
#define FEC_COMM_INT_STM__PRE 0x0
#define FEC_TOP_COMM_EXEC__A 0x2410000
#define FEC_TOP_COMM_EXEC__W 2
#define FEC_TOP_COMM_EXEC__M 0x3
......@@ -1492,7 +1415,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_TOP_COMM_EXEC_ACTIVE 0x1
#define FEC_TOP_COMM_EXEC_HOLD 0x2
#define FEC_TOP_ANNEX__A 0x2410010
#define FEC_TOP_ANNEX__W 2
#define FEC_TOP_ANNEX__M 0x3
......@@ -1502,8 +1424,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_TOP_ANNEX_C 0x2
#define FEC_TOP_ANNEX_D 0x3
#define FEC_DI_COMM_EXEC__A 0x2420000
#define FEC_DI_COMM_EXEC__W 2
#define FEC_DI_COMM_EXEC__M 0x3
......@@ -1574,7 +1494,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2
#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0
#define FEC_DI_STATUS__A 0x2420010
#define FEC_DI_STATUS__W 1
#define FEC_DI_STATUS__M 0x1
......@@ -1599,7 +1518,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4
#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0
#define FEC_DI_CONTROL_WORD__A 0x2420012
#define FEC_DI_CONTROL_WORD__W 4
#define FEC_DI_CONTROL_WORD__M 0xF
......@@ -1620,8 +1538,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_DI_TIMEOUT_HI__M 0xFF
#define FEC_DI_TIMEOUT_HI__PRE 0xA
#define FEC_RS_COMM_EXEC__A 0x2430000
#define FEC_RS_COMM_EXEC__W 2
#define FEC_RS_COMM_EXEC__M 0x3
......@@ -1786,8 +1702,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_RS_NR_FAILURES_EXP__M 0xF000
#define FEC_RS_NR_FAILURES_EXP__PRE 0x0
#define FEC_OC_COMM_EXEC__A 0x2440000
#define FEC_OC_COMM_EXEC__W 2
#define FEC_OC_COMM_EXEC__M 0x3
......@@ -2001,7 +1915,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2
#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0
#define FEC_OC_DPR_UNLOCK__A 0x2440013
#define FEC_OC_DPR_UNLOCK__W 1
#define FEC_OC_DPR_UNLOCK__M 0x1
......@@ -2026,7 +1939,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4
#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0
#define FEC_OC_DTO_PERIOD__A 0x2440015
#define FEC_OC_DTO_PERIOD__W 8
#define FEC_OC_DTO_PERIOD__M 0xFF
......@@ -2701,22 +2613,12 @@ extern RegisterTableInfo_t drxj_map_info[];
#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF
#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0
#define FEC_DI_RAM__A 0x2450000
#define FEC_RS_RAM__A 0x2460000
#define FEC_OC_RAM__A 0x2470000
#define IQM_COMM_EXEC__A 0x1800000
#define IQM_COMM_EXEC__W 2
#define IQM_COMM_EXEC__M 0x3
......@@ -2757,8 +2659,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_COMM_INT_STM__M 0xFFFF
#define IQM_COMM_INT_STM__PRE 0x0
#define IQM_FS_COMM_EXEC__A 0x1820000
#define IQM_FS_COMM_EXEC__W 2
#define IQM_FS_COMM_EXEC__M 0x3
......@@ -2809,8 +2709,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_FS_ADJ_SEL_QAM 0x1
#define IQM_FS_ADJ_SEL_VSB 0x2
#define IQM_FD_COMM_EXEC__A 0x1830000
#define IQM_FD_COMM_EXEC__W 2
#define IQM_FD_COMM_EXEC__M 0x3
......@@ -2836,8 +2734,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0
#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2
#define IQM_RC_COMM_EXEC__A 0x1840000
#define IQM_RC_COMM_EXEC__W 2
#define IQM_RC_COMM_EXEC__M 0x3
......@@ -2898,7 +2794,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_RC_CROUT_ENA_ENA__M 0x1
#define IQM_RC_CROUT_ENA_ENA__PRE 0x0
#define IQM_RC_STRETCH__A 0x1840016
#define IQM_RC_STRETCH__W 5
#define IQM_RC_STRETCH__M 0x1F
......@@ -2907,8 +2802,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_RC_STRETCH_QAM_B_256 0x1C
#define IQM_RC_STRETCH_ATV 0xF
#define IQM_RT_COMM_EXEC__A 0x1850000
#define IQM_RT_COMM_EXEC__W 2
#define IQM_RT_COMM_EXEC__M 0x3
......@@ -2953,7 +2846,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0
#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2
#define IQM_RT_LO_INCR__A 0x1850011
#define IQM_RT_LO_INCR__W 12
#define IQM_RT_LO_INCR__M 0xFFF
......@@ -2978,7 +2870,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_RT_ROT_BP_ROT_BPF__M 0x2
#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0
#define IQM_RT_LP_BP__A 0x1850013
#define IQM_RT_LP_BP__W 1
#define IQM_RT_LP_BP__M 0x1
......@@ -2989,8 +2880,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_RT_DELAY__M 0x7F
#define IQM_RT_DELAY__PRE 0x45
#define IQM_CF_COMM_EXEC__A 0x1860000
#define IQM_CF_COMM_EXEC__W 2
#define IQM_CF_COMM_EXEC__M 0x3
......@@ -3097,7 +2986,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_CF_OUT_ENA_VSB__M 0x4
#define IQM_CF_OUT_ENA_VSB__PRE 0x0
#define IQM_CF_ADJ_SEL__A 0x1860013
#define IQM_CF_ADJ_SEL__W 2
#define IQM_CF_ADJ_SEL__M 0x3
......@@ -3353,8 +3241,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_CF_TAP_IM27__M 0x7FF
#define IQM_CF_TAP_IM27__PRE 0x2
#define IQM_AF_COMM_EXEC__A 0x1870000
#define IQM_AF_COMM_EXEC__W 2
#define IQM_AF_COMM_EXEC__M 0x3
......@@ -3441,7 +3327,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2
#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0
#define IQM_AF_FDB_SEL__A 0x1870010
#define IQM_AF_FDB_SEL__W 1
#define IQM_AF_FDB_SEL__M 0x1
......@@ -3470,7 +3355,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0
#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2
#define IQM_AF_MON_IN_MUX__A 0x1870013
#define IQM_AF_MON_IN_MUX__W 2
#define IQM_AF_MON_IN_MUX__M 0x3
......@@ -3573,7 +3457,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0
#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8
#define IQM_AF_CLP_CLIP__A 0x1870022
#define IQM_AF_CLP_CLIP__W 16
#define IQM_AF_CLP_CLIP__M 0xFFFF
......@@ -3587,7 +3470,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_CLP_LEN_QAM_B_256 0x400
#define IQM_AF_CLP_LEN_ATV 0x0
#define IQM_AF_CLP_TH__A 0x1870024
#define IQM_AF_CLP_TH__W 9
#define IQM_AF_CLP_TH__M 0x1FF
......@@ -3596,7 +3478,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_CLP_TH_QAM_B_256 0x80
#define IQM_AF_CLP_TH_ATV 0x1C0
#define IQM_AF_DCF_BYPASS__A 0x1870025
#define IQM_AF_DCF_BYPASS__W 1
#define IQM_AF_DCF_BYPASS__M 0x1
......@@ -3604,7 +3485,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_DCF_BYPASS_ACTIVE 0x0
#define IQM_AF_DCF_BYPASS_BYPASS 0x1
#define IQM_AF_SNS_LEN__A 0x1870026
#define IQM_AF_SNS_LEN__W 16
#define IQM_AF_SNS_LEN__M 0xFFFF
......@@ -3613,7 +3493,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_SNS_LEN_QAM_B_256 0x400
#define IQM_AF_SNS_LEN_ATV 0x0
#define IQM_AF_SNS_SENSE__A 0x1870027
#define IQM_AF_SNS_SENSE__W 16
#define IQM_AF_SNS_SENSE__M 0xFFFF
......@@ -3699,7 +3578,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x20
#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x0
#define IQM_AF_AMUX__A 0x187002D
#define IQM_AF_AMUX__W 2
#define IQM_AF_AMUX__M 0x3
......@@ -3710,8 +3588,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_AF_TST_AFEMAIN__M 0xFF
#define IQM_AF_TST_AFEMAIN__PRE 0x0
#define IQM_RT_RAM__A 0x1880000
#define IQM_RT_RAM_DLY__B 0
......@@ -3719,10 +3595,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define IQM_RT_RAM_DLY__M 0x1FFF
#define IQM_RT_RAM_DLY__PRE 0x0
#define ORX_COMM_EXEC__A 0x2000000
#define ORX_COMM_EXEC__W 2
#define ORX_COMM_EXEC__M 0x3
......@@ -3764,7 +3636,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_COMM_INT_REQ_NSU_REQ__M 0x10
#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x0
#define ORX_COMM_INT_STA__A 0x2000005
#define ORX_COMM_INT_STA__W 16
#define ORX_COMM_INT_STA__M 0xFFFF
......@@ -3778,8 +3649,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_COMM_INT_STM__M 0xFFFF
#define ORX_COMM_INT_STM__PRE 0x0
#define ORX_TOP_COMM_EXEC__A 0x2010000
#define ORX_TOP_COMM_EXEC__W 2
#define ORX_TOP_COMM_EXEC__M 0x3
......@@ -3788,7 +3657,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_TOP_COMM_EXEC_ACTIVE 0x1
#define ORX_TOP_COMM_EXEC_HOLD 0x2
#define ORX_TOP_COMM_KEY__A 0x201000F
#define ORX_TOP_COMM_KEY__W 16
#define ORX_TOP_COMM_KEY__M 0xFFFF
......@@ -3827,8 +3695,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x0
#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x4
#define ORX_FWP_COMM_EXEC__A 0x2020000
#define ORX_FWP_COMM_EXEC__W 2
#define ORX_FWP_COMM_EXEC__M 0x3
......@@ -3864,7 +3730,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_FWP_COMM_MB_OBS_MUX__M 0xE0
#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x0
#define ORX_FWP_AAG_LEN_W__A 0x2020010
#define ORX_FWP_AAG_LEN_W__W 16
#define ORX_FWP_AAG_LEN_W__M 0xFFFF
......@@ -3893,7 +3758,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA4
#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC0
#define ORX_FWP_PFI_B_W__A 0x2020015
#define ORX_FWP_PFI_B_W__W 8
#define ORX_FWP_PFI_B_W__M 0xFF
......@@ -3902,7 +3766,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x94
#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB0
#define ORX_FWP_PFI_C_W__A 0x2020016
#define ORX_FWP_PFI_C_W__W 8
#define ORX_FWP_PFI_C_W__M 0xFF
......@@ -3911,7 +3774,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x64
#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x50
#define ORX_FWP_KR1_AMP_R__A 0x2020017
#define ORX_FWP_KR1_AMP_R__W 9
#define ORX_FWP_KR1_AMP_R__M 0x1FF
......@@ -3936,7 +3798,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_FWP_SRC_DGN_W_EXP__M 0xF000
#define ORX_FWP_SRC_DGN_W_EXP__PRE 0x0
#define ORX_FWP_NYQ_ADR_W__A 0x202001A
#define ORX_FWP_NYQ_ADR_W__W 5
#define ORX_FWP_NYQ_ADR_W__M 0x1F
......@@ -3952,8 +3813,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_FWP_IQM_FRQ_W__M 0xFFFF
#define ORX_FWP_IQM_FRQ_W__PRE 0x4301
#define ORX_EQU_COMM_EXEC__A 0x2030000
#define ORX_EQU_COMM_EXEC__W 2
#define ORX_EQU_COMM_EXEC__M 0x3
......@@ -4034,7 +3893,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x2
#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x0
#define ORX_EQU_FFF_SCL_W__A 0x2030010
#define ORX_EQU_FFF_SCL_W__W 1
#define ORX_EQU_FFF_SCL_W__M 0x1
......@@ -4042,7 +3900,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x0
#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x1
#define ORX_EQU_FFF_UPD_W__A 0x2030011
#define ORX_EQU_FFF_UPD_W__W 1
#define ORX_EQU_FFF_UPD_W__M 0x1
......@@ -4050,7 +3907,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x0
#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x1
#define ORX_EQU_FFF_STP_W__A 0x2030012
#define ORX_EQU_FFF_STP_W__W 3
#define ORX_EQU_FFF_STP_W__M 0x7
......@@ -4183,7 +4039,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x0
#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x1
#define ORX_EQU_FBF_UPD_W__A 0x203002C
#define ORX_EQU_FBF_UPD_W__W 1
#define ORX_EQU_FBF_UPD_W__M 0x1
......@@ -4191,7 +4046,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x0
#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x1
#define ORX_EQU_FBF_STP_W__A 0x203002D
#define ORX_EQU_FBF_STP_W__W 3
#define ORX_EQU_FBF_STP_W__M 0x7
......@@ -4274,7 +4128,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x0
#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x1
#define ORX_EQU_ERR_TIS_W__A 0x203003D
#define ORX_EQU_ERR_TIS_W__W 1
#define ORX_EQU_ERR_TIS_W__M 0x1
......@@ -4282,7 +4135,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x0
#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x1
#define ORX_EQU_ERR_EDI_R__A 0x203003E
#define ORX_EQU_ERR_EDI_R__W 5
#define ORX_EQU_ERR_EDI_R__M 0x1F
......@@ -4318,8 +4170,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_EQU_SYN_LEN_W__M 0xFFFF
#define ORX_EQU_SYN_LEN_W__PRE 0x0
#define ORX_DDC_COMM_EXEC__A 0x2040000
#define ORX_DDC_COMM_EXEC__W 2
#define ORX_DDC_COMM_EXEC__M 0x3
......@@ -4435,8 +4285,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_DDC_OFO_SET_W_DISABLE__M 0x8000
#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x0
#define ORX_CON_COMM_EXEC__A 0x2050000
#define ORX_CON_COMM_EXEC__W 2
#define ORX_CON_COMM_EXEC__M 0x3
......@@ -4480,7 +4328,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_CON_RST_W_KRP__M 0x8
#define ORX_CON_RST_W_KRP__PRE 0x0
#define ORX_CON_CPH_PHI_R__A 0x2050012
#define ORX_CON_CPH_PHI_R__W 16
#define ORX_CON_CPH_PHI_R__M 0xFFFF
......@@ -4540,7 +4387,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_CON_CPH_WLC_W_WLIM__M 0xF0
#define ORX_CON_CPH_WLC_W_WLIM__PRE 0x80
#define ORX_CON_CPH_DLY_W__A 0x205001A
#define ORX_CON_CPH_DLY_W__W 3
#define ORX_CON_CPH_DLY_W__M 0x7
......@@ -4586,8 +4432,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_CON_CTI_TAT_W__M 0xF
#define ORX_CON_CTI_TAT_W__PRE 0x3
#define ORX_NSU_COMM_EXEC__A 0x2060000
#define ORX_NSU_COMM_EXEC__W 2
#define ORX_NSU_COMM_EXEC__M 0x3
......@@ -4673,7 +4517,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x0
#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x80
#define ORX_NSU_AOX_LOFRQ_W__A 0x2060011
#define ORX_NSU_AOX_LOFRQ_W__W 16
#define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF
......@@ -4698,7 +4541,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC000
#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x0
#define ORX_NSU_AOX_LOPOW_W__A 0x2060013
#define ORX_NSU_AOX_LOPOW_W__W 2
#define ORX_NSU_AOX_LOPOW_W__M 0x3
......@@ -4708,7 +4550,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x2
#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x3
#define ORX_NSU_AOX_STHR_W__A 0x2060014
#define ORX_NSU_AOX_STHR_W__W 5
#define ORX_NSU_AOX_STHR_W__M 0x1F
......@@ -4748,8 +4589,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x4
#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x0
#define ORX_TST_COMM_EXEC__A 0x23F0000
#define ORX_TST_COMM_EXEC__W 2
#define ORX_TST_COMM_EXEC__M 0x3
......@@ -4758,16 +4597,11 @@ extern RegisterTableInfo_t drxj_map_info[];
#define ORX_TST_COMM_EXEC_ACTIVE 0x1
#define ORX_TST_COMM_EXEC_HOLD 0x2
#define ORX_TST_AOX_TST_W__A 0x23F0010
#define ORX_TST_AOX_TST_W__W 8
#define ORX_TST_AOX_TST_W__M 0xFF
#define ORX_TST_AOX_TST_W__PRE 0x0
#define QAM_COMM_EXEC__A 0x1400000
#define QAM_COMM_EXEC__W 2
#define QAM_COMM_EXEC__M 0x3
......@@ -4818,8 +4652,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_COMM_INT_STM__M 0xFFFF
#define QAM_COMM_INT_STM__PRE 0x0
#define QAM_TOP_COMM_EXEC__A 0x1410000
#define QAM_TOP_COMM_EXEC__W 2
#define QAM_TOP_COMM_EXEC__M 0x3
......@@ -4828,7 +4660,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_TOP_COMM_EXEC_ACTIVE 0x1
#define QAM_TOP_COMM_EXEC_HOLD 0x2
#define QAM_TOP_ANNEX__A 0x1410010
#define QAM_TOP_ANNEX__W 2
#define QAM_TOP_ANNEX__M 0x3
......@@ -4838,7 +4669,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_TOP_ANNEX_C 0x2
#define QAM_TOP_ANNEX_D 0x3
#define QAM_TOP_CONSTELLATION__A 0x1410011
#define QAM_TOP_CONSTELLATION__W 3
#define QAM_TOP_CONSTELLATION__M 0x7
......@@ -4852,8 +4682,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_TOP_CONSTELLATION_QAM128 0x6
#define QAM_TOP_CONSTELLATION_QAM256 0x7
#define QAM_FQ_COMM_EXEC__A 0x1420000
#define QAM_FQ_COMM_EXEC__W 2
#define QAM_FQ_COMM_EXEC__M 0x3
......@@ -4885,7 +4713,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0
#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4
#define QAM_FQ_MU_FACTOR__A 0x1420011
#define QAM_FQ_MU_FACTOR__W 3
#define QAM_FQ_MU_FACTOR__M 0x7
......@@ -5395,8 +5222,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF
#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2
#define QAM_SL_COMM_EXEC__A 0x1430000
#define QAM_SL_COMM_EXEC__W 2
#define QAM_SL_COMM_EXEC__M 0x3
......@@ -5529,7 +5354,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_SL_MODE_TILT_COMP__M 0x400
#define QAM_SL_MODE_TILT_COMP__PRE 0x0
#define QAM_SL_K_FACTOR__A 0x1430011
#define QAM_SL_K_FACTOR__W 4
#define QAM_SL_K_FACTOR__M 0xF
......@@ -5559,7 +5383,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_SL_MEDIAN_FAST__M 0x2000
#define QAM_SL_MEDIAN_FAST__PRE 0x0
#define QAM_SL_ALPHA__A 0x1430013
#define QAM_SL_ALPHA__W 3
#define QAM_SL_ALPHA__M 0x7
......@@ -5589,14 +5412,11 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF
#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0
#define QAM_SL_ERR_POWER__A 0x1430017
#define QAM_SL_ERR_POWER__W 16
#define QAM_SL_ERR_POWER__M 0xFFFF
#define QAM_SL_ERR_POWER__PRE 0x0
#define QAM_DQ_COMM_EXEC__A 0x1440000
#define QAM_DQ_COMM_EXEC__W 2
#define QAM_DQ_COMM_EXEC__M 0x3
......@@ -5637,7 +5457,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_DQ_MODE_FB_DFB 0x10
#define QAM_DQ_MODE_FB_TRELLIS 0x18
#define QAM_DQ_MU_FACTOR__A 0x1440011
#define QAM_DQ_MU_FACTOR__W 3
#define QAM_DQ_MU_FACTOR__M 0x7
......@@ -6311,8 +6130,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF
#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2
#define QAM_LC_COMM_EXEC__A 0x1450000
#define QAM_LC_COMM_EXEC__W 2
#define QAM_LC_COMM_EXEC__M 0x3
......@@ -6768,8 +6585,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF
#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0
#define QAM_VD_COMM_EXEC__A 0x1460000
#define QAM_VD_COMM_EXEC__W 2
#define QAM_VD_COMM_EXEC__M 0x3
......@@ -6890,7 +6705,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F
#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x10
#define QAM_VD_UNLOCK__A 0x1460015
#define QAM_VD_UNLOCK__W 1
#define QAM_VD_UNLOCK__M 0x1
......@@ -6970,8 +6784,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF
#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x0
#define QAM_SY_COMM_EXEC__A 0x1470000
#define QAM_SY_COMM_EXEC__W 2
#define QAM_SY_COMM_EXEC__M 0x3
......@@ -7078,7 +6890,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_SY_STATUS_SYNC_STATE__M 0x3
#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0
#define QAM_SY_TIMEOUT__A 0x1470011
#define QAM_SY_TIMEOUT__W 16
#define QAM_SY_TIMEOUT__M 0xFFFF
......@@ -7113,22 +6924,12 @@ extern RegisterTableInfo_t drxj_map_info[];
#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF
#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0
#define QAM_VD_ISS_RAM__A 0x1480000
#define QAM_VD_QSS_RAM__A 0x1490000
#define QAM_VD_SYM_RAM__A 0x14A0000
#define SCU_COMM_EXEC__A 0x800000
#define SCU_COMM_EXEC__W 2
#define SCU_COMM_EXEC__M 0x3
......@@ -7147,8 +6948,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF
#define SCU_COMM_STATE_COMM_STATE__PRE 0x0
#define SCU_TOP_COMM_EXEC__A 0x810000
#define SCU_TOP_COMM_EXEC__W 2
#define SCU_TOP_COMM_EXEC__M 0x3
......@@ -7157,7 +6956,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_TOP_COMM_EXEC_ACTIVE 0x1
#define SCU_TOP_COMM_EXEC_HOLD 0x2
#define SCU_TOP_COMM_STATE__A 0x810001
#define SCU_TOP_COMM_STATE__W 16
#define SCU_TOP_COMM_STATE__M 0xFFFF
......@@ -7181,8 +6979,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0
#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2
#define SCU_LOW_RAM__A 0x820000
#define SCU_LOW_RAM_LOW__B 0
......@@ -7190,8 +6986,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_LOW_RAM_LOW__M 0xFFFF
#define SCU_LOW_RAM_LOW__PRE 0x0
#define SCU_HIGH_RAM__A 0x830000
#define SCU_HIGH_RAM_HIGH__B 0
......@@ -7199,11 +6993,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_HIGH_RAM_HIGH__M 0xFFFF
#define SCU_HIGH_RAM_HIGH__PRE 0x0
#define SCU_RAM_AGC_RF_MAX__A 0x831E96
#define SCU_RAM_AGC_RF_MAX__W 15
#define SCU_RAM_AGC_RF_MAX__M 0x7FFF
......@@ -7293,7 +7082,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30
#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF
......@@ -7353,7 +7141,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00
#define SCU_RAM_AGC_KI_MAX_IF__PRE 0x0
#define SCU_RAM_AGC_CLP_SUM__A 0x831EA5
#define SCU_RAM_AGC_CLP_SUM__W 16
#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF
......@@ -7561,7 +7348,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0
#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4
#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9
#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16
#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF
......@@ -7918,7 +7704,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF
#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x0
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F01
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 16
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF
......@@ -7937,7 +7722,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC0
#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC1
#define SCU_RAM_ORX_SCU_STATE__A 0x831F03
#define SCU_RAM_ORX_SCU_STATE__W 8
#define SCU_RAM_ORX_SCU_STATE__M 0xFF
......@@ -7953,7 +7737,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x30
#define SCU_RAM_ORX_SCU_STATE_SYNC 0x40
#define SCU_RAM_ORX_SCU_LOCK__A 0x831F04
#define SCU_RAM_ORX_SCU_LOCK__W 16
#define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF
......@@ -7968,7 +7751,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x2
#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x3
#define SCU_RAM_ORX_MER_MIN_DB__A 0x831F06
#define SCU_RAM_ORX_MER_MIN_DB__W 8
#define SCU_RAM_ORX_MER_MIN_DB__M 0xFF
......@@ -8117,7 +7899,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x80
#define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC0
#define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F23
#define SCU_RAM_ORX_FRQ_OFFSET__W 16
#define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF
......@@ -8432,7 +8213,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0
#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80
#define SCU_RAM_ATV_RSV_01__A 0x831F4E
#define SCU_RAM_ATV_RSV_01__W 16
#define SCU_RAM_ATV_RSV_01__M 0xFFFF
......@@ -8496,7 +8276,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF
#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0
#define SCU_RAM_ATV_RSV_05__A 0x831F56
#define SCU_RAM_ATV_RSV_05__W 16
#define SCU_RAM_ATV_RSV_05__M 0xFFFF
......@@ -8556,7 +8335,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF
#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0
#define SCU_RAM_ATV_RSV_13__A 0x831F60
#define SCU_RAM_ATV_RSV_13__W 16
#define SCU_RAM_ATV_RSV_13__M 0xFFFF
......@@ -8596,7 +8374,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF
#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x0
#define SCU_RAM_ATV_RSV_17__A 0x831F66
#define SCU_RAM_ATV_RSV_17__W 16
#define SCU_RAM_ATV_RSV_17__M 0xFFFF
......@@ -10086,7 +9863,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x0
#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x2
#define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD8
#define SCU_RAM_VSB_NOTCH_THRESHOLD__W 16
#define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF
......@@ -10271,7 +10047,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000
#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000
#define SCU_RAM_PARAM_0__A 0x831FFC
#define SCU_RAM_PARAM_0__W 16
#define SCU_RAM_PARAM_0__M 0xFFFF
......@@ -10294,7 +10069,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD
#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC
#define SCU_RAM_COMMAND__A 0x831FFD
#define SCU_RAM_COMMAND__W 16
#define SCU_RAM_COMMAND__M 0xFFFF
......@@ -10385,10 +10159,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF
#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0
#define SIO_COMM_EXEC__A 0x400000
#define SIO_COMM_EXEC__W 2
#define SIO_COMM_EXEC__M 0x3
......@@ -10433,8 +10203,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_COMM_INT_STM__M 0xFFFF
#define SIO_COMM_INT_STM__PRE 0x0
#define SIO_TOP_COMM_EXEC__A 0x410000
#define SIO_TOP_COMM_EXEC__W 2
#define SIO_TOP_COMM_EXEC__M 0x3
......@@ -10443,14 +10211,12 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_TOP_COMM_EXEC_ACTIVE 0x1
#define SIO_TOP_COMM_EXEC_HOLD 0x2
#define SIO_TOP_COMM_KEY__A 0x41000F
#define SIO_TOP_COMM_KEY__W 16
#define SIO_TOP_COMM_KEY__M 0xFFFF
#define SIO_TOP_COMM_KEY__PRE 0x0
#define SIO_TOP_COMM_KEY_KEY 0xFABA
#define SIO_TOP_JTAGID_LO__A 0x410012
#define SIO_TOP_JTAGID_LO__W 16
#define SIO_TOP_JTAGID_LO__M 0xFFFF
......@@ -10461,9 +10227,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_TOP_JTAGID_HI__M 0xFFFF
#define SIO_TOP_JTAGID_HI__PRE 0x0
#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010
#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1
#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1
......@@ -10533,7 +10296,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF
#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0
#define SIO_HI_RA_RAM_S0_CRC__A 0x420017
#define SIO_HI_RA_RAM_S0_CRC__W 16
#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF
......@@ -10638,7 +10400,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF
#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0
#define SIO_HI_RA_RAM_S1_CRC__A 0x420027
#define SIO_HI_RA_RAM_S1_CRC__W 16
#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF
......@@ -10924,7 +10685,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00
#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500
#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E
#define SIO_HI_RA_RAM_AB_TEMP__W 16
#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF
......@@ -10970,7 +10730,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072
#define SIO_HI_RA_RAM_VB_ENTRY1__W 16
#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF
......@@ -10985,7 +10744,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074
#define SIO_HI_RA_RAM_VB_ENTRY2__W 16
#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF
......@@ -11000,7 +10758,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076
#define SIO_HI_RA_RAM_VB_ENTRY3__W 16
#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF
......@@ -11015,7 +10772,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078
#define SIO_HI_RA_RAM_VB_ENTRY4__W 16
#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF
......@@ -11030,7 +10786,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A
#define SIO_HI_RA_RAM_VB_ENTRY5__W 16
#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF
......@@ -11045,7 +10800,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C
#define SIO_HI_RA_RAM_VB_ENTRY6__W 16
#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF
......@@ -11060,7 +10814,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0
#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E
#define SIO_HI_RA_RAM_VB_ENTRY7__W 16
#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF
......@@ -11075,8 +10828,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0
#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000
#define SIO_HI_IF_RAM_TRP_BPT_0__W 12
#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF
......@@ -11098,8 +10849,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF
#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0
#define SIO_HI_IF_COMM_EXEC__A 0x440000
#define SIO_HI_IF_COMM_EXEC__W 2
#define SIO_HI_IF_COMM_EXEC__M 0x3
......@@ -11109,7 +10858,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_IF_COMM_EXEC_HOLD 0x2
#define SIO_HI_IF_COMM_EXEC_STEP 0x3
#define SIO_HI_IF_COMM_STATE__A 0x440001
#define SIO_HI_IF_COMM_STATE__W 10
#define SIO_HI_IF_COMM_STATE__M 0x3FF
......@@ -11203,8 +10951,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_HI_IF_BPT_ADDR__M 0x3FF
#define SIO_HI_IF_BPT_ADDR__PRE 0x2
#define SIO_CC_COMM_EXEC__A 0x450000
#define SIO_CC_COMM_EXEC__W 2
#define SIO_CC_COMM_EXEC__M 0x3
......@@ -11240,7 +10986,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10
#define SIO_CC_PLL_MODE_BYPASS_ON 0x20
#define SIO_CC_PLL_TEST__A 0x450011
#define SIO_CC_PLL_TEST__W 8
#define SIO_CC_PLL_TEST__M 0xFF
......@@ -11299,15 +11044,12 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_CC_SOFT_RST_OSC__M 0x2
#define SIO_CC_SOFT_RST_OSC__PRE 0x0
#define SIO_CC_UPDATE__A 0x450017
#define SIO_CC_UPDATE__W 16
#define SIO_CC_UPDATE__M 0xFFFF
#define SIO_CC_UPDATE__PRE 0x0
#define SIO_CC_UPDATE_KEY 0xFABA
#define SIO_SA_COMM_EXEC__A 0x460000
#define SIO_SA_COMM_EXEC__W 2
#define SIO_SA_COMM_EXEC__M 0x3
......@@ -11486,8 +11228,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2
#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0
#define SIO_PDR_COMM_EXEC__A 0x7F0000
#define SIO_PDR_COMM_EXEC__W 2
#define SIO_PDR_COMM_EXEC__M 0x3
......@@ -12308,11 +12048,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3
#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0
#define VSB_COMM_EXEC__A 0x1C00000
#define VSB_COMM_EXEC__W 2
#define VSB_COMM_EXEC__M 0x3
......@@ -12321,7 +12056,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_COMM_EXEC_ACTIVE 0x1
#define VSB_COMM_EXEC_HOLD 0x2
#define VSB_COMM_MB__A 0x1C00002
#define VSB_COMM_MB__W 16
#define VSB_COMM_MB__M 0xFFFF
......@@ -12336,7 +12070,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x1
#define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x0
#define VSB_COMM_INT_STA__A 0x1C00005
#define VSB_COMM_INT_STA__W 16
#define VSB_COMM_INT_STA__M 0xFFFF
......@@ -12352,9 +12085,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_COMM_INT_STM__M 0xFFFF
#define VSB_COMM_INT_STM__PRE 0x0
#define VSB_TOP_COMM_EXEC__A 0x1C10000
#define VSB_TOP_COMM_EXEC__W 2
#define VSB_TOP_COMM_EXEC__M 0x3
......@@ -12401,7 +12131,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C0
#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x200
#define VSB_TOP_COMM_INT_REQ__A 0x1C10003
#define VSB_TOP_COMM_INT_REQ__W 1
#define VSB_TOP_COMM_INT_REQ__M 0x1
......@@ -12511,7 +12240,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x20
#define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x0
#define VSB_TOP_CKGN1ACQ__A 0x1C10010
#define VSB_TOP_CKGN1ACQ__W 8
#define VSB_TOP_CKGN1ACQ__M 0xFF
......@@ -12591,7 +12319,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x10
#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x0
#define VSB_TOP_MAINSMUP__A 0x1C1001B
#define VSB_TOP_MAINSMUP__W 8
#define VSB_TOP_MAINSMUP__M 0xFF
......@@ -12776,7 +12503,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x80
#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x0
#define VSB_TOP_TAPREADCYC__A 0x1C10025
#define VSB_TOP_TAPREADCYC__W 9
#define VSB_TOP_TAPREADCYC__M 0x1FF
......@@ -12826,7 +12552,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_LOCKSTATUS_DDMON__M 0x40
#define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x0
#define VSB_TOP_CTST__A 0x1C1002B
#define VSB_TOP_CTST__W 4
#define VSB_TOP_CTST__M 0xF
......@@ -13481,7 +13206,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x10
#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x10
#define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A
#define VSB_TOP_PREEQAGCPWRREFLVLHI__W 8
#define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF
......@@ -13536,7 +13260,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x100
#define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x100
#define VSB_TOP_LBAGCREFLVL__A 0x1C1003E
#define VSB_TOP_LBAGCREFLVL__W 12
#define VSB_TOP_LBAGCREFLVL__M 0xFFF
......@@ -13621,7 +13344,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x8
#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x8
#define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C
#define VSB_TOP_BEAGC_DEADZONEINIT__W 8
#define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF
......@@ -13647,7 +13369,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x4000
#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x0
#define VSB_TOP_BEAGC_SCALE__A 0x1C10050
#define VSB_TOP_BEAGC_SCALE__W 14
#define VSB_TOP_BEAGC_SCALE__M 0x3FFF
......@@ -13678,7 +13399,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x4000
#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x0
#define VSB_TOP_CFAGC_SCALE__A 0x1C10055
#define VSB_TOP_CFAGC_SCALE__W 14
#define VSB_TOP_CFAGC_SCALE__M 0x3FFF
......@@ -13768,7 +13488,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x40
#define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x0
#define VSB_TOP_CURRENTSEGLOCAT__A 0x1C10065
#define VSB_TOP_CURRENTSEGLOCAT__W 10
#define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF
......@@ -13863,7 +13582,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x40
#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x0
#define VSB_TOP_DLOCKACCUM__A 0x1C10071
#define VSB_TOP_DLOCKACCUM__W 16
#define VSB_TOP_DLOCKACCUM__M 0xFFFF
......@@ -13889,9 +13607,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TOP_DCRMVACUMQ__M 0x3FF
#define VSB_TOP_DCRMVACUMQ__PRE 0x0
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C20000
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF
......@@ -14611,8 +14326,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F00
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x0
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C30000
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF
......@@ -15213,7 +14926,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M 0x7F00
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE 0x0
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A 0x1C30028
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W 12
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M 0xFFF
......@@ -15323,8 +15035,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M 0x7F00
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE 0x0
#define VSB_TCMEQ_RAM__A 0x1C40000
#define VSB_TCMEQ_RAM_TCMEQ_RAM__B 0
......@@ -15332,8 +15042,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_TCMEQ_RAM_TCMEQ_RAM__M 0xFFFF
#define VSB_TCMEQ_RAM_TCMEQ_RAM__PRE 0x0
#define VSB_FCPRE_RAM__A 0x1C50000
#define VSB_FCPRE_RAM_FCPRE_RAM__B 0
......@@ -15341,8 +15049,6 @@ extern RegisterTableInfo_t drxj_map_info[];
#define VSB_FCPRE_RAM_FCPRE_RAM__M 0xFFFF
#define VSB_FCPRE_RAM_FCPRE_RAM__PRE 0x0
#define VSB_EQTAP_RAM__A 0x1C60000
#define VSB_EQTAP_RAM_EQTAP_RAM__B 0
......@@ -15353,5 +15059,4 @@ extern RegisterTableInfo_t drxj_map_info[];
#ifdef __cplusplus
}
#endif
#endif
drivers/media/dvb-frontends/drx39xyj/drxj_mc.h
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drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h
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drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h
View file @ 443f18d0
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drivers/media/dvb-frontends/drx39xyj/drxj_options.h
View file @ 443f18d0
......@@ -62,4 +62,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXJ_OPTIONS_H__ */
#endif /* __DRXJ_OPTIONS_H__ */
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