Commit 44a26c89 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'tegra-for-4.21-dt-bindings' of...

Merge tag 'tegra-for-4.21-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt

dt-bindings: Changes for v4.21-rc1

This contains a few cleanups of and additions to existing device tree
bindings, such as XUSB, EMC, PMC and thermal.

* tag 'tegra-for-4.21-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: tegra186-pmc: Add interrupt controller properties
  dt-bindings: thermal: tegra-bpmp: Add Tegra194 support
  dt: bindings: Move tegra20-emc binding to memory-controllers directory
  dt: bindings: tegra20-emc: Document clock property
  dt: bindings: tegra20-emc: Document interrupt property
  dt-bindings: usb: xhci-tegra: Add power-domain details
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c5a06e70 b4c7bf00
...@@ -15,6 +15,9 @@ Required properties: ...@@ -15,6 +15,9 @@ Required properties:
Optional properties: Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
Example: Example:
......
...@@ -10,6 +10,8 @@ Properties: ...@@ -10,6 +10,8 @@ Properties:
and chosen using the ramcode board selector. If omitted, only one and chosen using the ramcode board selector. If omitted, only one
set of tables can be present and said tables will be used set of tables can be present and said tables will be used
irrespective of ram-code configuration. irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
Child device nodes describe the memory settings for different configurations and clock rates. Child device nodes describe the memory settings for different configurations and clock rates.
...@@ -20,6 +22,8 @@ Example: ...@@ -20,6 +22,8 @@ Example:
#size-cells = < 0 >; #size-cells = < 0 >;
compatible = "nvidia,tegra20-emc"; compatible = "nvidia,tegra20-emc";
reg = <0x7000f4000 0x200>; reg = <0x7000f4000 0x200>;
interrupts = <0 78 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
} }
......
...@@ -15,7 +15,8 @@ Required properties: ...@@ -15,7 +15,8 @@ Required properties:
- compatible: - compatible:
Array of strings. Array of strings.
One of: One of:
- "nvidia,tegra186-bpmp-thermal". - "nvidia,tegra186-bpmp-thermal"
- "nvidia,tegra194-bpmp-thermal"
- #thermal-sensor-cells: Cell for sensor index. - #thermal-sensor-cells: Cell for sensor index.
Single-cell integer. Single-cell integer.
Must be <1>. Must be <1>.
......
...@@ -59,6 +59,14 @@ For Tegra210: ...@@ -59,6 +59,14 @@ For Tegra210:
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
- power-domains: A list of PM domain specifiers that reference each power-domain
used by the xHCI controller. This list must comprise of a specifier for the
XUSBA and XUSBC power-domains. See ../power/power_domain.txt and
../arm/tegra/nvidia,tegra20-pmc.txt for details.
- power-domain-names: A list of names that represent each of the specifiers in
the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which
represent the power-domains XUSBA and XUSBC, respectively. See
../power/power_domain.txt for details.
Optional properties: Optional properties:
-------------------- --------------------
......
/*
* This header provides constants for binding nvidia,tegra194-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2
#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3
#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4
#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5
#define TEGRA194_BPMP_THERMAL_ZONE_AO 6
#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7
#endif
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