Commit 47eefa46 authored by Linus Torvalds's avatar Linus Torvalds

MGA driver update to DRI CVS (3.0.2 -> 3.1.0). Add vblank interrupt,

DMA blit and getparam support.
parent bfef4707
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
gamma-objs := gamma_drv.o gamma_dma.o gamma-objs := gamma_drv.o gamma_dma.o
tdfx-objs := tdfx_drv.o tdfx-objs := tdfx_drv.o
r128-objs := r128_drv.o r128_cce.o r128_state.o r128_irq.o r128-objs := r128_drv.o r128_cce.o r128_state.o r128_irq.o
mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o
i810-objs := i810_drv.o i810_dma.o i810-objs := i810_drv.o i810_dma.o
i830-objs := i830_drv.o i830_dma.o i830-objs := i830_drv.o i830_dma.o
radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o
......
...@@ -45,11 +45,11 @@ ...@@ -45,11 +45,11 @@
#define DRIVER_NAME "mga" #define DRIVER_NAME "mga"
#define DRIVER_DESC "Matrox G200/G400" #define DRIVER_DESC "Matrox G200/G400"
#define DRIVER_DATE "20010321" #define DRIVER_DATE "20021029"
#define DRIVER_MAJOR 3 #define DRIVER_MAJOR 3
#define DRIVER_MINOR 0 #define DRIVER_MINOR 1
#define DRIVER_PATCHLEVEL 2 #define DRIVER_PATCHLEVEL 0
#define DRIVER_IOCTLS \ #define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma_buffers, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma_buffers, 1, 0 }, \
...@@ -61,7 +61,8 @@ ...@@ -61,7 +61,8 @@
[DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, [DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_MGA_GETPARAM)]= { mga_getparam, 1, 0 },
#define __HAVE_COUNTERS 3 #define __HAVE_COUNTERS 3
#define __HAVE_COUNTER6 _DRM_STAT_IRQ #define __HAVE_COUNTER6 _DRM_STAT_IRQ
...@@ -77,6 +78,9 @@ ...@@ -77,6 +78,9 @@
/* DMA customization: /* DMA customization:
*/ */
#define __HAVE_DMA 1 #define __HAVE_DMA 1
#define __HAVE_DMA_IRQ 1
#define __HAVE_VBL_IRQ 1
#define __HAVE_SHARED_IRQ 1
#define __HAVE_DMA_QUIESCENT 1 #define __HAVE_DMA_QUIESCENT 1
#define DRIVER_DMA_QUIESCENT() do { \ #define DRIVER_DMA_QUIESCENT() do { \
......
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
* Authors: * Authors:
* Rickard E. (Rik) Faith <faith@valinux.com> * Rickard E. (Rik) Faith <faith@valinux.com>
* Jeff Hartmann <jhartmann@valinux.com> * Jeff Hartmann <jhartmann@valinux.com>
* Keith Whitwell <keithw@valinux.com> * Keith Whitwell <keith@tungstengraphics.com>
* *
* Rewritten by: * Rewritten by:
* Gareth Hughes <gareth@valinux.com> * Gareth Hughes <gareth@valinux.com>
...@@ -166,7 +166,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv ) ...@@ -166,7 +166,7 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
if ( status == MGA_ENDPRDMASTS ) break; if ( status == MGA_ENDPRDMASTS ) break;
udelay( 1 ); DRM_UDELAY( 1 );
} }
if ( primary->tail == primary->last_flush ) { if ( primary->tail == primary->last_flush ) {
......
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
* *
* Authors: * Authors:
* Jeff Hartmann <jhartmann@valinux.com> * Jeff Hartmann <jhartmann@valinux.com>
* Keith Whitwell <keithw@valinux.com> * Keith Whitwell <keith@tungstengraphics.com>
* *
* Rewritten by: * Rewritten by:
* Gareth Hughes <gareth@valinux.com> * Gareth Hughes <gareth@valinux.com>
...@@ -239,6 +239,7 @@ typedef struct _drm_mga_sarea { ...@@ -239,6 +239,7 @@ typedef struct _drm_mga_sarea {
#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) #define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) #define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(0x49, drm_mga_getparam_t)
typedef struct _drm_mga_warp_index { typedef struct _drm_mga_warp_index {
int installed; int installed;
...@@ -322,4 +323,14 @@ typedef struct _drm_mga_blit { ...@@ -322,4 +323,14 @@ typedef struct _drm_mga_blit {
int source_pitch, dest_pitch; int source_pitch, dest_pitch;
} drm_mga_blit_t; } drm_mga_blit_t;
/* 3.1: An ioctl to get parameters that aren't available to the 3d
* client any other way.
*/
#define MGA_PARAM_IRQ_NR 1
typedef struct drm_mga_getparam {
int param;
int *value;
} drm_mga_getparam_t;
#endif #endif
...@@ -125,6 +125,7 @@ extern int mga_dma_vertex( DRM_IOCTL_ARGS ); ...@@ -125,6 +125,7 @@ extern int mga_dma_vertex( DRM_IOCTL_ARGS );
extern int mga_dma_indices( DRM_IOCTL_ARGS ); extern int mga_dma_indices( DRM_IOCTL_ARGS );
extern int mga_dma_iload( DRM_IOCTL_ARGS ); extern int mga_dma_iload( DRM_IOCTL_ARGS );
extern int mga_dma_blit( DRM_IOCTL_ARGS ); extern int mga_dma_blit( DRM_IOCTL_ARGS );
extern int mga_getparam( DRM_IOCTL_ARGS );
/* mga_warp.c */ /* mga_warp.c */
extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
...@@ -141,6 +142,7 @@ extern int mga_warp_init( drm_mga_private_t *dev_priv ); ...@@ -141,6 +142,7 @@ extern int mga_warp_init( drm_mga_private_t *dev_priv );
#ifdef __alpha__ #ifdef __alpha__
#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
...@@ -152,6 +154,7 @@ static inline u32 _MGA_READ(u32 *addr) ...@@ -152,6 +154,7 @@ static inline u32 _MGA_READ(u32 *addr)
#else #else
#define MGA_READ( reg ) MGA_DEREF( reg ) #define MGA_READ( reg ) MGA_DEREF( reg )
#define MGA_READ8( reg ) MGA_DEREF8( reg )
#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0) #define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0)
#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0) #define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0)
#endif #endif
...@@ -345,6 +348,11 @@ do { \ ...@@ -345,6 +348,11 @@ do { \
/* A reduced set of the mga registers. /* A reduced set of the mga registers.
*/ */
#define MGA_CRTC_INDEX 0x1fd4 #define MGA_CRTC_INDEX 0x1fd4
#define MGA_CRTC_DATA 0x1fd5
/* CRTC11 */
#define MGA_VINTCLR (1 << 4)
#define MGA_VINTEN (1 << 5)
#define MGA_ALPHACTRL 0x2c7c #define MGA_ALPHACTRL 0x2c7c
#define MGA_AR0 0x1c60 #define MGA_AR0 0x1c60
...@@ -416,8 +424,10 @@ do { \ ...@@ -416,8 +424,10 @@ do { \
#define MGA_ICLEAR 0x1e18 #define MGA_ICLEAR 0x1e18
# define MGA_SOFTRAPICLR (1 << 0) # define MGA_SOFTRAPICLR (1 << 0)
# define MGA_VLINEICLR (1 << 5)
#define MGA_IEN 0x1e1c #define MGA_IEN 0x1e1c
# define MGA_SOFTRAPIEN (1 << 0) # define MGA_SOFTRAPIEN (1 << 0)
# define MGA_VLINEIEN (1 << 5)
#define MGA_LEN 0x1c5c #define MGA_LEN 0x1c5c
...@@ -456,6 +466,8 @@ do { \ ...@@ -456,6 +466,8 @@ do { \
# define MGA_SRCACC_AGP (1 << 1) # define MGA_SRCACC_AGP (1 << 1)
#define MGA_STATUS 0x1e14 #define MGA_STATUS 0x1e14
# define MGA_SOFTRAPEN (1 << 0) # define MGA_SOFTRAPEN (1 << 0)
# define MGA_VSYNCPEN (1 << 4)
# define MGA_VLINEPEN (1 << 5)
# define MGA_DWGENGSTS (1 << 16) # define MGA_DWGENGSTS (1 << 16)
# define MGA_ENDPRDMASTS (1 << 17) # define MGA_ENDPRDMASTS (1 << 17)
#define MGA_STENCIL 0x2cc8 #define MGA_STENCIL 0x2cc8
......
/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
*
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
*
* The Weather Channel (TM) funded Tungsten Graphics to develop the
* initial release of the Radeon 8500 driver under the XFree86 license.
* This notice must be preserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
* Eric Anholt <anholt@FreeBSD.org>
*/
#include "mga.h"
#include "drmP.h"
#include "drm.h"
#include "mga_drm.h"
#include "mga_drv.h"
void mga_dma_service( DRM_IRQ_ARGS )
{
drm_device_t *dev = (drm_device_t *) arg;
drm_mga_private_t *dev_priv =
(drm_mga_private_t *)dev->dev_private;
int status;
status = MGA_READ( MGA_STATUS );
/* VBLANK interrupt */
if ( status & MGA_VLINEPEN ) {
MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR );
atomic_inc(&dev->vbl_received);
DRM_WAKEUP(&dev->vbl_queue);
}
}
int mga_vblank_wait(drm_device_t *dev, unsigned int *sequence)
{
unsigned int cur_vblank;
int ret = 0;
/* Assume that the user has missed the current sequence number
* by about a day rather than she wants to wait for years
* using vertical blanks...
*/
DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
+ ~*sequence + 1 ) <= (1<<23) ) );
*sequence = cur_vblank;
return ret;
}
void mga_driver_irq_preinstall( drm_device_t *dev ) {
drm_mga_private_t *dev_priv =
(drm_mga_private_t *)dev->dev_private;
/* Disable *all* interrupts */
MGA_WRITE( MGA_IEN, 0 );
/* Clear bits if they're already high */
MGA_WRITE( MGA_ICLEAR, ~0 );
}
void mga_driver_irq_postinstall( drm_device_t *dev ) {
drm_mga_private_t *dev_priv =
(drm_mga_private_t *)dev->dev_private;
/* Turn on VBL interrupt */
MGA_WRITE( MGA_IEN, MGA_VLINEIEN );
}
void mga_driver_irq_uninstall( drm_device_t *dev ) {
drm_mga_private_t *dev_priv =
(drm_mga_private_t *)dev->dev_private;
if ( dev_priv ) {
/* Disable *all* interrupts */
MGA_WRITE( MGA_IEN, 0 );
}
}
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
* *
* Authors: * Authors:
* Jeff Hartmann <jhartmann@valinux.com> * Jeff Hartmann <jhartmann@valinux.com>
* Keith Whitwell <keithw@valinux.com> * Keith Whitwell <keith@tungstengraphics.com>
* *
* Rewritten by: * Rewritten by:
* Gareth Hughes <gareth@valinux.com> * Gareth Hughes <gareth@valinux.com>
...@@ -1075,3 +1075,36 @@ int mga_dma_blit( DRM_IOCTL_ARGS ) ...@@ -1075,3 +1075,36 @@ int mga_dma_blit( DRM_IOCTL_ARGS )
return 0; return 0;
} }
int mga_getparam( DRM_IOCTL_ARGS )
{
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_getparam_t param;
int value;
if ( !dev_priv ) {
DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
return DRM_ERR(EINVAL);
}
DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t *)data,
sizeof(param) );
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
switch( param.param ) {
case MGA_PARAM_IRQ_NR:
value = dev->irq;
break;
default:
return DRM_ERR(EINVAL);
}
if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
DRM_ERROR( "copy_to_user\n" );
return DRM_ERR(EFAULT);
}
return 0;
}
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