Skip to content

L
linux
Commit 48936a08 authored by Haiying Wang's avatar Haiying Wang Committed by Kumar Gala
Browse files
Options

powerpc/85xx: Add P1021MDS board support 

P1021 is a dual e500v2 core based SOC with:
* 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board)
* 2 PCIe Controller
* 1 USB2.0 controller
* eSDHC, eSPI, I2C, DUART
* eLBC (NAND, BCSR, PMC0/1)
* Security Engine (SEC 3.3.2)
* Quicc Engine (QE)
Signed-off-by: default avatarHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: default avatarYu Liu <Yu.Liu@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 710e3383
Show whitespace changes
Inline Side-by-side
Showing with 797 additions and 3 deletions
arch/powerpc/boot/dts/p1021mds.dts 0 → 100644
View file @ 48936a08
/*
* P1021 MDS Device Tree Source
*
* Copyright 2010 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,P1021";
compatible = "fsl,P1021MDS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &serial0;
serial1 = &serial1;
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
ethernet4 = &enet4;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1021@0 {
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
PowerPC,P1021@1 {
device_type = "cpu";
reg = <0x1>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
localbus@ffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
reg = <0 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
/* NAND Flash, BCSR, PMC0/1*/
ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
0x1 0x0 0x0 0xf8000000 0x00008000
0x2 0x0 0x0 0xf8010000 0x00020000
0x3 0x0 0x0 0xf8020000 0x00020000>;
nand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1021-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x0 0x0 0x40000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND (RO) U-Boot Image";
read-only;
};
partition@100000 {
/* 1MB for DTB Image */
reg = <0x00100000 0x00100000>;
label = "NAND (RO) DTB Image";
read-only;
};
partition@200000 {
/* 4MB for Linux Kernel Image */
reg = <0x00200000 0x00400000>;
label = "NAND (RO) Linux Kernel Image";
read-only;
};
partition@600000 {
/* 5MB for Compressed Root file System Image */
reg = <0x00600000 0x00500000>;
label = "NAND (RO) Compressed RFS Image";
read-only;
};
partition@b00000 {
/* 6MB for JFFS2 based Root file System */
reg = <0x00a00000 0x00600000>;
label = "NAND (RW) JFFS2 Root File System";
};
partition@1100000 {
/* 14MB for JFFS2 based Root file System */
reg = <0x01100000 0x00e00000>;
label = "NAND (RW) Writable User area";
};
partition@1f00000 {
/* 1MB for microcode */
reg = <0x01f00000 0x00100000>;
label = "NAND (RO) QE Ucode";
read-only;
};
};
bcsr@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1021mds-bcsr";
reg = <1 0 0x8000>;
ranges = <0 1 0 0x8000>;
};
pib@2,0 {
compatible = "fsl,p1021mds-pib";
reg = <2 0 0x10000>;
};
pib@3,0 {
compatible = "fsl,p1021mds-pib";
reg = <3 0 0x10000>;
};
};
soc@ffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1021-immr", "simple-bus";
ranges = <0x0 0x0 0xffe00000 0x100000>;
bus-frequency = <0>; // Filled out by uboot.
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,p1021-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <16 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,p1021-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
spi@7000 {
cell-index = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,espi";
reg = <0x7000 0x1000>;
interrupts = <59 0x2>;
interrupt-parent = <&mpic>;
espi,num-ss-bits = <4>;
mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,espi-flash";
reg = <0>;
linux,modalias = "fsl_m25p80";
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
label = "u-boot-spi";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@kernel {
label = "kernel-spi";
reg = <0x00100000 0x00500000>;
read-only;
};
partition@dtb {
label = "dtb-spi";
reg = <0x00600000 0x00100000>;
read-only;
};
partition@fs {
label = "file system-spi";
reg = <0x00700000 0x00900000>;
};
};
};
gpio: gpio-controller@f000 {
#gpio-cells = <2>;
compatible = "fsl,mpc8572-gpio";
reg = <0xf000 0x100>;
interrupts = <47 0x2>;
interrupt-parent = <&mpic>;
gpio-controller;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,p1021-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x40000>; // L2,256K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-usb2-dr";
reg = <0x22000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <28 0x2>;
phy_type = "ulpi";
};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <1 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x1>;
};
phy4: ethernet-phy@4 {
interrupt-parent = <&mpic>;
reg = <0x4>;
};
};
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@B0000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
};
};
enet1: ethernet@B1000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy4>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
};
};
enet2: ethernet@B2000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
queue-group@0{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB2000 0x1000>;
interrupts = <31 2 32 2 33 2>;
};
queue-group@1{
#address-cells = <1>;
#size-cells = <1>;
reg = <0xB6000 0x1000>;
interrupts = <25 2 26 2 27 2>;
};
};
sdhci@2e000 {
compatible = "fsl,p1021-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
crypto@30000 {
compatible = "fsl,sec3.3", "fsl,sec3.1",
"fsl,sec3.0", "fsl,sec2.4",
"fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3a30abf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
msi@41600 {
compatible = "fsl,p1021-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,p1021-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
par_io@e0100 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xe0100 0x60>;
ranges = <0x0 0xe0100 0x60>;
device_type = "par_io";
num-ports = <3>;
pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9
*/
0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
};
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
};
};
};
pci0: pcie@ffe09000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
pci1: pcie@ffe0a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <16 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
};
};
qe@ffe80000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0x0 0xffe80000 0x40000>;
reg = <0 0xffe80000 0 0x480>;
brg-frequency = <0>;
bus-frequency = <0>;
fsl,qe-num-riscs = <1>;
fsl,qe-num-snums = <28>;
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
interrupts = <63 2 60 2>; //high:47 low:44
interrupt-parent = <&mpic>;
};
enet3: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk12";
tx-clock-name = "clk9";
pio-handle = <&pio1>;
phy-handle = <&qe_phy0>;
phy-connection-type = "mii";
};
mdio@2120 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
qe_phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <4 1>;
reg = <0x0>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@03 {
interrupt-parent = <&mpic>;
interrupts = <5 1>;
reg = <0x3>;
device_type = "ethernet-phy";
};
tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet4: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <5>;
reg = <0x2400 0x200>;
interrupts = <40>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk13";
pio-handle = <&pio2>;
phy-handle = <&qe_phy1>;
phy-connection-type = "rmii";
};
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x10000 0x6000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x6000>;
};
};
};
};
arch/powerpc/platforms/85xx/mpc85xx_mds.c
View file @ 48936a08
/* /*
* Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
* *
* Author: Andy Fleming <afleming@freescale.com> * Author: Andy Fleming <afleming@freescale.com>
* *
...@@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev) ...@@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
* Setup the architecture * Setup the architecture
* *
*/ */
#ifdef CONFIG_SMP
extern void __init mpc85xx_smp_init(void);
#endif
static void __init mpc85xx_mds_setup_arch(void) static void __init mpc85xx_mds_setup_arch(void)
{ {
struct device_node *np; struct device_node *np;
...@@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void) ...@@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void)
} }
#endif #endif
#ifdef CONFIG_SMP
mpc85xx_smp_init();
#endif
#ifdef CONFIG_QUICC_ENGINE #ifdef CONFIG_QUICC_ENGINE
np = of_find_compatible_node(NULL, NULL, "fsl,qe"); np = of_find_compatible_node(NULL, NULL, "fsl,qe");
if (!np) { if (!np) {
...@@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void) ...@@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void)
BCSR_UCC_RGMII, BCSR_UCC_RTBI); BCSR_UCC_RGMII, BCSR_UCC_RTBI);
} }
} else if (machine_is(p1021_mds)) {
#define BCSR11_ENET_MICRST (0x1 << 5)
/* Reset Micrel PHY */
clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
} }
iounmap(bcsr_regs); iounmap(bcsr_regs);
} }
if (machine_is(p1021_mds)) {
#define MPC85xx_PMUXCR_OFFSET 0x60
#define MPC85xx_PMUXCR_QE0 0x00008000
#define MPC85xx_PMUXCR_QE3 0x00001000
#define MPC85xx_PMUXCR_QE9 0x00000040
#define MPC85xx_PMUXCR_QE12 0x00000008
static __be32 __iomem *pmuxcr;
np = of_find_node_by_name(NULL, "global-utilities");
if (np) {
pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
if (!pmuxcr)
printk(KERN_EMERG "Error: Alternate function"
" signal multiplex control register not"
" mapped!\n");
else
/* P1021 has pins muxed for QE and other functions. To
* enable QE UEC mode, we need to set bit QE0 for UCC1
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
* and QE12 for QE MII management singals in PMUXCR
* register.
*/
setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
MPC85xx_PMUXCR_QE3 |
MPC85xx_PMUXCR_QE9 |
MPC85xx_PMUXCR_QE12);
of_node_put(np);
}
}
#endif /* CONFIG_QUICC_ENGINE */ #endif /* CONFIG_QUICC_ENGINE */
#ifdef CONFIG_SWIOTLB #ifdef CONFIG_SWIOTLB
...@@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = { ...@@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = {
{}, {},
}; };
static struct of_device_id p1021_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
{ .compatible = "simple-bus", },
{ .type = "qe", },
{ .compatible = "fsl,qe", },
{ .compatible = "gianfar", },
{},
};
static int __init mpc85xx_publish_devices(void) static int __init mpc85xx_publish_devices(void)
{ {
if (machine_is(mpc8568_mds)) if (machine_is(mpc8568_mds))
...@@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void) ...@@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void)
return 0; return 0;
} }
static int __init p1021_publish_devices(void)
{
/* Publish the QE devices */
of_platform_bus_probe(NULL, p1021_ids, NULL);
return 0;
}
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
machine_device_initcall(p1021_mds, p1021_publish_devices);
machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier); machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier); machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
static void __init mpc85xx_mds_pic_init(void) static void __init mpc85xx_mds_pic_init(void)
{ {
...@@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void) ...@@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void)
mpic = mpic_alloc(np, r.start, mpic = mpic_alloc(np, r.start,
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
MPIC_BROKEN_FRR_NIRQS, MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC "); 0, 256, " OpenPIC ");
BUG_ON(mpic == NULL); BUG_ON(mpic == NULL);
of_node_put(np); of_node_put(np);
...@@ -380,6 +449,10 @@ static void __init mpc85xx_mds_pic_init(void) ...@@ -380,6 +449,10 @@ static void __init mpc85xx_mds_pic_init(void)
if (!np) if (!np)
return; return;
} }
if (machine_is(p1021_mds))
qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
qe_ic_cascade_high_mpic);
else
qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL); qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
of_node_put(np); of_node_put(np);
#endif /* CONFIG_QUICC_ENGINE */ #endif /* CONFIG_QUICC_ENGINE */
...@@ -426,3 +499,26 @@ define_machine(mpc8569_mds) { ...@@ -426,3 +499,26 @@ define_machine(mpc8569_mds) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus, .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif #endif
}; };
static int __init p1021_mds_probe(void)
{
unsigned long root = of_get_flat_dt_root();
return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
}
define_machine(p1021_mds) {
.name = "P1021 MDS",
.probe = p1021_mds_probe,
.setup_arch = mpc85xx_mds_setup_arch,
.init_IRQ = mpc85xx_mds_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
};
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7