Commit 4a079643 authored by Neil Armstrong's avatar Neil Armstrong Committed by Jerome Brunet

clk: meson: g12a: fix cpu clock rate setting

CLK_SET_RATE_NO_REPARENT is wrongly set on the g12a cpu premux0 clocks
flags, and CLK_SET_RATE_PARENT is required for the g12a cpu premux0 clock
and the g12b cpub premux0 clock, otherwise CCF always selects the SYS_PLL
clock to feed the cpu cluster.

Fixes: ffae8475 ("clk: meson: g12a: add notifiers to handle cpu clock change")
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 44b09b11
...@@ -353,8 +353,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { ...@@ -353,8 +353,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
{ .hw = &g12a_fclk_div3.hw }, { .hw = &g12a_fclk_div3.hw },
}, },
.num_parents = 3, .num_parents = 3,
/* This sub-tree is used a parking clock */ .flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_NO_REPARENT,
}, },
}; };
...@@ -533,6 +532,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { ...@@ -533,6 +532,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
{ .hw = &g12a_fclk_div3.hw }, { .hw = &g12a_fclk_div3.hw },
}, },
.num_parents = 3, .num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
}, },
}; };
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment