Commit 4a79ce74 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next

Georgi writes:

interconnect patches for 5.4

Here are the interconnect driver updates for the 5.4-rc1 merge window.

- New feature is the path tagging support that helps with grouping and
aggregating the bandwidth requests into separate buckets based on a tag.
- The first user of the path tagging is the Qualcomm sdm845 driver that
now implements support for wake/sleep sets. This allows consumer drivers
to express their bandwidth needs for the different CPU power states.
- New interconnect driver for the qcs404 platforms and a driver that
communicates bandwidth requests with remote processor over shared memory.
- Cleanups and fixes.
Signed-off-by: default avatarGeorgi Djakov <georgi.djakov@linaro.org>

* tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux:
  drivers: qcom: Add BCM vote macro to header
  interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404
  interconnect: qcom: Add QCS404 interconnect provider driver
  interconnect: qcom: Add interconnect RPM over SMD driver
  dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
  interconnect: qcom: Add tagging and wake/sleep support for sdm845
  interconnect: Add pre_aggregate() callback
  interconnect: Add support for path tags
parents 77fda29f 6311b652
Qualcomm QCS404 Network-On-Chip interconnect driver binding
-----------------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,qcs404-bimc"
"qcom,qcs404-pcnoc"
"qcom,qcs404-snoc"
- #interconnect-cells : should contain 1
reg : specifies the physical base address and size of registers
clocks : list of phandles and specifiers to all interconnect bus clocks
clock-names : clock names should include both "bus" and "bus_a"
Example:
soc {
...
bimc: interconnect@400000 {
reg = <0x00400000 0x80000>;
compatible = "qcom,qcs404-bimc";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
pnoc: interconnect@500000 {
reg = <0x00500000 0x15080>;
compatible = "qcom,qcs404-pcnoc";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
<&rpmcc RPM_SMD_PNOC_A_CLK>;
};
snoc: interconnect@580000 {
reg = <0x00580000 0x23080>;
compatible = "qcom,qcs404-snoc";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
};
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Copyright (c) 2018, The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/ */
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
...@@ -12,23 +12,13 @@ ...@@ -12,23 +12,13 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <soc/qcom/cmd-db.h> #include <soc/qcom/cmd-db.h>
#include <soc/qcom/rpmh.h> #include <soc/qcom/rpmh.h>
#include <soc/qcom/tcs.h>
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#define CLK_RPMH_ARC_EN_OFFSET 0 #define CLK_RPMH_ARC_EN_OFFSET 0
#define CLK_RPMH_VRM_EN_OFFSET 4 #define CLK_RPMH_VRM_EN_OFFSET 4
#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
#define BCM_TCS_CMD_VALID_SHIFT 29
#define BCM_TCS_CMD_VOTE_MASK 0x3fff
#define BCM_TCS_CMD_VOTE_SHIFT 0
#define BCM_TCS_CMD(valid, vote) \
(BCM_TCS_CMD_COMMIT_MASK | \
((valid) << BCM_TCS_CMD_VALID_SHIFT) | \
((vote & BCM_TCS_CMD_VOTE_MASK) \
<< BCM_TCS_CMD_VOTE_SHIFT))
/** /**
* struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
* @unit: divisor used to convert Hz value to an RPMh msg * @unit: divisor used to convert Hz value to an RPMh msg
...@@ -269,7 +259,7 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) ...@@ -269,7 +259,7 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
} }
cmd.addr = c->res_addr; cmd.addr = c->res_addr;
cmd.data = BCM_TCS_CMD(enable, cmd_state); cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1); ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
if (ret) { if (ret) {
......
...@@ -29,6 +29,7 @@ static struct dentry *icc_debugfs_dir; ...@@ -29,6 +29,7 @@ static struct dentry *icc_debugfs_dir;
* @req_node: entry in list of requests for the particular @node * @req_node: entry in list of requests for the particular @node
* @node: the interconnect node to which this constraint applies * @node: the interconnect node to which this constraint applies
* @dev: reference to the device that sets the constraints * @dev: reference to the device that sets the constraints
* @tag: path tag (optional)
* @avg_bw: an integer describing the average bandwidth in kBps * @avg_bw: an integer describing the average bandwidth in kBps
* @peak_bw: an integer describing the peak bandwidth in kBps * @peak_bw: an integer describing the peak bandwidth in kBps
*/ */
...@@ -36,6 +37,7 @@ struct icc_req { ...@@ -36,6 +37,7 @@ struct icc_req {
struct hlist_node req_node; struct hlist_node req_node;
struct icc_node *node; struct icc_node *node;
struct device *dev; struct device *dev;
u32 tag;
u32 avg_bw; u32 avg_bw;
u32 peak_bw; u32 peak_bw;
}; };
...@@ -203,8 +205,11 @@ static int aggregate_requests(struct icc_node *node) ...@@ -203,8 +205,11 @@ static int aggregate_requests(struct icc_node *node)
node->avg_bw = 0; node->avg_bw = 0;
node->peak_bw = 0; node->peak_bw = 0;
if (p->pre_aggregate)
p->pre_aggregate(node);
hlist_for_each_entry(r, &node->req_list, req_node) hlist_for_each_entry(r, &node->req_list, req_node)
p->aggregate(node, r->avg_bw, r->peak_bw, p->aggregate(node, r->tag, r->avg_bw, r->peak_bw,
&node->avg_bw, &node->peak_bw); &node->avg_bw, &node->peak_bw);
return 0; return 0;
...@@ -385,6 +390,26 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) ...@@ -385,6 +390,26 @@ struct icc_path *of_icc_get(struct device *dev, const char *name)
} }
EXPORT_SYMBOL_GPL(of_icc_get); EXPORT_SYMBOL_GPL(of_icc_get);
/**
* icc_set_tag() - set an optional tag on a path
* @path: the path we want to tag
* @tag: the tag value
*
* This function allows consumers to append a tag to the requests associated
* with a path, so that a different aggregation could be done based on this tag.
*/
void icc_set_tag(struct icc_path *path, u32 tag)
{
int i;
if (!path)
return;
for (i = 0; i < path->num_nodes; i++)
path->reqs[i].tag = tag;
}
EXPORT_SYMBOL_GPL(icc_set_tag);
/** /**
* icc_set_bw() - set bandwidth constraints on an interconnect path * icc_set_bw() - set bandwidth constraints on an interconnect path
* @path: reference to the path returned by icc_get() * @path: reference to the path returned by icc_get()
......
...@@ -5,6 +5,15 @@ config INTERCONNECT_QCOM ...@@ -5,6 +5,15 @@ config INTERCONNECT_QCOM
help help
Support for Qualcomm's Network-on-Chip interconnect hardware. Support for Qualcomm's Network-on-Chip interconnect hardware.
config INTERCONNECT_QCOM_QCS404
tristate "Qualcomm QCS404 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on qcs404-based
platforms.
config INTERCONNECT_QCOM_SDM845 config INTERCONNECT_QCOM_SDM845
tristate "Qualcomm SDM845 interconnect driver" tristate "Qualcomm SDM845 interconnect driver"
depends on INTERCONNECT_QCOM depends on INTERCONNECT_QCOM
...@@ -12,3 +21,6 @@ config INTERCONNECT_QCOM_SDM845 ...@@ -12,3 +21,6 @@ config INTERCONNECT_QCOM_SDM845
help help
This is a driver for the Qualcomm Network-on-Chip on sdm845-based This is a driver for the Qualcomm Network-on-Chip on sdm845-based
platforms. platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
qnoc-qcs404-objs := qcs404.o
qnoc-sdm845-objs := sdm845.o qnoc-sdm845-objs := sdm845.o
icc-smd-rpm-objs := smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Copyright (c) 2018, The Linux Foundation. All rights reserved. * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* *
*/ */
...@@ -20,23 +20,6 @@ ...@@ -20,23 +20,6 @@
#include <soc/qcom/rpmh.h> #include <soc/qcom/rpmh.h>
#include <soc/qcom/tcs.h> #include <soc/qcom/tcs.h>
#define BCM_TCS_CMD_COMMIT_SHFT 30
#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
#define BCM_TCS_CMD_VALID_SHFT 29
#define BCM_TCS_CMD_VALID_MASK 0x20000000
#define BCM_TCS_CMD_VOTE_X_SHFT 14
#define BCM_TCS_CMD_VOTE_MASK 0x3fff
#define BCM_TCS_CMD_VOTE_Y_SHFT 0
#define BCM_TCS_CMD_VOTE_Y_MASK 0xfffc000
#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
(((commit) << BCM_TCS_CMD_COMMIT_SHFT) | \
((valid) << BCM_TCS_CMD_VALID_SHFT) | \
((cpu_to_le32(vote_x) & \
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \
((cpu_to_le32(vote_y) & \
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT))
#define to_qcom_provider(_provider) \ #define to_qcom_provider(_provider) \
container_of(_provider, struct qcom_icc_provider, provider) container_of(_provider, struct qcom_icc_provider, provider)
...@@ -66,6 +49,22 @@ struct bcm_db { ...@@ -66,6 +49,22 @@ struct bcm_db {
#define SDM845_MAX_BCM_PER_NODE 2 #define SDM845_MAX_BCM_PER_NODE 2
#define SDM845_MAX_VCD 10 #define SDM845_MAX_VCD 10
/*
* The AMC bucket denotes constraints that are applied to hardware when
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
* when the execution environment transitions between active and low power mode.
*/
#define QCOM_ICC_BUCKET_AMC 0
#define QCOM_ICC_BUCKET_WAKE 1
#define QCOM_ICC_BUCKET_SLEEP 2
#define QCOM_ICC_NUM_BUCKETS 3
#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC)
#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE)
#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP)
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
QCOM_ICC_TAG_SLEEP)
/** /**
* struct qcom_icc_node - Qualcomm specific interconnect nodes * struct qcom_icc_node - Qualcomm specific interconnect nodes
* @name: the node name used in debugfs * @name: the node name used in debugfs
...@@ -86,8 +85,8 @@ struct qcom_icc_node { ...@@ -86,8 +85,8 @@ struct qcom_icc_node {
u16 num_links; u16 num_links;
u16 channels; u16 channels;
u16 buswidth; u16 buswidth;
u64 sum_avg; u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
u64 max_peak; u64 max_peak[QCOM_ICC_NUM_BUCKETS];
struct qcom_icc_bcm *bcms[SDM845_MAX_BCM_PER_NODE]; struct qcom_icc_bcm *bcms[SDM845_MAX_BCM_PER_NODE];
size_t num_bcms; size_t num_bcms;
}; };
...@@ -112,8 +111,8 @@ struct qcom_icc_bcm { ...@@ -112,8 +111,8 @@ struct qcom_icc_bcm {
const char *name; const char *name;
u32 type; u32 type;
u32 addr; u32 addr;
u64 vote_x; u64 vote_x[QCOM_ICC_NUM_BUCKETS];
u64 vote_y; u64 vote_y[QCOM_ICC_NUM_BUCKETS];
bool dirty; bool dirty;
bool keepalive; bool keepalive;
struct bcm_db aux_data; struct bcm_db aux_data;
...@@ -555,7 +554,7 @@ inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y, ...@@ -555,7 +554,7 @@ inline void tcs_cmd_gen(struct tcs_cmd *cmd, u64 vote_x, u64 vote_y,
cmd->wait = true; cmd->wait = true;
} }
static void tcs_list_gen(struct list_head *bcm_list, static void tcs_list_gen(struct list_head *bcm_list, int bucket,
struct tcs_cmd tcs_list[SDM845_MAX_VCD], struct tcs_cmd tcs_list[SDM845_MAX_VCD],
int n[SDM845_MAX_VCD]) int n[SDM845_MAX_VCD])
{ {
...@@ -573,8 +572,8 @@ static void tcs_list_gen(struct list_head *bcm_list, ...@@ -573,8 +572,8 @@ static void tcs_list_gen(struct list_head *bcm_list,
commit = true; commit = true;
cur_vcd_size = 0; cur_vcd_size = 0;
} }
tcs_cmd_gen(&tcs_list[idx], bcm->vote_x, bcm->vote_y, tcs_cmd_gen(&tcs_list[idx], bcm->vote_x[bucket],
bcm->addr, commit); bcm->vote_y[bucket], bcm->addr, commit);
idx++; idx++;
n[batch]++; n[batch]++;
/* /*
...@@ -595,38 +594,56 @@ static void tcs_list_gen(struct list_head *bcm_list, ...@@ -595,38 +594,56 @@ static void tcs_list_gen(struct list_head *bcm_list,
static void bcm_aggregate(struct qcom_icc_bcm *bcm) static void bcm_aggregate(struct qcom_icc_bcm *bcm)
{ {
size_t i; size_t i, bucket;
u64 agg_avg = 0; u64 agg_avg[QCOM_ICC_NUM_BUCKETS] = {0};
u64 agg_peak = 0; u64 agg_peak[QCOM_ICC_NUM_BUCKETS] = {0};
u64 temp; u64 temp;
for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) {
for (i = 0; i < bcm->num_nodes; i++) { for (i = 0; i < bcm->num_nodes; i++) {
temp = bcm->nodes[i]->sum_avg * bcm->aux_data.width; temp = bcm->nodes[i]->sum_avg[bucket] * bcm->aux_data.width;
do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels); do_div(temp, bcm->nodes[i]->buswidth * bcm->nodes[i]->channels);
agg_avg = max(agg_avg, temp); agg_avg[bucket] = max(agg_avg[bucket], temp);
temp = bcm->nodes[i]->max_peak * bcm->aux_data.width; temp = bcm->nodes[i]->max_peak[bucket] * bcm->aux_data.width;
do_div(temp, bcm->nodes[i]->buswidth); do_div(temp, bcm->nodes[i]->buswidth);
agg_peak = max(agg_peak, temp); agg_peak[bucket] = max(agg_peak[bucket], temp);
} }
temp = agg_avg * 1000ULL; temp = agg_avg[bucket] * 1000ULL;
do_div(temp, bcm->aux_data.unit); do_div(temp, bcm->aux_data.unit);
bcm->vote_x = temp; bcm->vote_x[bucket] = temp;
temp = agg_peak * 1000ULL; temp = agg_peak[bucket] * 1000ULL;
do_div(temp, bcm->aux_data.unit); do_div(temp, bcm->aux_data.unit);
bcm->vote_y = temp; bcm->vote_y[bucket] = temp;
}
if (bcm->keepalive && bcm->vote_x == 0 && bcm->vote_y == 0) { if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
bcm->vote_x = 1; bcm->vote_y[QCOM_ICC_BUCKET_AMC] == 0) {
bcm->vote_y = 1; bcm->vote_x[QCOM_ICC_BUCKET_AMC] = 1;
bcm->vote_x[QCOM_ICC_BUCKET_WAKE] = 1;
bcm->vote_y[QCOM_ICC_BUCKET_AMC] = 1;
bcm->vote_y[QCOM_ICC_BUCKET_WAKE] = 1;
} }
bcm->dirty = false; bcm->dirty = false;
} }
static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw, static void qcom_icc_pre_aggregate(struct icc_node *node)
{
size_t i;
struct qcom_icc_node *qn;
qn = node->data;
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
qn->sum_avg[i] = 0;
qn->max_peak[i] = 0;
}
}
static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak) u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
{ {
size_t i; size_t i;
...@@ -634,12 +651,19 @@ static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw, ...@@ -634,12 +651,19 @@ static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw,
qn = node->data; qn = node->data;
if (!tag)
tag = QCOM_ICC_TAG_ALWAYS;
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
if (tag & BIT(i)) {
qn->sum_avg[i] += avg_bw;
qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw);
}
}
*agg_avg += avg_bw; *agg_avg += avg_bw;
*agg_peak = max_t(u32, *agg_peak, peak_bw); *agg_peak = max_t(u32, *agg_peak, peak_bw);
qn->sum_avg = *agg_avg;
qn->max_peak = *agg_peak;
for (i = 0; i < qn->num_bcms; i++) for (i = 0; i < qn->num_bcms; i++)
qn->bcms[i]->dirty = true; qn->bcms[i]->dirty = true;
...@@ -675,7 +699,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) ...@@ -675,7 +699,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
* Construct the command list based on a pre ordered list of BCMs * Construct the command list based on a pre ordered list of BCMs
* based on VCD. * based on VCD.
*/ */
tcs_list_gen(&commit_list, cmds, commit_idx); tcs_list_gen(&commit_list, QCOM_ICC_BUCKET_AMC, cmds, commit_idx);
if (!commit_idx[0]) if (!commit_idx[0])
return ret; return ret;
...@@ -693,6 +717,41 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) ...@@ -693,6 +717,41 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
return ret; return ret;
} }
INIT_LIST_HEAD(&commit_list);
for (i = 0; i < qp->num_bcms; i++) {
/*
* Only generate WAKE and SLEEP commands if a resource's
* requirements change as the execution environment transitions
* between different power states.
*/
if (qp->bcms[i]->vote_x[QCOM_ICC_BUCKET_WAKE] !=
qp->bcms[i]->vote_x[QCOM_ICC_BUCKET_SLEEP] ||
qp->bcms[i]->vote_y[QCOM_ICC_BUCKET_WAKE] !=
qp->bcms[i]->vote_y[QCOM_ICC_BUCKET_SLEEP]) {
list_add_tail(&qp->bcms[i]->list, &commit_list);
}
}
if (list_empty(&commit_list))
return ret;
tcs_list_gen(&commit_list, QCOM_ICC_BUCKET_WAKE, cmds, commit_idx);
ret = rpmh_write_batch(qp->dev, RPMH_WAKE_ONLY_STATE, cmds, commit_idx);
if (ret) {
pr_err("Error sending WAKE RPMH requests (%d)\n", ret);
return ret;
}
tcs_list_gen(&commit_list, QCOM_ICC_BUCKET_SLEEP, cmds, commit_idx);
ret = rpmh_write_batch(qp->dev, RPMH_SLEEP_STATE, cmds, commit_idx);
if (ret) {
pr_err("Error sending SLEEP RPMH requests (%d)\n", ret);
return ret;
}
return ret; return ret;
} }
...@@ -738,6 +797,7 @@ static int qnoc_probe(struct platform_device *pdev) ...@@ -738,6 +797,7 @@ static int qnoc_probe(struct platform_device *pdev)
provider = &qp->provider; provider = &qp->provider;
provider->dev = &pdev->dev; provider->dev = &pdev->dev;
provider->set = qcom_icc_set; provider->set = qcom_icc_set;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate; provider->aggregate = qcom_icc_aggregate;
provider->xlate = of_icc_xlate_onecell; provider->xlate = of_icc_xlate_onecell;
INIT_LIST_HEAD(&provider->nodes); INIT_LIST_HEAD(&provider->nodes);
......
// SPDX-License-Identifier: GPL-2.0
/*
* RPM over SMD communication wrapper for interconnects
*
* Copyright (C) 2019 Linaro Ltd
* Author: Georgi Djakov <georgi.djakov@linaro.org>
*/
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/soc/qcom/smd-rpm.h>
#include "smd-rpm.h"
#define RPM_KEY_BW 0x00007762
static struct qcom_smd_rpm *icc_smd_rpm;
struct icc_rpm_smd_req {
__le32 key;
__le32 nbytes;
__le32 value;
};
bool qcom_icc_rpm_smd_available(void)
{
return !!icc_smd_rpm;
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_available);
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
{
struct icc_rpm_smd_req req = {
.key = cpu_to_le32(RPM_KEY_BW),
.nbytes = cpu_to_le32(sizeof(u32)),
.value = cpu_to_le32(val),
};
return qcom_rpm_smd_write(icc_smd_rpm, ctx, rsc_type, id, &req,
sizeof(req));
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send);
static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
{
icc_smd_rpm = NULL;
return 0;
}
static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
{
icc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
if (!icc_smd_rpm) {
dev_err(&pdev->dev, "unable to retrieve handle to RPM\n");
return -ENODEV;
}
return 0;
}
static struct platform_driver qcom_interconnect_rpm_smd_driver = {
.driver = {
.name = "icc_smd_rpm",
},
.probe = qcom_icc_rpm_smd_probe,
.remove = qcom_icc_rpm_smd_remove,
};
module_platform_driver(qcom_interconnect_rpm_smd_driver);
MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect proxy driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:icc_smd_rpm");
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019, Linaro Ltd.
* Author: Georgi Djakov <georgi.djakov@linaro.org>
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
#define __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
#include <linux/soc/qcom/smd-rpm.h>
bool qcom_icc_rpm_smd_available(void);
int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
#endif
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm interconnect IDs
*
* Copyright (c) 2019, Linaro Ltd.
* Author: Georgi Djakov <georgi.djakov@linaro.org>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
#define MASTER_AMPSS_M0 0
#define MASTER_OXILI 1
#define MASTER_MDP_PORT0 2
#define MASTER_SNOC_BIMC_1 3
#define MASTER_TCU_0 4
#define SLAVE_EBI_CH0 5
#define SLAVE_BIMC_SNOC 6
#define MASTER_SPDM 0
#define MASTER_BLSP_1 1
#define MASTER_BLSP_2 2
#define MASTER_XI_USB_HS1 3
#define MASTER_CRYPT0 4
#define MASTER_SDCC_1 5
#define MASTER_SDCC_2 6
#define MASTER_SNOC_PCNOC 7
#define MASTER_QPIC 8
#define PCNOC_INT_0 9
#define PCNOC_INT_2 10
#define PCNOC_INT_3 11
#define PCNOC_S_0 12
#define PCNOC_S_1 13
#define PCNOC_S_2 14
#define PCNOC_S_3 15
#define PCNOC_S_4 16
#define PCNOC_S_6 17
#define PCNOC_S_7 18
#define PCNOC_S_8 19
#define PCNOC_S_9 20
#define PCNOC_S_10 21
#define PCNOC_S_11 22
#define SLAVE_SPDM 23
#define SLAVE_PDM 24
#define SLAVE_PRNG 25
#define SLAVE_TCSR 26
#define SLAVE_SNOC_CFG 27
#define SLAVE_MESSAGE_RAM 28
#define SLAVE_DISP_SS_CFG 29
#define SLAVE_GPU_CFG 30
#define SLAVE_BLSP_1 31
#define SLAVE_BLSP_2 32
#define SLAVE_TLMM_NORTH 33
#define SLAVE_PCIE 34
#define SLAVE_ETHERNET 35
#define SLAVE_TLMM_EAST 36
#define SLAVE_TCU 37
#define SLAVE_PMIC_ARB 38
#define SLAVE_SDCC_1 39
#define SLAVE_SDCC_2 40
#define SLAVE_TLMM_SOUTH 41
#define SLAVE_USB_HS 42
#define SLAVE_USB3 43
#define SLAVE_CRYPTO_0_CFG 44
#define SLAVE_PCNOC_SNOC 45
#define MASTER_QDSS_BAM 0
#define MASTER_BIMC_SNOC 1
#define MASTER_PCNOC_SNOC 2
#define MASTER_QDSS_ETR 3
#define MASTER_EMAC 4
#define MASTER_PCIE 5
#define MASTER_USB3 6
#define QDSS_INT 7
#define SNOC_INT_0 8
#define SNOC_INT_1 9
#define SNOC_INT_2 10
#define SLAVE_KPSS_AHB 11
#define SLAVE_WCSS 12
#define SLAVE_SNOC_BIMC_1 13
#define SLAVE_IMEM 14
#define SLAVE_SNOC_PCNOC 15
#define SLAVE_QDSS_STM 16
#define SLAVE_CATS_0 17
#define SLAVE_CATS_1 18
#define SLAVE_LPASS 19
#endif
...@@ -36,6 +36,8 @@ struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec, ...@@ -36,6 +36,8 @@ struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
* @nodes: internal list of the interconnect provider nodes * @nodes: internal list of the interconnect provider nodes
* @set: pointer to device specific set operation function * @set: pointer to device specific set operation function
* @aggregate: pointer to device specific aggregate operation function * @aggregate: pointer to device specific aggregate operation function
* @pre_aggregate: pointer to device specific function that is called
* before the aggregation begins (optional)
* @xlate: provider-specific callback for mapping nodes from phandle arguments * @xlate: provider-specific callback for mapping nodes from phandle arguments
* @dev: the device this interconnect provider belongs to * @dev: the device this interconnect provider belongs to
* @users: count of active users * @users: count of active users
...@@ -45,8 +47,9 @@ struct icc_provider { ...@@ -45,8 +47,9 @@ struct icc_provider {
struct list_head provider_list; struct list_head provider_list;
struct list_head nodes; struct list_head nodes;
int (*set)(struct icc_node *src, struct icc_node *dst); int (*set)(struct icc_node *src, struct icc_node *dst);
int (*aggregate)(struct icc_node *node, u32 avg_bw, u32 peak_bw, int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
u32 *agg_avg, u32 *agg_peak); u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
void (*pre_aggregate)(struct icc_node *node);
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data); struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
struct device *dev; struct device *dev;
int users; int users;
......
...@@ -30,6 +30,7 @@ struct icc_path *icc_get(struct device *dev, const int src_id, ...@@ -30,6 +30,7 @@ struct icc_path *icc_get(struct device *dev, const int src_id,
struct icc_path *of_icc_get(struct device *dev, const char *name); struct icc_path *of_icc_get(struct device *dev, const char *name);
void icc_put(struct icc_path *path); void icc_put(struct icc_path *path);
int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw); int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw);
void icc_set_tag(struct icc_path *path, u32 tag);
#else #else
...@@ -54,6 +55,10 @@ static inline int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) ...@@ -54,6 +55,10 @@ static inline int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw)
return 0; return 0;
} }
static inline void icc_set_tag(struct icc_path *path, u32 tag)
{
}
#endif /* CONFIG_INTERCONNECT */ #endif /* CONFIG_INTERCONNECT */
#endif /* __LINUX_INTERCONNECT_H */ #endif /* __LINUX_INTERCONNECT_H */
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
/* /*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*/ */
#ifndef __SOC_QCOM_TCS_H__ #ifndef __SOC_QCOM_TCS_H__
...@@ -53,4 +53,22 @@ struct tcs_request { ...@@ -53,4 +53,22 @@ struct tcs_request {
struct tcs_cmd *cmds; struct tcs_cmd *cmds;
}; };
#define BCM_TCS_CMD_COMMIT_SHFT 30
#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
#define BCM_TCS_CMD_VALID_SHFT 29
#define BCM_TCS_CMD_VALID_MASK 0x20000000
#define BCM_TCS_CMD_VOTE_X_SHFT 14
#define BCM_TCS_CMD_VOTE_MASK 0x3fff
#define BCM_TCS_CMD_VOTE_Y_SHFT 0
#define BCM_TCS_CMD_VOTE_Y_MASK 0xfffc000
/* Construct a Bus Clock Manager (BCM) specific TCS command */
#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
(((commit) << BCM_TCS_CMD_COMMIT_SHFT) | \
((valid) << BCM_TCS_CMD_VALID_SHFT) | \
((cpu_to_le32(vote_x) & \
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \
((cpu_to_le32(vote_y) & \
BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT))
#endif /* __SOC_QCOM_TCS_H__ */ #endif /* __SOC_QCOM_TCS_H__ */
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