[SPARC64]: Annotate 64-bit constants with 'UL'

arch/sparc64/kernel/sbus.c

@@ -810,17 +810,17 @@ unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
 /* Error interrupt handling. */
 #define SYSIO_UE_AFSR	0x0030UL
 #define SYSIO_UE_AFAR	0x0038UL
-#define  SYSIO_UEAFSR_PPIO	0x8000000000000000 /* Primary PIO is cause         */
-#define  SYSIO_UEAFSR_PDRD	0x4000000000000000 /* Primary DVMA read is cause   */
-#define  SYSIO_UEAFSR_PDWR	0x2000000000000000 /* Primary DVMA write is cause  */
-#define  SYSIO_UEAFSR_SPIO	0x1000000000000000 /* Secondary PIO is cause       */
-#define  SYSIO_UEAFSR_SDRD	0x0800000000000000 /* Secondary DVMA read is cause */
-#define  SYSIO_UEAFSR_SDWR	0x0400000000000000 /* Secondary DVMA write is cause*/
-#define  SYSIO_UEAFSR_RESV1	0x03ff000000000000 /* Reserved                     */
-#define  SYSIO_UEAFSR_DOFF	0x0000e00000000000 /* Doubleword Offset            */
-#define  SYSIO_UEAFSR_SIZE	0x00001c0000000000 /* Bad transfer size is 2**SIZE */
-#define  SYSIO_UEAFSR_MID	0x000003e000000000 /* UPA MID causing the fault    */
-#define  SYSIO_UEAFSR_RESV2	0x0000001fffffffff /* Reserved                     */
+#define  SYSIO_UEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
+#define  SYSIO_UEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
+#define  SYSIO_UEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
+#define  SYSIO_UEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO is cause    */
+#define  SYSIO_UEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
+#define  SYSIO_UEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
+#define  SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
+#define  SYSIO_UEAFSR_DOFF  0x0000e00000000000UL /* Doubleword Offset         */
+#define  SYSIO_UEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
+#define  SYSIO_UEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
+#define  SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
 static irqreturn_t sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct sbus_bus *sbus = dev_id;
@@ -881,18 +881,18 @@ static irqreturn_t sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
 
 #define SYSIO_CE_AFSR	0x0040UL
 #define SYSIO_CE_AFAR	0x0048UL
-#define  SYSIO_CEAFSR_PPIO	0x8000000000000000 /* Primary PIO is cause         */
-#define  SYSIO_CEAFSR_PDRD	0x4000000000000000 /* Primary DVMA read is cause   */
-#define  SYSIO_CEAFSR_PDWR	0x2000000000000000 /* Primary DVMA write is cause  */
-#define  SYSIO_CEAFSR_SPIO	0x1000000000000000 /* Secondary PIO is cause       */
-#define  SYSIO_CEAFSR_SDRD	0x0800000000000000 /* Secondary DVMA read is cause */
-#define  SYSIO_CEAFSR_SDWR	0x0400000000000000 /* Secondary DVMA write is cause*/
-#define  SYSIO_CEAFSR_RESV1	0x0300000000000000 /* Reserved                     */
-#define  SYSIO_CEAFSR_ESYND	0x00ff000000000000 /* Syndrome Bits                */
-#define  SYSIO_CEAFSR_DOFF	0x0000e00000000000 /* Double Offset                */
-#define  SYSIO_CEAFSR_SIZE	0x00001c0000000000 /* Bad transfer size is 2**SIZE */
-#define  SYSIO_CEAFSR_MID	0x000003e000000000 /* UPA MID causing the fault    */
-#define  SYSIO_CEAFSR_RESV2	0x0000001fffffffff /* Reserved                     */
+#define  SYSIO_CEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
+#define  SYSIO_CEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
+#define  SYSIO_CEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
+#define  SYSIO_CEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO cause       */
+#define  SYSIO_CEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
+#define  SYSIO_CEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
+#define  SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved                  */
+#define  SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits             */
+#define  SYSIO_CEAFSR_DOFF  0x0000e00000000000UL /* Double Offset             */
+#define  SYSIO_CEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
+#define  SYSIO_CEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
+#define  SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
 static irqreturn_t sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct sbus_bus *sbus = dev_id;
@@ -958,18 +958,18 @@ static irqreturn_t sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
 
 #define SYSIO_SBUS_AFSR		0x2010UL
 #define SYSIO_SBUS_AFAR		0x2018UL
-#define  SYSIO_SBAFSR_PLE	0x8000000000000000 /* Primary Late PIO Error       */
-#define  SYSIO_SBAFSR_PTO	0x4000000000000000 /* Primary SBUS Timeout         */
-#define  SYSIO_SBAFSR_PBERR	0x2000000000000000 /* Primary SBUS Error ACK       */
-#define  SYSIO_SBAFSR_SLE	0x1000000000000000 /* Secondary Late PIO Error     */
-#define  SYSIO_SBAFSR_STO	0x0800000000000000 /* Secondary SBUS Timeout       */
-#define  SYSIO_SBAFSR_SBERR	0x0400000000000000 /* Secondary SBUS Error ACK     */
-#define  SYSIO_SBAFSR_RESV1	0x03ff000000000000 /* Reserved                     */
-#define  SYSIO_SBAFSR_RD	0x0000800000000000 /* Primary was late PIO read    */
-#define  SYSIO_SBAFSR_RESV2	0x0000600000000000 /* Reserved                     */
-#define  SYSIO_SBAFSR_SIZE	0x00001c0000000000 /* Size of transfer             */
-#define  SYSIO_SBAFSR_MID	0x000003e000000000 /* MID causing the error        */
-#define  SYSIO_SBAFSR_RESV3	0x0000001fffffffff /* Reserved                     */
+#define  SYSIO_SBAFSR_PLE   0x8000000000000000UL /* Primary Late PIO Error    */
+#define  SYSIO_SBAFSR_PTO   0x4000000000000000UL /* Primary SBUS Timeout      */
+#define  SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK    */
+#define  SYSIO_SBAFSR_SLE   0x1000000000000000UL /* Secondary Late PIO Error  */
+#define  SYSIO_SBAFSR_STO   0x0800000000000000UL /* Secondary SBUS Timeout    */
+#define  SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK  */
+#define  SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
+#define  SYSIO_SBAFSR_RD    0x0000800000000000UL /* Primary was late PIO read */
+#define  SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved                  */
+#define  SYSIO_SBAFSR_SIZE  0x00001c0000000000UL /* Size of transfer          */
+#define  SYSIO_SBAFSR_MID   0x000003e000000000UL /* MID causing the error     */
+#define  SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved                  */
 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct sbus_bus *sbus = dev_id;
@@ -1030,9 +1030,9 @@ static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id, struct pt_reg
 }
 
 #define ECC_CONTROL	0x0020UL
-#define  SYSIO_ECNTRL_ECCEN	0x8000000000000000 /* Enable ECC Checking          */
-#define  SYSIO_ECNTRL_UEEN	0x4000000000000000 /* Enable UE Interrupts         */
-#define  SYSIO_ECNTRL_CEEN	0x2000000000000000 /* Enable CE Interrupts         */
+#define  SYSIO_ECNTRL_ECCEN	0x8000000000000000UL /* Enable ECC Checking   */
+#define  SYSIO_ECNTRL_UEEN	0x4000000000000000UL /* Enable UE Interrupts  */
+#define  SYSIO_ECNTRL_CEEN	0x2000000000000000UL /* Enable CE Interrupts  */
 
 #define SYSIO_UE_INO		0x34
 #define SYSIO_CE_INO		0x35

include/asm-sparc64/chmctrl.h

@@ -14,171 +14,171 @@
 #define CHMCTRL_MACTRL		0x30 /* Memory Address Control		*/
 
 /* Memory Timing Control I */
-#define TCTRL1_SDRAMCTL_DLY	0xf000000000000000
+#define TCTRL1_SDRAMCTL_DLY	0xf000000000000000UL
 #define TCTRL1_SDRAMCTL_DLY_SHIFT     60
-#define TCTRL1_SDRAMCLK_DLY	0x0e00000000000000
+#define TCTRL1_SDRAMCLK_DLY	0x0e00000000000000UL
 #define TCTRL1_SDRAMCLK_DLY_SHIFT     57
-#define TCTRL1_R		0x0100000000000000
+#define TCTRL1_R		0x0100000000000000UL
 #define TCTRL1_R_SHIFT 		      56
-#define TCTRL1_AUTORFR_CYCLE	0x00fe000000000000
+#define TCTRL1_AUTORFR_CYCLE	0x00fe000000000000UL
 #define TCTRL1_AUTORFR_CYCLE_SHIFT    49
-#define TCTRL1_RD_WAIT		0x0001f00000000000
+#define TCTRL1_RD_WAIT		0x0001f00000000000UL
 #define TCTRL1_RD_WAIT_SHIFT	      44
-#define TCTRL1_PC_CYCLE		0x00000fc000000000
+#define TCTRL1_PC_CYCLE		0x00000fc000000000UL
 #define TCTRL1_PC_CYCLE_SHIFT	      38
-#define TCTRL1_WR_MORE_RAS_PW	0x0000003f00000000
+#define TCTRL1_WR_MORE_RAS_PW	0x0000003f00000000UL
 #define TCTRL1_WR_MORE_RAS_PW_SHIFT   32
-#define TCTRL1_RD_MORE_RAW_PW	0x00000000fc000000
+#define TCTRL1_RD_MORE_RAW_PW	0x00000000fc000000UL
 #define TCTRL1_RD_MORE_RAS_PW_SHIFT   26
-#define TCTRL1_ACT_WR_DLY	0x0000000003f00000
+#define TCTRL1_ACT_WR_DLY	0x0000000003f00000UL
 #define TCTRL1_ACT_WR_DLY_SHIFT	      20
-#define TCTRL1_ACT_RD_DLY	0x00000000000fc000
+#define TCTRL1_ACT_RD_DLY	0x00000000000fc000UL
 #define TCTRL1_ACT_RD_DLY_SHIFT	      14
-#define TCTRL1_BANK_PRESENT	0x0000000000003000
+#define TCTRL1_BANK_PRESENT	0x0000000000003000UL
 #define TCTRL1_BANK_PRESENT_SHIFT     12
-#define TCTRL1_RFR_INT		0x0000000000000ff8
+#define TCTRL1_RFR_INT		0x0000000000000ff8UL
 #define TCTRL1_RFR_INT_SHIFT	      3
-#define TCTRL1_SET_MODE_REG	0x0000000000000004
+#define TCTRL1_SET_MODE_REG	0x0000000000000004UL
 #define TCTRL1_SET_MODE_REG_SHIFT     2
-#define TCTRL1_RFR_ENABLE	0x0000000000000002
+#define TCTRL1_RFR_ENABLE	0x0000000000000002UL
 #define TCTRL1_RFR_ENABLE_SHIFT	      1
-#define TCTRL1_PRECHG_ALL	0x0000000000000001
+#define TCTRL1_PRECHG_ALL	0x0000000000000001UL
 #define TCTRL1_PRECHG_ALL_SHIFT	      0
 
 /* Memory Timing Control II */
-#define TCTRL2_WR_MSEL_DLY	0xfc00000000000000
+#define TCTRL2_WR_MSEL_DLY	0xfc00000000000000UL
 #define TCTRL2_WR_MSEL_DLY_SHIFT      58
-#define TCTRL2_RD_MSEL_DLY	0x03f0000000000000
+#define TCTRL2_RD_MSEL_DLY	0x03f0000000000000UL
 #define TCTRL2_RD_MSEL_DLY_SHIFT      52
-#define TCTRL2_WRDATA_THLD	0x000c000000000000
+#define TCTRL2_WRDATA_THLD	0x000c000000000000UL
 #define TCTRL2_WRDATA_THLD_SHIFT      50
-#define TCTRL2_RDWR_RD_TI_DLY	0x0003f00000000000
+#define TCTRL2_RDWR_RD_TI_DLY	0x0003f00000000000UL
 #define TCTRL2_RDWR_RD_TI_DLY_SHIFT   44
-#define TCTRL2_AUTOPRECHG_ENBL	0x0000080000000000
+#define TCTRL2_AUTOPRECHG_ENBL	0x0000080000000000UL
 #define TCTRL2_AUTOPRECHG_ENBL_SHIFT  43
-#define TCTRL2_RDWR_PI_MORE_DLY	0x000007c000000000
+#define TCTRL2_RDWR_PI_MORE_DLY	0x000007c000000000UL
 #define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
-#define TCTRL2_RDWR_1_DLY	0x0000003f00000000
+#define TCTRL2_RDWR_1_DLY	0x0000003f00000000UL
 #define TCTRL2_RDWR_1_DLY_SHIFT       32
-#define TCTRL2_WRWR_PI_MORE_DLY	0x00000000f8000000
+#define TCTRL2_WRWR_PI_MORE_DLY	0x00000000f8000000UL
 #define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
-#define TCTRL2_WRWR_1_DLY	0x0000000007e00000
+#define TCTRL2_WRWR_1_DLY	0x0000000007e00000UL
 #define TCTRL2_WRWR_1_DLY_SHIFT       21
-#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000
+#define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
 #define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
-#define TCTRL2_R		0x0000000000008000
+#define TCTRL2_R		0x0000000000008000UL
 #define TCTRL2_R_SHIFT		      15
-#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fff
+#define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
 #define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
 
 /* Memory Timing Control III */
-#define TCTRL3_SDRAM_CTL_DLY	0xf000000000000000
+#define TCTRL3_SDRAM_CTL_DLY	0xf000000000000000UL
 #define TCTRL3_SDRAM_CTL_DLY_SHIFT    60
-#define TCTRL3_SDRAM_CLK_DLY	0x0e00000000000000
+#define TCTRL3_SDRAM_CLK_DLY	0x0e00000000000000UL
 #define TCTRL3_SDRAM_CLK_DLY_SHIFT    57
-#define TCTRL3_R		0x0100000000000000
+#define TCTRL3_R		0x0100000000000000UL
 #define TCTRL3_R_SHIFT		      56
-#define TCTRL3_AUTO_RFR_CYCLE	0x00fe000000000000
+#define TCTRL3_AUTO_RFR_CYCLE	0x00fe000000000000UL
 #define TCTRL3_AUTO_RFR_CYCLE_SHIFT   49
-#define TCTRL3_RD_WAIT		0x0001f00000000000
+#define TCTRL3_RD_WAIT		0x0001f00000000000UL
 #define TCTRL3_RD_WAIT_SHIFT	      44
-#define TCTRL3_PC_CYCLE		0x00000fc000000000
+#define TCTRL3_PC_CYCLE		0x00000fc000000000UL
 #define TCTRL3_PC_CYCLE_SHIFT	      38
-#define TCTRL3_WR_MORE_RAW_PW	0x0000003f00000000
+#define TCTRL3_WR_MORE_RAW_PW	0x0000003f00000000UL
 #define TCTRL3_WR_MORE_RAW_PW_SHIFT   32
-#define TCTRL3_RD_MORE_RAW_PW	0x00000000fc000000
+#define TCTRL3_RD_MORE_RAW_PW	0x00000000fc000000UL
 #define TCTRL3_RD_MORE_RAW_PW_SHIFT   26
-#define TCTRL3_ACT_WR_DLY	0x0000000003f00000
+#define TCTRL3_ACT_WR_DLY	0x0000000003f00000UL
 #define TCTRL3_ACT_WR_DLY_SHIFT       20
-#define TCTRL3_ACT_RD_DLY	0x00000000000fc000
+#define TCTRL3_ACT_RD_DLY	0x00000000000fc000UL
 #define TCTRL3_ACT_RD_DLY_SHIFT       14
-#define TCTRL3_BANK_PRESENT	0x0000000000003000
+#define TCTRL3_BANK_PRESENT	0x0000000000003000UL
 #define TCTRL3_BANK_PRESENT_SHIFT     12
-#define TCTRL3_RFR_INT		0x0000000000000ff8
+#define TCTRL3_RFR_INT		0x0000000000000ff8UL
 #define TCTRL3_RFR_INT_SHIFT	      3
-#define TCTRL3_SET_MODE_REG	0x0000000000000004
+#define TCTRL3_SET_MODE_REG	0x0000000000000004UL
 #define TCTRL3_SET_MODE_REG_SHIFT     2
-#define TCTRL3_RFR_ENABLE	0x0000000000000002
+#define TCTRL3_RFR_ENABLE	0x0000000000000002UL
 #define TCTRL3_RFR_ENABLE_SHIFT       1
-#define TCTRL3_PRECHG_ALL	0x0000000000000001
+#define TCTRL3_PRECHG_ALL	0x0000000000000001UL
 #define TCTRL3_PRECHG_ALL_SHIFT	      0
 
 /* Memory Timing Control IV */
-#define TCTRL4_WR_MSEL_DLY	0xfc00000000000000
+#define TCTRL4_WR_MSEL_DLY	0xfc00000000000000UL
 #define TCTRL4_WR_MSEL_DLY_SHIFT      58
-#define TCTRL4_RD_MSEL_DLY	0x03f0000000000000
+#define TCTRL4_RD_MSEL_DLY	0x03f0000000000000UL
 #define TCTRL4_RD_MSEL_DLY_SHIFT      52
-#define TCTRL4_WRDATA_THLD	0x000c000000000000
+#define TCTRL4_WRDATA_THLD	0x000c000000000000UL
 #define TCTRL4_WRDATA_THLD_SHIFT      50
-#define TCTRL4_RDWR_RD_RI_DLY	0x0003f00000000000
+#define TCTRL4_RDWR_RD_RI_DLY	0x0003f00000000000UL
 #define TCTRL4_RDWR_RD_RI_DLY_SHIFT   44
-#define TCTRL4_AUTO_PRECHG_ENBL	0x0000080000000000
+#define TCTRL4_AUTO_PRECHG_ENBL	0x0000080000000000UL
 #define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
-#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000
+#define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
 #define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
-#define TCTRL4_RD_WR_TI_DLY	0x0000003f00000000
+#define TCTRL4_RD_WR_TI_DLY	0x0000003f00000000UL
 #define TCTRL4_RD_WR_TI_DLY_SHIFT     32
-#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000
+#define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
 #define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
-#define TCTRL4_WR_WR_TI_DLY	0x0000000007e00000
+#define TCTRL4_WR_WR_TI_DLY	0x0000000007e00000UL
 #define TCTRL4_WR_WR_TI_DLY_SHIFT     21
-#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f0000
+#define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
 #define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
-#define TCTRL4_R		0x0000000000008000
+#define TCTRL4_R		0x0000000000008000UL
 #define TCTRL4_R_SHIFT		      15
-#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fff
+#define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
 #define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
 
 /* All 4 memory address decoding registers have the
  * same layout.
  */
-#define MEM_DECODE_VALID	0x8000000000000000 /* Valid */
+#define MEM_DECODE_VALID	0x8000000000000000UL /* Valid */
 #define MEM_DECODE_VALID_SHIFT	      63
-#define MEM_DECODE_UK		0x001ffe0000000000 /* Upper mask */
+#define MEM_DECODE_UK		0x001ffe0000000000UL /* Upper mask */
 #define MEM_DECODE_UK_SHIFT	      41
-#define MEM_DECODE_UM		0x0000001ffff00000 /* Upper match */
+#define MEM_DECODE_UM		0x0000001ffff00000UL /* Upper match */
 #define MEM_DECODE_UM_SHIFT	      20
-#define MEM_DECODE_LK		0x000000000003c000 /* Lower mask */
+#define MEM_DECODE_LK		0x000000000003c000UL /* Lower mask */
 #define MEM_DECODE_LK_SHIFT	      14
-#define MEM_DECODE_LM		0x0000000000000f00 /* Lower match */
+#define MEM_DECODE_LM		0x0000000000000f00UL /* Lower match */
 #define MEM_DECODE_LM_SHIFT           8
 
-#define PA_UPPER_BITS		0x000007fffc000000
+#define PA_UPPER_BITS		0x000007fffc000000UL
 #define PA_UPPER_BITS_SHIFT	26
-#define PA_LOWER_BITS		0x00000000000003c0
+#define PA_LOWER_BITS		0x00000000000003c0UL
 #define PA_LOWER_BITS_SHIFT	6
 
-#define MACTRL_R0		         0x8000000000000000
+#define MACTRL_R0		         0x8000000000000000UL
 #define MACTRL_R0_SHIFT		         63
-#define MACTRL_ADDR_LE_PW                0x7000000000000000
+#define MACTRL_ADDR_LE_PW                0x7000000000000000UL
 #define MACTRL_ADDR_LE_PW_SHIFT		 60
-#define MACTRL_CMD_PW                    0x0f00000000000000
+#define MACTRL_CMD_PW                    0x0f00000000000000UL
 #define MACTRL_CMD_PW_SHIFT		 56
-#define MACTRL_HALF_MODE_WR_MSEL_DLY     0x00fc000000000000
+#define MACTRL_HALF_MODE_WR_MSEL_DLY     0x00fc000000000000UL
 #define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
-#define MACTRL_HALF_MODE_RD_MSEL_DLY     0x0003f00000000000
+#define MACTRL_HALF_MODE_RD_MSEL_DLY     0x0003f00000000000UL
 #define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
-#define MACTRL_HALF_MODE_SDRAM_CTL_DLY   0x00000f0000000000
+#define MACTRL_HALF_MODE_SDRAM_CTL_DLY   0x00000f0000000000UL
 #define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
-#define MACTRL_HALF_MODE_SDRAM_CLK_DLY   0x000000e000000000
+#define MACTRL_HALF_MODE_SDRAM_CLK_DLY   0x000000e000000000UL
 #define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
-#define MACTRL_R1                        0x0000001000000000
+#define MACTRL_R1                        0x0000001000000000UL
 #define MACTRL_R1_SHIFT                      36
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
-#define MACTRL_ENC_INTLV_B3              0x00000000f8000000
+#define MACTRL_ENC_INTLV_B3              0x00000000f8000000UL
 #define MACTRL_ENC_INTLV_B3_SHIFT              27
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
-#define MACTRL_ENC_INTLV_B2              0x00000000007c0000
+#define MACTRL_ENC_INTLV_B2              0x00000000007c0000UL
 #define MACTRL_ENC_INTLV_B2_SHIFT              18
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
-#define MACTRL_ENC_INTLV_B1              0x0000000000003e00
+#define MACTRL_ENC_INTLV_B1              0x0000000000003e00UL
 #define MACTRL_ENC_INTLV_B1_SHIFT               9
-#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0
+#define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT  5
-#define MACTRL_ENC_INTLV_B0              0x000000000000001f
+#define MACTRL_ENC_INTLV_B0              0x000000000000001fUL
 #define MACTRL_ENC_INTLV_B0_SHIFT               0
 
 #endif /* _SPARC64_CHMCTRL_H */

include/asm-sparc64/const.h

+/* const.h: Macros for dealing with constants.  */
+
+#ifndef _SPARC64_CONST_H
+#define _SPARC64_CONST_H
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specificers unilaterally.  We
+ * use the following macros to deal with this.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)	X
+#else
+#define _AC(X,Y)	(X##Y)
+#endif
+
+
+#endif /* !(_SPARC64_CONST_H) */

include/asm-sparc64/iommu.h

@@ -7,13 +7,13 @@
 #define _SPARC64_IOMMU_H
 
 /* The format of an iopte in the page tables. */
-#define IOPTE_VALID         0x8000000000000000 /* IOPTE is valid                   */
-#define IOPTE_64K           0x2000000000000000 /* IOPTE is for 64k page            */
-#define IOPTE_STBUF         0x1000000000000000 /* DVMA can use streaming buffer    */
-#define IOPTE_INTRA         0x0800000000000000 /* SBUS slot-->slot direct transfer */
-#define IOPTE_CONTEXT	    0x07ff800000000000 /* Context number		   */
-#define IOPTE_PAGE          0x00007fffffffe000 /* Physical page number (PA[42:13]) */
-#define IOPTE_CACHE         0x0000000000000010 /* Cached (in UPA E-cache)          */
-#define IOPTE_WRITE         0x0000000000000002 /* Writeable                        */
+#define IOPTE_VALID   0x8000000000000000UL /* IOPTE is valid                  */
+#define IOPTE_64K     0x2000000000000000UL /* IOPTE is for 64k page           */
+#define IOPTE_STBUF   0x1000000000000000UL /* DVMA can use streaming buffer   */
+#define IOPTE_INTRA   0x0800000000000000UL /* SBUS slot-->slot direct transfer*/
+#define IOPTE_CONTEXT 0x07ff800000000000UL /* Context number		      */
+#define IOPTE_PAGE    0x00007fffffffe000UL /* Physical page number (PA[42:13])*/
+#define IOPTE_CACHE   0x0000000000000010UL /* Cached (in UPA E-cache)         */
+#define IOPTE_WRITE   0x0000000000000002UL /* Writeable                       */
 
 #endif /* !(_SPARC_IOMMU_H) */

include/asm-sparc64/page.h

@@ -4,18 +4,12 @@
 #define _SPARC64_PAGE_H
 
 #include <linux/config.h>
+#include <asm/const.h>
 
 #define PAGE_SHIFT   13
-#ifndef __ASSEMBLY__
-/* I have my suspicions... -DaveM */
-#define PAGE_SIZE    (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE    (1 << PAGE_SHIFT)
-#endif
-
+#define PAGE_SIZE    (_AC(1,UL) << PAGE_SHIFT)
 #define PAGE_MASK    (~(PAGE_SIZE-1))
 
-
 #ifdef __KERNEL__
 
 #ifndef __ASSEMBLY__
@@ -99,13 +93,13 @@ typedef unsigned long iopgprot_t;
 #endif
 
 #ifdef CONFIG_HUGETLB_PAGE
-#define HPAGE_SIZE		((1UL) << HPAGE_SHIFT)
+#define HPAGE_SIZE		(_AC(1,UL) << HPAGE_SHIFT)
 #define HPAGE_MASK		(~(HPAGE_SIZE - 1UL))
 #define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
 #endif
 
 #define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_32BIT) ? \
-				 (0x0000000070000000UL) : (PAGE_OFFSET))
+				 (_AC(0x0000000070000000,UL)) : (PAGE_OFFSET))
 
 #endif /* !(__ASSEMBLY__) */
 
@@ -115,7 +109,7 @@ typedef unsigned long iopgprot_t;
 /* We used to stick this into a hard-coded global register (%g4)
  * but that does not make sense anymore.
  */
-#define PAGE_OFFSET		0xFFFFF80000000000
+#define PAGE_OFFSET		_AC(0xFFFFF80000000000,UL)
 
 #define __pa(x)			((unsigned long)(x) - PAGE_OFFSET)
 #define __va(x)			((void *)((unsigned long) (x) + PAGE_OFFSET))

include/asm-sparc64/pci.h

@@ -168,7 +168,7 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
  * can drive enough of the 64 bits.
  */
 #define PCI64_REQUIRED_MASK	(~(dma64_addr_t)0)
-#define PCI64_ADDR_BASE		0xfffc000000000000
+#define PCI64_ADDR_BASE		0xfffc000000000000UL
 
 /* Usage of the pci_dac_foo interfaces is only valid if this
  * test passes.

include/asm-sparc64/pgtable.h

@@ -18,6 +18,7 @@
 #include <asm/system.h>
 #include <asm/page.h>
 #include <asm/processor.h>
+#include <asm/const.h>
 
 /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 16MB).
  * The page copy blockops use 0x1000000 to 0x18000000 (16MB --> 24MB).
@@ -26,14 +27,14 @@
  * There is a single static kernel PMD which maps from 0x0 to address
  * 0x400000000.
  */
-#define	TLBTEMP_BASE		0x0000000001000000
-#define MODULES_VADDR		0x0000000002000000
-#define MODULES_LEN		0x000000007e000000
-#define MODULES_END		0x0000000080000000
-#define VMALLOC_START		0x0000000140000000
-#define VMALLOC_END		0x0000000200000000
-#define LOW_OBP_ADDRESS		0x00000000f0000000
-#define HI_OBP_ADDRESS		0x0000000100000000
+#define	TLBTEMP_BASE		_AC(0x0000000001000000,UL)
+#define MODULES_VADDR		_AC(0x0000000002000000,UL)
+#define MODULES_LEN		_AC(0x000000007e000000,UL)
+#define MODULES_END		_AC(0x0000000080000000,UL)
+#define VMALLOC_START		_AC(0x0000000140000000,UL)
+#define VMALLOC_END		_AC(0x0000000200000000,UL)
+#define LOW_OBP_ADDRESS		_AC(0x00000000f0000000,UL)
+#define HI_OBP_ADDRESS		_AC(0x0000000100000000,UL)
 
 /* XXX All of this needs to be rethought so we can take advantage
  * XXX cheetah's full 64-bit virtual address space, ie. no more hole
@@ -49,7 +50,9 @@
  * long). Finally, the higher few bits determine pgde#.
  */
 
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
+/* PMD_SHIFT determines the size of the area a second-level page
+ * table can map
+ */
 #define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-3))
 #define PMD_SIZE	(1UL << PMD_SHIFT)
 #define PMD_MASK	(~(PMD_SIZE-1))
@@ -78,7 +81,8 @@
  */
 #define REAL_PTRS_PER_PMD	(1UL << PMD_BITS)
 #define PTRS_PER_PMD		((const int)(test_thread_flag(TIF_32BIT) ? \
-				 (1UL << (32 - (PAGE_SHIFT-3) - PAGE_SHIFT)) : (REAL_PTRS_PER_PMD)))
+				 (1UL << (32 - (PAGE_SHIFT-3) - PAGE_SHIFT)) : \
+				 (REAL_PTRS_PER_PMD)))
 
 /*
  * We cannot use the top address range because VPTE table lives there. This
@@ -102,33 +106,33 @@
 #endif /* !(__ASSEMBLY__) */
 
 /* Spitfire/Cheetah TTE bits. */
-#define _PAGE_VALID	0x8000000000000000	/* Valid TTE                          */
-#define _PAGE_R		0x8000000000000000	/* Used to keep ref bit up to date    */
-#define _PAGE_SZ4MB	0x6000000000000000	/* 4MB Page                           */
-#define _PAGE_SZ512K	0x4000000000000000	/* 512K Page                          */
-#define _PAGE_SZ64K	0x2000000000000000	/* 64K Page                           */
-#define _PAGE_SZ8K	0x0000000000000000	/* 8K Page                            */
-#define _PAGE_NFO	0x1000000000000000	/* No Fault Only                      */
-#define _PAGE_IE	0x0800000000000000	/* Invert Endianness                  */
-#define _PAGE_SN	0x0000800000000000	/* (Cheetah) Snoop                    */
-#define _PAGE_PADDR_SF	0x000001FFFFFFE000	/* (Spitfire) Phys Address [40:13]    */
-#define _PAGE_PADDR	0x000007FFFFFFE000	/* (Cheetah) Phys Address [42:13]     */
-#define _PAGE_SOFT	0x0000000000001F80	/* Software bits                      */
-#define _PAGE_L		0x0000000000000040	/* Locked TTE                         */
-#define _PAGE_CP	0x0000000000000020	/* Cacheable in Physical Cache        */
-#define _PAGE_CV	0x0000000000000010	/* Cacheable in Virtual Cache         */
-#define _PAGE_E		0x0000000000000008	/* side-Effect                        */
-#define _PAGE_P		0x0000000000000004	/* Privileged Page                    */
-#define _PAGE_W		0x0000000000000002	/* Writable                           */
-#define _PAGE_G		0x0000000000000001	/* Global                             */
+#define _PAGE_VALID	_AC(0x8000000000000000,UL) /* Valid TTE               */
+#define _PAGE_R		_AC(0x8000000000000000,UL) /* Keep ref bit up to date */
+#define _PAGE_SZ4MB	_AC(0x6000000000000000,UL) /* 4MB Page                */
+#define _PAGE_SZ512K	_AC(0x4000000000000000,UL) /* 512K Page               */
+#define _PAGE_SZ64K	_AC(0x2000000000000000,UL) /* 64K Page                */
+#define _PAGE_SZ8K	_AC(0x0000000000000000,UL) /* 8K Page                 */
+#define _PAGE_NFO	_AC(0x1000000000000000,UL) /* No Fault Only           */
+#define _PAGE_IE	_AC(0x0800000000000000,UL) /* Invert Endianness       */
+#define _PAGE_SN	_AC(0x0000800000000000,UL) /* (Cheetah) Snoop         */
+#define _PAGE_PADDR_SF	_AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr [40:13]*/
+#define _PAGE_PADDR	_AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr [42:13] */
+#define _PAGE_SOFT	_AC(0x0000000000001F80,UL) /* Software bits           */
+#define _PAGE_L		_AC(0x0000000000000040,UL) /* Locked TTE              */
+#define _PAGE_CP	_AC(0x0000000000000020,UL) /* Cacheable in P-Cache    */
+#define _PAGE_CV	_AC(0x0000000000000010,UL) /* Cacheable in V-Cache    */
+#define _PAGE_E		_AC(0x0000000000000008,UL) /* side-Effect             */
+#define _PAGE_P		_AC(0x0000000000000004,UL) /* Privileged Page         */
+#define _PAGE_W		_AC(0x0000000000000002,UL) /* Writable                */
+#define _PAGE_G		_AC(0x0000000000000001,UL) /* Global                  */
 
 /* Here are the SpitFire software bits we use in the TTE's. */
-#define _PAGE_FILE	0x0000000000001000	/* Pagecache page                     */
-#define _PAGE_MODIFIED	0x0000000000000800	/* Modified Page (ie. dirty)          */
-#define _PAGE_ACCESSED	0x0000000000000400	/* Accessed Page (ie. referenced)     */
-#define _PAGE_READ	0x0000000000000200	/* Readable SW Bit                    */
-#define _PAGE_WRITE	0x0000000000000100	/* Writable SW Bit                    */
-#define _PAGE_PRESENT	0x0000000000000080	/* Present Page (ie. not swapped out) */
+#define _PAGE_FILE	_AC(0x0000000000001000,UL)	/* Pagecache page     */
+#define _PAGE_MODIFIED	_AC(0x0000000000000800,UL)	/* Modified (dirty)   */
+#define _PAGE_ACCESSED	_AC(0x0000000000000400,UL)	/* Accessed (ref'd)   */
+#define _PAGE_READ	_AC(0x0000000000000200,UL)	/* Readable SW Bit    */
+#define _PAGE_WRITE	_AC(0x0000000000000100,UL)	/* Writable SW Bit    */
+#define _PAGE_PRESENT	_AC(0x0000000000000080,UL)	/* Present            */
 
 #if PAGE_SHIFT == 13
 #define _PAGE_SZBITS	_PAGE_SZ8K
@@ -173,7 +177,8 @@
 
 #define _PFN_MASK	_PAGE_PADDR
 
-#define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | __ACCESS_BITS | _PAGE_E)
+#define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \
+		   __ACCESS_BITS | _PAGE_E)
 
 #define __P000	PAGE_NONE
 #define __P001	PAGE_READONLY
@@ -260,9 +265,12 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
 #define pte_dirty(pte)		(pte_val(pte) & _PAGE_MODIFIED)
 #define pte_young(pte)		(pte_val(pte) & _PAGE_ACCESSED)
 #define pte_wrprotect(pte)	(__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
-#define pte_rdprotect(pte)	(__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
-#define pte_mkclean(pte)	(__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
-#define pte_mkold(pte)		(__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
+#define pte_rdprotect(pte)	\
+	(__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
+#define pte_mkclean(pte)	\
+	(__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
+#define pte_mkold(pte)		\
+	(__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
 
 /* Permanent address of a page. */
 #define __page_address(page)	page_address(page)
@@ -280,11 +288,13 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
 /* Find an entry in the second-level page table.. */
-#define pmd_offset(dir, address)	((pmd_t *) pgd_page(*(dir)) + \
+#define pmd_offset(dir, address)	\
+	((pmd_t *) pgd_page(*(dir)) + \
 	 ((address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD-1)))
 
 /* Find an entry in the third-level page table.. */
-#define pte_index(dir, address)	((pte_t *) __pmd_page(*(dir)) + \
+#define pte_index(dir, address)	\
+	((pte_t *) __pmd_page(*(dir)) + \
 	 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 #define pte_offset_kernel		pte_index
 #define pte_offset_map			pte_index
@@ -305,7 +315,8 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
 static inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
 {
 	pte_t pte;
-	pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE;
+	pte_val(pte) = (((page) | pgprot_val(prot) | _PAGE_E) &
+			~(unsigned long)_PAGE_CACHE);
 	pte_val(pte) |= (((unsigned long)space) << 32);
 	return pte;
 }
@@ -365,7 +376,8 @@ extern unsigned long *sparc64_valid_addr_bitmap;
 #define kern_addr_valid(addr)	\
 	(test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
 
-extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, unsigned long offset,
+extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from,
+			       unsigned long offset,
 			       unsigned long size, pgprot_t prot, int space);
 
 #include <asm-generic/pgtable.h>
@@ -376,7 +388,9 @@ extern int io_remap_page_range(struct vm_area_struct *vma, unsigned long from, u
 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
  * the largest alignment possible such that larget PTEs can be used.
  */
-extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, unsigned long, unsigned long, unsigned long);
+extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
+					  unsigned long, unsigned long,
+					  unsigned long);
 #define HAVE_ARCH_FB_UNMAPPED_AREA
 
 /*

include/asm-sparc64/pstate.h

@@ -2,6 +2,8 @@
 #ifndef _SPARC64_PSTATE_H
 #define _SPARC64_PSTATE_H
 
+#include <asm/const.h>
+
 /* The V9 PSTATE Register (with SpitFire extensions).
  *
  * -----------------------------------------------------------------------
@@ -9,20 +11,20 @@
  * -----------------------------------------------------------------------
  *  63  12  11   10    9     8    7   6   5     4     3     2     1    0
  */
-#define PSTATE_IG	0x0000000000000800	/* Interrupt Globals.		*/
-#define PSTATE_MG	0x0000000000000400	/* MMU Globals.			*/
-#define PSTATE_CLE	0x0000000000000200	/* Current Little Endian.	*/
-#define PSTATE_TLE	0x0000000000000100	/* Trap Little Endian.		*/
-#define PSTATE_MM	0x00000000000000c0	/* Memory Model.		*/
-#define PSTATE_TSO	0x0000000000000000	/* MM: Total Store Order	*/
-#define PSTATE_PSO	0x0000000000000040	/* MM: Partial Store Order	*/
-#define PSTATE_RMO	0x0000000000000080	/* MM: Relaxed Memory Order	*/
-#define PSTATE_RED	0x0000000000000020	/* Reset Error Debug State.	*/
-#define PSTATE_PEF	0x0000000000000010	/* Floating Point Enable.	*/
-#define PSTATE_AM	0x0000000000000008	/* Address Mask.		*/
-#define PSTATE_PRIV	0x0000000000000004	/* Privilege.			*/
-#define PSTATE_IE	0x0000000000000002	/* Interrupt Enable.		*/
-#define PSTATE_AG	0x0000000000000001	/* Alternate Globals.		*/
+#define PSTATE_IG   _AC(0x0000000000000800,UL) /* Interrupt Globals.	*/
+#define PSTATE_MG   _AC(0x0000000000000400,UL) /* MMU Globals.		*/
+#define PSTATE_CLE  _AC(0x0000000000000200,UL) /* Current Little Endian.*/
+#define PSTATE_TLE  _AC(0x0000000000000100,UL) /* Trap Little Endian.	*/
+#define PSTATE_MM   _AC(0x00000000000000c0,UL) /* Memory Model.		*/
+#define PSTATE_TSO  _AC(0x0000000000000000,UL) /* MM: TotalStoreOrder	*/
+#define PSTATE_PSO  _AC(0x0000000000000040,UL) /* MM: PartialStoreOrder	*/
+#define PSTATE_RMO  _AC(0x0000000000000080,UL) /* MM: RelaxedMemoryOrder*/
+#define PSTATE_RED  _AC(0x0000000000000020,UL) /* Reset Error Debug.	*/
+#define PSTATE_PEF  _AC(0x0000000000000010,UL) /* Floating Point Enable.*/
+#define PSTATE_AM   _AC(0x0000000000000008,UL) /* Address Mask.		*/
+#define PSTATE_PRIV _AC(0x0000000000000004,UL) /* Privilege.		*/
+#define PSTATE_IE   _AC(0x0000000000000002,UL) /* Interrupt Enable.	*/
+#define PSTATE_AG   _AC(0x0000000000000001,UL) /* Alternate Globals.	*/
 
 /* The V9 TSTATE Register (with SpitFire and Linux extensions).
  *
@@ -31,35 +33,35 @@
  * ---------------------------------------------------------------
  *  63    40 39   32 31   24 23    20 19       8 7      5 4     0
  */
-#define TSTATE_CCR	0x000000ff00000000	/* Condition Codes.		*/
-#define TSTATE_XCC	0x000000f000000000	/* Condition Codes.		*/
-#define TSTATE_XNEG	0x0000008000000000	/* %xcc Negative.		*/
-#define TSTATE_XZERO	0x0000004000000000	/* %xcc Zero.			*/
-#define TSTATE_XOVFL	0x0000002000000000	/* %xcc Overflow.		*/
-#define TSTATE_XCARRY	0x0000001000000000	/* %xcc Carry.			*/
-#define TSTATE_ICC	0x0000000f00000000	/* Condition Codes.		*/
-#define TSTATE_INEG	0x0000000800000000	/* %icc Negative.		*/
-#define TSTATE_IZERO	0x0000000400000000	/* %icc Zero.			*/
-#define TSTATE_IOVFL	0x0000000200000000	/* %icc Overflow.		*/
-#define TSTATE_ICARRY	0x0000000100000000	/* %icc Carry.			*/
-#define TSTATE_ASI	0x00000000ff000000	/* Address Space Identifier.	*/
-#define TSTATE_PIL	0x0000000000f00000	/* %pil (Linux traps set this)  */
-#define TSTATE_PSTATE	0x00000000000fff00	/* PSTATE.			*/
-#define TSTATE_IG	0x0000000000080000	/* Interrupt Globals.		*/
-#define TSTATE_MG	0x0000000000040000	/* MMU Globals.			*/
-#define TSTATE_CLE	0x0000000000020000	/* Current Little Endian.	*/
-#define TSTATE_TLE	0x0000000000010000	/* Trap Little Endian.		*/
-#define TSTATE_MM	0x000000000000c000	/* Memory Model.		*/
-#define TSTATE_TSO	0x0000000000000000	/* MM: Total Store Order	*/
-#define TSTATE_PSO	0x0000000000004000	/* MM: Partial Store Order	*/
-#define TSTATE_RMO	0x0000000000008000	/* MM: Relaxed Memory Order	*/
-#define TSTATE_RED	0x0000000000002000	/* Reset Error Debug State.	*/
-#define TSTATE_PEF	0x0000000000001000	/* Floating Point Enable.	*/
-#define TSTATE_AM	0x0000000000000800	/* Address Mask.		*/
-#define TSTATE_PRIV	0x0000000000000400	/* Privilege.			*/
-#define TSTATE_IE	0x0000000000000200	/* Interrupt Enable.		*/
-#define TSTATE_AG	0x0000000000000100	/* Alternate Globals.		*/
-#define TSTATE_CWP	0x000000000000001f	/* Current Window Pointer.	*/
+#define TSTATE_CCR	_AC(0x000000ff00000000,UL) /* Condition Codes.	*/
+#define TSTATE_XCC	_AC(0x000000f000000000,UL) /* Condition Codes.	*/
+#define TSTATE_XNEG	_AC(0x0000008000000000,UL) /* %xcc Negative.	*/
+#define TSTATE_XZERO	_AC(0x0000004000000000,UL) /* %xcc Zero.	*/
+#define TSTATE_XOVFL	_AC(0x0000002000000000,UL) /* %xcc Overflow.	*/
+#define TSTATE_XCARRY	_AC(0x0000001000000000,UL) /* %xcc Carry.	*/
+#define TSTATE_ICC	_AC(0x0000000f00000000,UL) /* Condition Codes.	*/
+#define TSTATE_INEG	_AC(0x0000000800000000,UL) /* %icc Negative.	*/
+#define TSTATE_IZERO	_AC(0x0000000400000000,UL) /* %icc Zero.	*/
+#define TSTATE_IOVFL	_AC(0x0000000200000000,UL) /* %icc Overflow.	*/
+#define TSTATE_ICARRY	_AC(0x0000000100000000,UL) /* %icc Carry.	*/
+#define TSTATE_ASI	_AC(0x00000000ff000000,UL) /* AddrSpace ID.	*/
+#define TSTATE_PIL	_AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/
+#define TSTATE_PSTATE	_AC(0x00000000000fff00,UL) /* PSTATE.		*/
+#define TSTATE_IG	_AC(0x0000000000080000,UL) /* Interrupt Globals.*/
+#define TSTATE_MG	_AC(0x0000000000040000,UL) /* MMU Globals.	*/
+#define TSTATE_CLE	_AC(0x0000000000020000,UL) /* CurrLittleEndian.	*/
+#define TSTATE_TLE	_AC(0x0000000000010000,UL) /* TrapLittleEndian.	*/
+#define TSTATE_MM	_AC(0x000000000000c000,UL) /* Memory Model.	*/
+#define TSTATE_TSO	_AC(0x0000000000000000,UL) /* MM: TSO		*/
+#define TSTATE_PSO	_AC(0x0000000000004000,UL) /* MM: PSO		*/
+#define TSTATE_RMO	_AC(0x0000000000008000,UL) /* MM: RMO		*/
+#define TSTATE_RED	_AC(0x0000000000002000,UL) /* Reset Error Debug.*/
+#define TSTATE_PEF	_AC(0x0000000000001000,UL) /* FPU Enable.	*/
+#define TSTATE_AM	_AC(0x0000000000000800,UL) /* Address Mask.	*/
+#define TSTATE_PRIV	_AC(0x0000000000000400,UL) /* Privilege.	*/
+#define TSTATE_IE	_AC(0x0000000000000200,UL) /* Interrupt Enable.	*/
+#define TSTATE_AG	_AC(0x0000000000000100,UL) /* Alternate Globals.*/
+#define TSTATE_CWP	_AC(0x000000000000001f,UL) /* Curr Win-Pointer.	*/
 
 /* Floating-Point Registers State Register.
  *
@@ -68,9 +70,9 @@
  * --------------------------------
  *  63     3    2       1      0
  */
-#define FPRS_FEF	0x0000000000000004	/* Enable Floating Point.	*/
-#define FPRS_DU		0x0000000000000002	/* Dirty Upper.			*/
-#define FPRS_DL		0x0000000000000001	/* Dirty Lower.			*/
+#define FPRS_FEF	_AC(0x0000000000000004,UL) /* FPU Enable.	*/
+#define FPRS_DU		_AC(0x0000000000000002,UL) /* Dirty Upper.	*/
+#define FPRS_DL		_AC(0x0000000000000001,UL) /* Dirty Lower.	*/
 
 /* Version Register.
  *
@@ -79,10 +81,10 @@
  * ------------------------------------------------------
  *  63   48 47  32 31  24 23  16 15    8 7    5 4      0
  */
-#define VERS_MANUF	0xffff000000000000	/* Manufacturer.		*/
-#define VERS_IMPL	0x0000ffff00000000	/* Implementation.		*/
-#define VERS_MASK	0x00000000ff000000	/* Mask Set Revision.		*/
-#define VERS_MAXTL	0x000000000000ff00	/* Maximum Trap Level.		*/
-#define VERS_MAXWIN	0x000000000000001f	/* Maximum Reg Window Index.	*/
+#define VERS_MANUF	_AC(0xffff000000000000,UL) /* Manufacturer.	*/
+#define VERS_IMPL	_AC(0x0000ffff00000000,UL) /* Implementation.	*/
+#define VERS_MASK	_AC(0x00000000ff000000,UL) /* Mask Set Revision.*/
+#define VERS_MAXTL	_AC(0x000000000000ff00,UL) /* Max Trap Level.	*/
+#define VERS_MAXWIN	_AC(0x000000000000001f,UL) /* Max RegWindow Idx.*/
 
 #endif /* !(_SPARC64_PSTATE_H) */