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Commit 4ffd03f5 authored by Raju Lakkaraju's avatar Raju Lakkaraju Committed by David S. Miller
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net: phy: Fixed checkpatch errors for Microsemi PHYs. 

The existing VSC85xx PHY driver did not follow the coding style and caused "checkpatch" to complain. This commit fixes this.
Signed-off-by: default avatarRaju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 05f1b12f
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Showing with 92 additions and 92 deletions
drivers/net/phy/Kconfig
View file @ 4ffd03f5
...@@ -274,9 +274,9 @@ config MICROCHIP_PHY ...@@ -274,9 +274,9 @@ config MICROCHIP_PHY
Supports the LAN88XX PHYs. Supports the LAN88XX PHYs.
config MICROSEMI_PHY config MICROSEMI_PHY
tristate "Microsemi PHYs" tristate "Microsemi PHYs"
---help--- ---help---
Currently supports the VSC8531 and VSC8541 PHYs Currently supports the VSC8531 and VSC8541 PHYs
config NATIONAL_PHY config NATIONAL_PHY
tristate "National Semiconductor PHYs" tristate "National Semiconductor PHYs"
......
drivers/net/phy/mscc.c
View file @ 4ffd03f5
...@@ -13,135 +13,135 @@ ...@@ -13,135 +13,135 @@
#include <linux/phy.h> #include <linux/phy.h>
enum rgmii_rx_clock_delay { enum rgmii_rx_clock_delay {
RGMII_RX_CLK_DELAY_0_2_NS = 0, RGMII_RX_CLK_DELAY_0_2_NS = 0,
RGMII_RX_CLK_DELAY_0_8_NS = 1, RGMII_RX_CLK_DELAY_0_8_NS = 1,
RGMII_RX_CLK_DELAY_1_1_NS = 2, RGMII_RX_CLK_DELAY_1_1_NS = 2,
RGMII_RX_CLK_DELAY_1_7_NS = 3, RGMII_RX_CLK_DELAY_1_7_NS = 3,
RGMII_RX_CLK_DELAY_2_0_NS = 4, RGMII_RX_CLK_DELAY_2_0_NS = 4,
RGMII_RX_CLK_DELAY_2_3_NS = 5, RGMII_RX_CLK_DELAY_2_3_NS = 5,
RGMII_RX_CLK_DELAY_2_6_NS = 6, RGMII_RX_CLK_DELAY_2_6_NS = 6,
RGMII_RX_CLK_DELAY_3_4_NS = 7 RGMII_RX_CLK_DELAY_3_4_NS = 7
}; };
#define MII_VSC85XX_INT_MASK 25 #define MII_VSC85XX_INT_MASK 25
#define MII_VSC85XX_INT_MASK_MASK 0xa000 #define MII_VSC85XX_INT_MASK_MASK 0xa000
#define MII_VSC85XX_INT_STATUS 26 #define MII_VSC85XX_INT_STATUS 26
#define MSCC_EXT_PAGE_ACCESS 31 #define MSCC_EXT_PAGE_ACCESS 31
#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */ #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */ #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
/* Extended Page 2 Registers */ /* Extended Page 2 Registers */
#define MSCC_PHY_RGMII_CNTL 20 #define MSCC_PHY_RGMII_CNTL 20
#define RGMII_RX_CLK_DELAY_MASK 0x0070 #define RGMII_RX_CLK_DELAY_MASK 0x0070
#define RGMII_RX_CLK_DELAY_POS 4 #define RGMII_RX_CLK_DELAY_POS 4
/* Microsemi PHY ID's */ /* Microsemi PHY ID's */
#define PHY_ID_VSC8531 0x00070570 #define PHY_ID_VSC8531 0x00070570
#define PHY_ID_VSC8541 0x00070770 #define PHY_ID_VSC8541 0x00070770
static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page) static int vsc85xx_phy_page_set(struct phy_device *phydev, u8 page)
{ {
int rc; int rc;
rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); rc = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
return rc; return rc;
} }
static int vsc85xx_default_config(struct phy_device *phydev) static int vsc85xx_default_config(struct phy_device *phydev)
{ {
int rc; int rc;
u16 reg_val; u16 reg_val;
mutex_lock(&phydev->lock); mutex_lock(&phydev->lock);
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2); rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_EXTENDED_2);
if (rc != 0) if (rc != 0)
goto out_unlock; goto out_unlock;
reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL); reg_val = phy_read(phydev, MSCC_PHY_RGMII_CNTL);
reg_val &= ~(RGMII_RX_CLK_DELAY_MASK); reg_val &= ~(RGMII_RX_CLK_DELAY_MASK);
reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS); reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS);
phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val); phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val);
rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD);
out_unlock: out_unlock:
mutex_unlock(&phydev->lock); mutex_unlock(&phydev->lock);
return rc; return rc;
} }
static int vsc85xx_config_init(struct phy_device *phydev) static int vsc85xx_config_init(struct phy_device *phydev)
{ {
int rc; int rc;
rc = vsc85xx_default_config(phydev); rc = vsc85xx_default_config(phydev);
if (rc) if (rc)
return rc; return rc;
rc = genphy_config_init(phydev); rc = genphy_config_init(phydev);
return rc; return rc;
} }
static int vsc85xx_ack_interrupt(struct phy_device *phydev) static int vsc85xx_ack_interrupt(struct phy_device *phydev)
{ {
int rc = 0; int rc = 0;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
return (rc < 0) ? rc : 0; return (rc < 0) ? rc : 0;
} }
static int vsc85xx_config_intr(struct phy_device *phydev) static int vsc85xx_config_intr(struct phy_device *phydev)
{ {
int rc; int rc;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
rc = phy_write(phydev, MII_VSC85XX_INT_MASK, rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
MII_VSC85XX_INT_MASK_MASK); MII_VSC85XX_INT_MASK_MASK);
} else { } else {
rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
if (rc < 0) if (rc < 0)
return rc; return rc;
rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
} }
return rc; return rc;
} }
/* Microsemi VSC85xx PHYs */ /* Microsemi VSC85xx PHYs */
static struct phy_driver vsc85xx_driver[] = { static struct phy_driver vsc85xx_driver[] = {
{ {
.phy_id = PHY_ID_VSC8531, .phy_id = PHY_ID_VSC8531,
.name = "Microsemi VSC8531", .name = "Microsemi VSC8531",
.phy_id_mask = 0xfffffff0, .phy_id_mask = 0xfffffff0,
.features = PHY_GBIT_FEATURES, .features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT, .flags = PHY_HAS_INTERRUPT,
.soft_reset = &genphy_soft_reset, .soft_reset = &genphy_soft_reset,
.config_init = &vsc85xx_config_init, .config_init = &vsc85xx_config_init,
.config_aneg = &genphy_config_aneg, .config_aneg = &genphy_config_aneg,
.aneg_done = &genphy_aneg_done, .aneg_done = &genphy_aneg_done,
.read_status = &genphy_read_status, .read_status = &genphy_read_status,
.ack_interrupt = &vsc85xx_ack_interrupt, .ack_interrupt = &vsc85xx_ack_interrupt,
.config_intr = &vsc85xx_config_intr, .config_intr = &vsc85xx_config_intr,
.suspend = &genphy_suspend, .suspend = &genphy_suspend,
.resume = &genphy_resume, .resume = &genphy_resume,
}, },
{ {
.phy_id = PHY_ID_VSC8541, .phy_id = PHY_ID_VSC8541,
.name = "Microsemi VSC8541 SyncE", .name = "Microsemi VSC8541 SyncE",
.phy_id_mask = 0xfffffff0, .phy_id_mask = 0xfffffff0,
.features = PHY_GBIT_FEATURES, .features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT, .flags = PHY_HAS_INTERRUPT,
.soft_reset = &genphy_soft_reset, .soft_reset = &genphy_soft_reset,
.config_init = &vsc85xx_config_init, .config_init = &vsc85xx_config_init,
.config_aneg = &genphy_config_aneg, .config_aneg = &genphy_config_aneg,
.aneg_done = &genphy_aneg_done, .aneg_done = &genphy_aneg_done,
.read_status = &genphy_read_status, .read_status = &genphy_read_status,
.ack_interrupt = &vsc85xx_ack_interrupt, .ack_interrupt = &vsc85xx_ack_interrupt,
.config_intr = &vsc85xx_config_intr, .config_intr = &vsc85xx_config_intr,
.suspend = &genphy_suspend, .suspend = &genphy_suspend,
.resume = &genphy_resume, .resume = &genphy_resume,
} }
}; };
...@@ -149,9 +149,9 @@ static struct phy_driver vsc85xx_driver[] = { ...@@ -149,9 +149,9 @@ static struct phy_driver vsc85xx_driver[] = {
module_phy_driver(vsc85xx_driver); module_phy_driver(vsc85xx_driver);
static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
{ PHY_ID_VSC8531, 0xfffffff0, }, { PHY_ID_VSC8531, 0xfffffff0, },
{ PHY_ID_VSC8541, 0xfffffff0, }, { PHY_ID_VSC8541, 0xfffffff0, },
{ } { }
}; };
MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
......
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