Commit 501be6c1 authored by Thierry Reding's avatar Thierry Reding

drm/tegra: Fix SMMU support on Tegra124 and Tegra210

When testing whether or not to enable the use of the SMMU, consult the
supported DMA mask rather than the actually configured DMA mask, since
the latter might already have been restricted.

Fixes: 2d9384ff ("drm/tegra: Relax IOMMU usage criteria on old Tegra")
Tested-by: default avatarJon Hunter <jonathanh@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 8f3d9f35
...@@ -1039,6 +1039,7 @@ void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, ...@@ -1039,6 +1039,7 @@ void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
static bool host1x_drm_wants_iommu(struct host1x_device *dev) static bool host1x_drm_wants_iommu(struct host1x_device *dev)
{ {
struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
struct iommu_domain *domain; struct iommu_domain *domain;
/* /*
...@@ -1076,7 +1077,7 @@ static bool host1x_drm_wants_iommu(struct host1x_device *dev) ...@@ -1076,7 +1077,7 @@ static bool host1x_drm_wants_iommu(struct host1x_device *dev)
* sufficient and whether or not the host1x is attached to an IOMMU * sufficient and whether or not the host1x is attached to an IOMMU
* doesn't matter. * doesn't matter.
*/ */
if (!domain && dma_get_mask(dev->dev.parent) <= DMA_BIT_MASK(32)) if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
return true; return true;
return domain != NULL; return domain != NULL;
......
...@@ -502,6 +502,19 @@ static void __exit tegra_host1x_exit(void) ...@@ -502,6 +502,19 @@ static void __exit tegra_host1x_exit(void)
} }
module_exit(tegra_host1x_exit); module_exit(tegra_host1x_exit);
/**
* host1x_get_dma_mask() - query the supported DMA mask for host1x
* @host1x: host1x instance
*
* Note that this returns the supported DMA mask for host1x, which can be
* different from the applicable DMA mask under certain circumstances.
*/
u64 host1x_get_dma_mask(struct host1x *host1x)
{
return host1x->info->dma_mask;
}
EXPORT_SYMBOL(host1x_get_dma_mask);
MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
MODULE_DESCRIPTION("Host1x driver for Tegra products"); MODULE_DESCRIPTION("Host1x driver for Tegra products");
......
...@@ -17,9 +17,12 @@ enum host1x_class { ...@@ -17,9 +17,12 @@ enum host1x_class {
HOST1X_CLASS_GR3D = 0x60, HOST1X_CLASS_GR3D = 0x60,
}; };
struct host1x;
struct host1x_client; struct host1x_client;
struct iommu_group; struct iommu_group;
u64 host1x_get_dma_mask(struct host1x *host1x);
/** /**
* struct host1x_client_ops - host1x client operations * struct host1x_client_ops - host1x client operations
* @init: host1x client initialization code * @init: host1x client initialization code
......
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