Commit 52833e89 authored by Trond Myklebust's avatar Trond Myklebust

Merge branch 'linus_origin' into hotfixes

parents 8d042218 4ee29f6a
......@@ -109,6 +109,8 @@ cpu-hotplug.txt
- document describing CPU hotplug support in the Linux kernel.
cpu-load.txt
- document describing how CPU load statistics are collected.
cpuidle/
- info on CPU_IDLE, CPU idle state management subsystem.
cpusets.txt
- documents the cpusets feature; assign CPUs and Mem to a set of tasks.
cputopology.txt
......
Supporting multiple CPU idle levels in kernel
cpuidle
General Information:
Various CPUs today support multiple idle levels that are differentiated
by varying exit latencies and power consumption during idle.
cpuidle is a generic in-kernel infrastructure that separates
idle policy (governor) from idle mechanism (driver) and provides a
standardized infrastructure to support independent development of
governors and drivers.
cpuidle resides under drivers/cpuidle.
Boot options:
"cpuidle_sysfs_switch"
enables current_governor interface in /sys/devices/system/cpu/cpuidle/,
which can be used to switch governors at run time. This boot option
is meant for developer testing only. In normal usage, kernel picks the
best governor based on governor ratings.
SEE ALSO: sysfs.txt in this directory.
Supporting multiple CPU idle levels in kernel
cpuidle drivers
cpuidle driver hooks into the cpuidle infrastructure and handles the
architecture/platform dependent part of CPU idle states. Driver
provides the platform idle state detection capability and also
has mechanisms in place to support actual entry-exit into CPU idle states.
cpuidle driver initializes the cpuidle_device structure for each CPU device
and registers with cpuidle using cpuidle_register_device.
It can also support the dynamic changes (like battery <-> AC), by using
cpuidle_pause_and_lock, cpuidle_disable_device and cpuidle_enable_device,
cpuidle_resume_and_unlock.
Interfaces:
extern int cpuidle_register_driver(struct cpuidle_driver *drv);
extern void cpuidle_unregister_driver(struct cpuidle_driver *drv);
extern int cpuidle_register_device(struct cpuidle_device *dev);
extern void cpuidle_unregister_device(struct cpuidle_device *dev);
extern void cpuidle_pause_and_lock(void);
extern void cpuidle_resume_and_unlock(void);
extern int cpuidle_enable_device(struct cpuidle_device *dev);
extern void cpuidle_disable_device(struct cpuidle_device *dev);
Supporting multiple CPU idle levels in kernel
cpuidle governors
cpuidle governor is policy routine that decides what idle state to enter at
any given time. cpuidle core uses different callbacks to the governor.
* enable() to enable governor for a particular device
* disable() to disable governor for a particular device
* select() to select an idle state to enter
* reflect() called after returning from the idle state, which can be used
by the governor for some record keeping.
More than one governor can be registered at the same time and
users can switch between drivers using /sysfs interface (when enabled).
More than one governor part is supported for developers to easily experiment
with different governors. By default, most optimal governor based on your
kernel configuration and platform will be selected by cpuidle.
Interfaces:
extern int cpuidle_register_governor(struct cpuidle_governor *gov);
extern void cpuidle_unregister_governor(struct cpuidle_governor *gov);
struct cpuidle_governor
Supporting multiple CPU idle levels in kernel
cpuidle sysfs
System global cpuidle related information and tunables are under
/sys/devices/system/cpu/cpuidle
The current interfaces in this directory has self-explanatory names:
* current_driver
* current_governor_ro
With cpuidle_sysfs_switch boot option (meant for developer testing)
following objects are visible instead.
* current_driver
* available_governors
* current_governor
In this case users can switch the governor at run time by writing
to current_governor.
Per logical CPU specific cpuidle information are under
/sys/devices/system/cpu/cpuX/cpuidle
for each online cpu X
--------------------------------------------------------------------------------
# ls -lR /sys/devices/system/cpu/cpu0/cpuidle/
/sys/devices/system/cpu/cpu0/cpuidle/:
total 0
drwxr-xr-x 2 root root 0 Feb 8 10:42 state0
drwxr-xr-x 2 root root 0 Feb 8 10:42 state1
drwxr-xr-x 2 root root 0 Feb 8 10:42 state2
drwxr-xr-x 2 root root 0 Feb 8 10:42 state3
/sys/devices/system/cpu/cpu0/cpuidle/state0:
total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 desc
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
/sys/devices/system/cpu/cpu0/cpuidle/state1:
total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 desc
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
/sys/devices/system/cpu/cpu0/cpuidle/state2:
total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 desc
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
/sys/devices/system/cpu/cpu0/cpuidle/state3:
total 0
-r--r--r-- 1 root root 4096 Feb 8 10:42 desc
-r--r--r-- 1 root root 4096 Feb 8 10:42 latency
-r--r--r-- 1 root root 4096 Feb 8 10:42 name
-r--r--r-- 1 root root 4096 Feb 8 10:42 power
-r--r--r-- 1 root root 4096 Feb 8 10:42 time
-r--r--r-- 1 root root 4096 Feb 8 10:42 usage
--------------------------------------------------------------------------------
* desc : Small description about the idle state (string)
* latency : Latency to exit out of this idle state (in microseconds)
* name : Name of the idle state (string)
* power : Power consumed while in this idle state (in milliwatts)
* time : Total time spent in this idle state (in microseconds)
* usage : Number of times this state was entered (count)
......@@ -1255,8 +1255,8 @@ W: http://linux-net.osdl.org/index.php/DCCP
S: Maintained
DECnet NETWORK LAYER
P: Patrick Caulfield
M: patrick@tykepenguin.com
P: Christine Caulfield
M: christine.caulfield@googlemail.com
W: http://linux-decnet.sourceforge.net
L: linux-decnet-user@lists.sourceforge.net
S: Maintained
......@@ -1318,8 +1318,8 @@ L: linux-kernel@vger.kernel.org
S: Maintained
DISTRIBUTED LOCK MANAGER
P: Patrick Caulfield
M: pcaulfie@redhat.com
P: Christine Caulfield
M: ccaulfie@redhat.com
P: David Teigland
M: teigland@redhat.com
L: cluster-devel@redhat.com
......@@ -1616,6 +1616,7 @@ S: Maintained
FILESYSTEMS (VFS and infrastructure)
P: Alexander Viro
M: viro@zeniv.linux.org.uk
L: linux-fsdevel@vger.kernel.org
S: Maintained
FIREWIRE SUBSYSTEM (drivers/firewire, <linux/firewire*.h>)
......
......@@ -259,8 +259,8 @@ osf_statfs(char __user *path, struct osf_statfs __user *buffer, unsigned long bu
retval = user_path_walk(path, &nd);
if (!retval) {
retval = do_osf_statfs(nd.dentry, buffer, bufsiz);
path_release(&nd);
retval = do_osf_statfs(nd.path.dentry, buffer, bufsiz);
path_put(&nd.path);
}
return retval;
}
......
......@@ -126,15 +126,13 @@ static void decode_address(char *buf, unsigned long address)
struct vm_area_struct *vma = vml->vma;
if (address >= vma->vm_start && address < vma->vm_end) {
char _tmpbuf[256];
char *name = p->comm;
struct file *file = vma->vm_file;
if (file) {
char _tmpbuf[256];
name = d_path(file->f_dentry,
file->f_vfsmnt,
_tmpbuf,
if (file)
name = d_path(&file->f_path, _tmpbuf,
sizeof(_tmpbuf));
}
/* FLAT does not have its text aligned to the start of
* the map while FDPIC ELF does ...
......
This diff is collapsed.
This diff is collapsed.
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,8 +12,6 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,8 +12,6 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y += config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
EXTRA_AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
......@@ -12,9 +12,7 @@
# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
#
ifdef CONFIG_FULLDEBUG
AFLAGS += -DDEBUGGER_COMPATIBLE_CACHE=1
endif
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-$(CONFIG_COLDFIRE) += dma.o entry.o vectors.o
obj-$(CONFIG_M5206) += timers.o
......
......@@ -197,14 +197,13 @@ ENTRY(fasthandler)
RESTORE_LOCAL
ENTRY(ret_from_interrupt)
jeq 2f
1:
RESTORE_ALL
2:
moveb %sp@(PT_SR),%d0
andl #0x7,%d0
jhi 1b
jeq 1f
RESTORE_ALL
1:
/* check if we need to do software interrupts */
movel irq_stat+CPUSTAT_SOFTIRQ_PENDING,%d0
jeq ret_from_exception
......
......@@ -148,25 +148,32 @@ irqreturn_t coldfire_profile_tick(int irq, void *dummy)
/* Reset ColdFire timer2 */
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
if (current->pid)
profile_tick(CPU_PROFILING, regs);
profile_tick(CPU_PROFILING);
return IRQ_HANDLED;
}
/***************************************************************************/
static struct irqaction coldfire_profile_irq = {
.name = "profile timer",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = coldfire_profile_tick,
};
void coldfire_profile_init(void)
{
printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", PROFILEHZ);
printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
PROFILEHZ);
setup_irq(mcf_profilevector, &coldfire_profile_irq);
/* Set up TIMER 2 as high speed profile clock */
__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
__raw_writetrr(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
__raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
request_irq(mcf_profilevector, coldfire_profile_tick,
(IRQF_DISABLED | IRQ_FLG_FAST), "profile timer", NULL);
mcf_settimericr(2, 7);
}
......
......@@ -694,7 +694,7 @@ asmlinkage int irix_statfs(const char __user *path,
if (error)
goto out;
error = vfs_statfs(nd.dentry, &kbuf);
error = vfs_statfs(nd.path.dentry, &kbuf);
if (error)
goto dput_and_out;
......@@ -711,7 +711,7 @@ asmlinkage int irix_statfs(const char __user *path,
}
dput_and_out:
path_release(&nd);
path_put(&nd.path);
out:
return error;
}
......@@ -1360,7 +1360,7 @@ asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf)
error = user_path_walk(fname, &nd);
if (error)
goto out;
error = vfs_statfs(nd.dentry, &kbuf);
error = vfs_statfs(nd.path.dentry, &kbuf);
if (error)
goto dput_and_out;
......@@ -1385,7 +1385,7 @@ asmlinkage int irix_statvfs(char __user *fname, struct irix_statvfs __user *buf)
error |= __put_user(0, &buf->f_fstr[i]);
dput_and_out:
path_release(&nd);
path_put(&nd.path);
out:
return error;
}
......@@ -1611,7 +1611,7 @@ asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *
error = user_path_walk(fname, &nd);
if (error)
goto out;
error = vfs_statfs(nd.dentry, &kbuf);
error = vfs_statfs(nd.path.dentry, &kbuf);
if (error)
goto dput_and_out;
......@@ -1636,7 +1636,7 @@ asmlinkage int irix_statvfs64(char __user *fname, struct irix_statvfs64 __user *
error |= __put_user(0, &buf->f_fstr[i]);
dput_and_out:
path_release(&nd);
path_put(&nd.path);
out:
return error;
}
......
......@@ -219,10 +219,10 @@ asmlinkage long hpux_statfs(const char __user *path,
error = user_path_walk(path, &nd);
if (!error) {
struct hpux_statfs tmp;
error = vfs_statfs_hpux(nd.dentry, &tmp);
error = vfs_statfs_hpux(nd.path.dentry, &tmp);
if (!error && copy_to_user(buf, &tmp, sizeof(tmp)))
error = -EFAULT;
path_release(&nd);
path_put(&nd.path);
}
return error;
}
......
......@@ -442,10 +442,6 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
config WANT_DEVICE_TREE
bool
default n
endmenu
config ISA_DMA_API
......
......@@ -147,6 +147,8 @@ HOSTCFLAGS += -I$(src)/dtc-src/ -I$(src)/libfdt/
targets += dtc-src/dtc-parser.tab.c
targets += dtc-src/dtc-lexer.lex.c
clean-files += dtc-src/dtc-parser.tab.h
ifdef DTC_GENPARSER
BISON = bison
FLEX = flex
......
......@@ -145,7 +145,7 @@
.macro STORE_REGS_5_2
lwz r11, 16(r1)
std r4, 0(r11)
lwz r11, 24(r1)
lwz r11, 20(r1)
std r5, 0(r11)
.endm
......
......@@ -104,3 +104,5 @@ quiet_cmd_systbl_chk = CALL $<
PHONY += systbl_chk
systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i
$(call cmd,systbl_chk)
clean-files := vmlinux.lds
......@@ -462,7 +462,7 @@ void show_regs(struct pt_regs * regs)
current, task_pid_nr(current), current->comm, task_thread_info(current));
#ifdef CONFIG_SMP
printk(" CPU: %d", smp_processor_id());
printk(" CPU: %d", raw_smp_processor_id());
#endif /* CONFIG_SMP */
for (i = 0; i < 32; i++) {
......
......@@ -336,7 +336,7 @@ static unsigned long __init find_function32(struct lib32_elfinfo *lib,
return sym->st_value - VDSO32_LBASE;
}
static int vdso_do_func_patch32(struct lib32_elfinfo *v32,
static int __init vdso_do_func_patch32(struct lib32_elfinfo *v32,
struct lib64_elfinfo *v64,
const char *orig, const char *fix)
{
......@@ -433,7 +433,7 @@ static unsigned long __init find_function64(struct lib64_elfinfo *lib,
#endif
}
static int vdso_do_func_patch64(struct lib32_elfinfo *v32,
static int __init vdso_do_func_patch64(struct lib32_elfinfo *v32,
struct lib64_elfinfo *v64,
const char *orig, const char *fix)
{
......
......@@ -198,14 +198,13 @@ static int release_cached_info(int spu_index)
* dcookie user still being registered (namely, the reader
* of the event buffer).
*/
static inline unsigned long fast_get_dcookie(struct dentry *dentry,
struct vfsmount *vfsmnt)
static inline unsigned long fast_get_dcookie(struct path *path)
{
unsigned long cookie;
if (dentry->d_cookie)
return (unsigned long)dentry;
get_dcookie(dentry, vfsmnt, &cookie);
if (path->dentry->d_cookie)
return (unsigned long)path->dentry;
get_dcookie(path, &cookie);
return cookie;
}
......@@ -240,8 +239,7 @@ get_exec_dcookie_and_offset(struct spu *spu, unsigned int *offsetp,
continue;
if (!(vma->vm_flags & VM_EXECUTABLE))
continue;
app_cookie = fast_get_dcookie(vma->vm_file->f_dentry,
vma->vm_file->f_vfsmnt);
app_cookie = fast_get_dcookie(&vma->vm_file->f_path);
pr_debug("got dcookie for %s\n",
vma->vm_file->f_dentry->d_name.name);
app = vma->vm_file;
......@@ -262,8 +260,7 @@ get_exec_dcookie_and_offset(struct spu *spu, unsigned int *offsetp,
break;
}
*spu_bin_dcookie = fast_get_dcookie(vma->vm_file->f_dentry,
vma->vm_file->f_vfsmnt);
*spu_bin_dcookie = fast_get_dcookie(&vma->vm_file->f_path);
pr_debug("got dcookie for %s\n", vma->vm_file->f_dentry->d_name.name);
up_read(&mm->mmap_sem);
......
......@@ -13,7 +13,6 @@ config MPC5121_ADS
bool "Freescale MPC5121E ADS"
depends on PPC_MULTIPLATFORM && PPC32
select DEFAULT_UIMAGE
select WANT_DEVICE_TREE
select PPC_MPC5121
help
This option enables support for the MPC5121E ADS board.
......
......@@ -8,7 +8,6 @@ config PPC_MPC5200_SIMPLE
bool "Generic support for simple MPC5200 based boards"
depends on PPC_MPC52xx
select DEFAULT_UIMAGE
select WANT_DEVICE_TREE
help
This option enables support for a simple MPC52xx based boards which
do not need a custom platform specific setup. Such boards are
......@@ -35,7 +34,6 @@ config PPC_LITE5200
bool "Freescale Lite5200 Eval Board"
depends on PPC_MPC52xx
select DEFAULT_UIMAGE
select WANT_DEVICE_TREE
config PPC_MPC5200_BUGFIX
bool "MPC5200 (L25R) bugfix support"
......
......@@ -15,7 +15,6 @@ config PPC_MULTIPLATFORM
config PPC_82xx
bool "Freescale 82xx"
depends on 6xx
select WANT_DEVICE_TREE
config PPC_83xx
bool "Freescale 83xx"
......@@ -23,7 +22,6 @@ config PPC_83xx
select FSL_SOC
select MPC83xx
select IPIC
select WANT_DEVICE_TREE
select FSL_EMB_PERFMON
config PPC_86xx
......
......@@ -29,26 +29,22 @@ config PPC_85xx
bool "Freescale 85xx"
select E500
select FSL_SOC
select WANT_DEVICE_TREE
select MPC85xx
config PPC_8xx
bool "Freescale 8xx"
select FSL_SOC
select 8xx
select WANT_DEVICE_TREE
select PPC_LIB_RHEAP
config 40x
bool "AMCC 40x"
select PPC_DCR_NATIVE
select WANT_DEVICE_TREE
select PPC_UDBG_16550
config 44x
bool "AMCC 44x"
select PPC_DCR_NATIVE
select WANT_DEVICE_TREE
select PPC_UDBG_16550
config E200
......
#define DEBUG
/*
* Copyright 2006-2008, IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#undef DEBUG
#include <linux/types.h>
#include <linux/kernel.h>
......
/*
* SPU file system
*
......@@ -592,7 +593,7 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
ret = -EINVAL;
/* check if we are on spufs */
if (nd->dentry->d_sb->s_type != &spufs_type)
if (nd->path.dentry->d_sb->s_type != &spufs_type)
goto out;
/* don't accept undefined flags */
......@@ -600,9 +601,9 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
goto out;
/* only threads can be underneath a gang */
if (nd->dentry != nd->dentry->d_sb->s_root) {
if (nd->path.dentry != nd->path.dentry->d_sb->s_root) {
if ((flags & SPU_CREATE_GANG) ||
!SPUFS_I(nd->dentry->d_inode)->i_gang)
!SPUFS_I(nd->path.dentry->d_inode)->i_gang)
goto out;
}
......@@ -618,16 +619,17 @@ long spufs_create(struct nameidata *nd, unsigned int flags, mode_t mode,
mode &= ~current->fs->umask;
if (flags & SPU_CREATE_GANG)
return spufs_create_gang(nd->dentry->d_inode,
dentry, nd->mnt, mode);
return spufs_create_gang(nd->path.dentry->d_inode,
dentry, nd->path.mnt, mode);
else
return spufs_create_context(nd->dentry->d_inode,
dentry, nd->mnt, flags, mode, filp);
return spufs_create_context(nd->path.dentry->d_inode,
dentry, nd->path.mnt, flags, mode,
filp);
out_dput:
dput(dentry);
out_dir:
mutex_unlock(&nd->dentry->d_inode->i_mutex);
mutex_unlock(&nd->path.dentry->d_inode->i_mutex);
out:
return ret;
}
......
......@@ -73,7 +73,7 @@ static long do_spu_create(const char __user *pathname, unsigned int flags,
LOOKUP_OPEN|LOOKUP_CREATE, &nd);
if (!ret) {
ret = spufs_create(&nd, flags, mode, neighbor);
path_release(&nd);
path_put(&nd.path);
}
putname(tmp);
}
......
......@@ -24,7 +24,6 @@ config STORCENTER
select MPIC
select FSL_SOC
select PPC_UDBG_16550 if SERIAL_8250
select WANT_DEVICE_TREE
select MPC10X_OPENPIC
select MPC10X_BRIDGE
help
......@@ -37,7 +36,6 @@ config MPC7448HPC2
select TSI108_BRIDGE
select DEFAULT_UIMAGE
select PPC_UDBG_16550
select WANT_DEVICE_TREE
select TSI108_BRIDGE
help
Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
......@@ -48,7 +46,6 @@ config PPC_HOLLY
depends on EMBEDDED6xx
select TSI108_BRIDGE
select PPC_UDBG_16550
select WANT_DEVICE_TREE
select TSI108_BRIDGE
help
Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval
......@@ -59,7 +56,6 @@ config PPC_PRPMC2800
depends on EMBEDDED6xx
select MV64X60
select NOT_COHERENT_CACHE
select WANT_DEVICE_TREE
help
This option enables support for the Motorola PrPMC2800 board
......
......@@ -75,7 +75,7 @@ static struct property *new_property(const char *name, int length,
return np;
}
static void __init free_property(struct property *np)
static void free_property(struct property *np)
{
kfree(np);
}
......
......@@ -93,6 +93,9 @@ config ARCH_NO_VIRT_TO_BUS
config ARCH_SUPPORTS_AOUT
def_bool y
config IO_TRAPPED
bool
source "init/Kconfig"
menu "System type"
......@@ -312,6 +315,13 @@ config CPU_SUBTYPE_SH7722
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
config CPU_SUBTYPE_SH7366
bool "Support SH7366 processor"
select CPU_SH4AL_DSP
select CPU_SHX2
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_NUMA
# SH-5 Processor Support
config CPU_SUBTYPE_SH5_101
......@@ -456,6 +466,7 @@ config SH_RTS7751R2D
bool "RTS7751R2D"
depends on CPU_SUBTYPE_SH7751R
select SYS_SUPPORTS_PCI
select IO_TRAPPED
help
Select RTS7751R2D if configuring for a Renesas Technology
Sales SH-Graphics board.
......@@ -472,6 +483,14 @@ config SH_HIGHLANDER
bool "Highlander"
depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
select SYS_SUPPORTS_PCI
select IO_TRAPPED
config SH_MIGOR
bool "Migo-R"
depends on CPU_SUBTYPE_SH7722
help
Select Migo-R if configuring for the SH7722 Migo-R platform
by Renesas System Solutions Asia Pte. Ltd.
config SH_EDOSK7705
bool "EDOSK7705"
......
......@@ -12,6 +12,7 @@ config CPU_LITTLE_ENDIAN
config CPU_BIG_ENDIAN
bool "Big Endian"
depends on !CPU_SH5
endchoice
......@@ -87,9 +88,6 @@ config SH64_ID2815_WORKAROUND
config CPU_HAS_INTEVT
bool
config CPU_HAS_MASKREG_IRQ
bool
config CPU_HAS_IPR_IRQ
bool
......
......@@ -30,6 +30,7 @@ config EARLY_SCIF_CONSOLE_PORT
hex
depends on EARLY_SCIF_CONSOLE
default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
default "0xffe00000" if CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366
default "0xffea0000" if CPU_SUBTYPE_SH7785
default "0xfffe8000" if CPU_SUBTYPE_SH7203
default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
......
......@@ -116,6 +116,7 @@ machdir-$(CONFIG_SH_RTS7751R2D) += renesas/rts7751r2d
machdir-$(CONFIG_SH_7751_SYSTEMH) += renesas/systemh
machdir-$(CONFIG_SH_EDOSK7705) += renesas/edosk7705
machdir-$(CONFIG_SH_HIGHLANDER) += renesas/r7780rp
machdir-$(CONFIG_SH_MIGOR) += renesas/migor
machdir-$(CONFIG_SH_SDK7780) += renesas/sdk7780
machdir-$(CONFIG_SH_7710VOIPGW) += renesas/sh7710voipgw
machdir-$(CONFIG_SH_X3PROTO) += renesas/x3proto
......
/*
* Renesas System Solutions Asia Pte. Ltd - Migo-R
*
* Copyright (C) 2008 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <asm/machvec.h>
#include <asm/io.h>
/* Address IRQ Size Bus Description
* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
*/
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "smc91x-regs" ,
.start = P2SEGADDR(0x10000300),
.end = P2SEGADDR(0x1000030f),
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 32, /* IRQ0 */
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
};
static struct platform_device *migor_devices[] __initdata = {
&smc91x_eth_device,
};
static int __init migor_devices_setup(void)
{
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
__initcall(migor_devices_setup);
static void __init migor_setup(char **cmdline_p)
{
ctrl_outw(0x1000, 0xa4050110); /* Enable IRQ0 in PJCR */
}
static struct sh_machine_vector mv_migor __initmv = {
.mv_name = "Migo-R",
.mv_setup = migor_setup,
};
......@@ -23,6 +23,7 @@
#include <asm/clock.h>
#include <asm/heartbeat.h>
#include <asm/io.h>
#include <asm/io_trapped.h>
static struct resource r8a66597_usb_host_resources[] = {
[0] = {
......@@ -181,13 +182,27 @@ static struct platform_device *r7780rp_devices[] __initdata = {
&m66592_usb_peripheral_device,
&heartbeat_device,
#ifndef CONFIG_SH_R7780RP
&cf_ide_device,
&ax88796_device,
#endif
};
/*
* The CF is connected using a 16-bit bus where 8-bit operations are
* unsupported. The linux ata driver is however using 8-bit operations, so
* insert a trapped io filter to convert 8-bit operations into 16-bit.
*/
static struct trapped_io cf_trapped_io = {
.resource = cf_ide_resources,
.num_resources = 2,
.minimum_bus_width = 16,
};
static int __init r7780rp_devices_setup(void)
{
#ifndef CONFIG_SH_R7780RP
if (register_trapped_io(&cf_trapped_io) == 0)
platform_device_register(&cf_ide_device);
#endif
return platform_add_devices(r7780rp_devices,
ARRAY_SIZE(r7780rp_devices));
}
......@@ -226,34 +241,6 @@ static void r7780rp_power_off(void)
ctrl_outw(0x0001, PA_POFF);
}
static inline unsigned char is_ide_ioaddr(unsigned long addr)
{
return ((cf_ide_resources[0].start <= addr &&
addr <= cf_ide_resources[0].end) ||
(cf_ide_resources[1].start <= addr &&
addr <= cf_ide_resources[1].end));
}
void highlander_writeb(u8 b, void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
ctrl_outw((u16)b, tmp);
else
ctrl_outb(b, tmp);
}
u8 highlander_readb(void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
return ctrl_inw(tmp) & 0xff;
else
return ctrl_inb(tmp);
}
/*
* Initialize the board
*/
......@@ -338,6 +325,4 @@ static struct sh_machine_vector mv_highlander __initmv = {
.mv_setup = highlander_setup,
.mv_init_irq = highlander_init_irq,
.mv_irq_demux = highlander_irq_demux,
.mv_readb = highlander_readb,
.mv_writeb = highlander_writeb,
};
......@@ -21,6 +21,7 @@
#include <asm/machvec.h>
#include <asm/rts7751r2d.h>
#include <asm/io.h>
#include <asm/io_trapped.h>
#include <asm/spi.h>
static struct resource cf_ide_resources[] = {
......@@ -214,13 +215,25 @@ static struct platform_device *rts7751r2d_devices[] __initdata = {
&uart_device,
&sm501_device,
#endif
&cf_ide_device,
&heartbeat_device,
&spi_sh_sci_device,
};
/*
* The CF is connected with a 16-bit bus where 8-bit operations are
* unsupported. The linux ata driver is however using 8-bit operations, so
* insert a trapped io filter to convert 8-bit operations into 16-bit.
*/
static struct trapped_io cf_trapped_io = {
.resource = cf_ide_resources,
.num_resources = 2,
.minimum_bus_width = 16,
};
static int __init rts7751r2d_devices_setup(void)
{
if (register_trapped_io(&cf_trapped_io) == 0)
platform_device_register(&cf_ide_device);
spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
return platform_add_devices(rts7751r2d_devices,
ARRAY_SIZE(rts7751r2d_devices));
......@@ -232,34 +245,6 @@ static void rts7751r2d_power_off(void)
ctrl_outw(0x0001, PA_POWOFF);
}
static inline unsigned char is_ide_ioaddr(unsigned long addr)
{
return ((cf_ide_resources[0].start <= addr &&
addr <= cf_ide_resources[0].end) ||
(cf_ide_resources[1].start <= addr &&
addr <= cf_ide_resources[1].end));
}
void rts7751r2d_writeb(u8 b, void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
ctrl_outw((u16)b, tmp);
else
ctrl_outb(b, tmp);
}
u8 rts7751r2d_readb(void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
return ctrl_inw(tmp) & 0xff;
else
return ctrl_inb(tmp);
}
/*
* Initialize the board
*/
......@@ -310,6 +295,4 @@ static struct sh_machine_vector mv_rts7751r2d __initmv = {
.mv_setup = rts7751r2d_setup,
.mv_init_irq = init_rts7751r2d_IRQ,
.mv_irq_demux = rts7751r2d_irq_demux,
.mv_writeb = rts7751r2d_writeb,
.mv_readb = rts7751r2d_readb,
};
......@@ -4,13 +4,6 @@ choice
prompt "SDK7780 options"
default SH_SDK7780_BASE
config SH_SDK7780_STANDALONE
bool "SDK7780 board support"
depends on CPU_SUBTYPE_SH7780
help
Selecting this option will enable support for the
standalone version of the SDK7780. If in doubt, say Y.
config SH_SDK7780_BASE
bool "SDK7780 with base-board support"
depends on CPU_SUBTYPE_SH7780
......
......@@ -17,10 +17,8 @@
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hd64465/hd64465.h>
static void disable_hd64465_irq(unsigned int irq)
......@@ -34,7 +32,6 @@ static void disable_hd64465_irq(unsigned int irq)
outw(nimr, HD64465_REG_NIMR);
}
static void enable_hd64465_irq(unsigned int irq)
{
unsigned short nimr;
......@@ -46,33 +43,28 @@ static void enable_hd64465_irq(unsigned int irq)
outw(nimr, HD64465_REG_NIMR);
}
static void mask_and_ack_hd64465(unsigned int irq)
{
disable_hd64465_irq(irq);
}
static void end_hd64465_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_hd64465_irq(irq);
}
static unsigned int startup_hd64465_irq(unsigned int irq)
{
enable_hd64465_irq(irq);
return 0;
}
static void shutdown_hd64465_irq(unsigned int irq)
{
disable_hd64465_irq(irq);
}
static struct hw_interrupt_type hd64465_irq_type = {
.typename = "HD64465-IRQ",
.startup = startup_hd64465_irq,
......@@ -83,7 +75,6 @@ static struct hw_interrupt_type hd64465_irq_type = {
.end = end_hd64465_irq,
};
static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
{
printk(KERN_INFO
......@@ -93,9 +84,6 @@ static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
return IRQ_NONE;
}
/*====================================================*/
/*
* Support for a secondary IRQ demux step. This is necessary
* because the HD64465 presents a very thin interface to the
......@@ -103,8 +91,7 @@ static irqreturn_t hd64465_interrupt(int irq, void *dev_id)
* normally done in hardware by other PCMCIA host bridges is
* instead done in software.
*/
static struct
{
static struct {
int (*func)(int, void *);
void *dev;
} hd64465_demux[HD64465_IRQ_NUM];
......@@ -123,8 +110,6 @@ void hd64465_unregister_irq_demux(int irq)
}
EXPORT_SYMBOL(hd64465_unregister_irq_demux);
int hd64465_irq_demux(int irq)
{
if (irq == CONFIG_HD64465_IRQ) {
......@@ -154,7 +139,6 @@ static struct irqaction irq0 = {
.name = "HD64465",
};
static int __init setup_hd64465(void)
{
int i;
......@@ -185,16 +169,13 @@ static int __init setup_hd64465(void)
setup_irq(CONFIG_HD64465_IRQ, &irq0);
#ifdef CONFIG_SERIAL
/* wake up the UART from STANDBY at this point */
smscr = inw(HD64465_REG_SMSCR);
outw(smscr & (~HD64465_SMSCR_UARTST), HD64465_REG_SMSCR);
/* remap IO ports for first ISA serial port to HD64465 UART */
hd64465_port_map(0x3f8, 8, CONFIG_HD64465_IOBASE + 0x8000, 1);
#endif
return 0;
}
module_init(setup_hd64465);
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......@@ -231,7 +231,6 @@ CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_SH_DSP is not set
# CONFIG_SH_ADC is not set
CONFIG_CPU_HAS_INTEVT=y
CONFIG_CPU_HAS_PINT_IRQ=y
CONFIG_CPU_HAS_IPR_IRQ=y
CONFIG_CPU_HAS_SR_RB=y
......
......@@ -350,7 +350,7 @@ int register_dmac(struct dma_info *info)
BUG_ON((info->flags & DMAC_CHANNELS_CONFIGURED) && !info->channels);
info->pdev = platform_device_register_simple((char *)info->name, -1,
info->pdev = platform_device_register_simple(info->name, -1,
NULL, 0);
if (IS_ERR(info->pdev))
return PTR_ERR(info->pdev);
......
......@@ -18,7 +18,7 @@ int pci_fixup_pcic(void)
{
unsigned long bcr1, mcr;
bcr1 = inl(SH7751_BCR1);
bcr1 = ctrl_inl(SH7751_BCR1);
bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
pci_write_reg(bcr1, SH4_PCIBCR1);
......@@ -28,7 +28,7 @@ int pci_fixup_pcic(void)
pci_write_reg(0xfb900047, SH7751_PCICONF1);
pci_write_reg(0xab000001, SH7751_PCICONF4);
mcr = inl(SH7751_MCR);
mcr = ctrl_inl(SH7751_MCR);
mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
pci_write_reg(mcr, SH4_PCIMCR);
......
......@@ -19,7 +19,7 @@ int pci_fixup_pcic(void)
{
unsigned long bcr1, mcr;
bcr1 = inl(SH7751_BCR1);
bcr1 = ctrl_inl(SH7751_BCR1);
bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
pci_write_reg(bcr1, SH4_PCIBCR1);
......@@ -30,7 +30,7 @@ int pci_fixup_pcic(void)
pci_write_reg(0xfb900047, SH7751_PCICONF1);
pci_write_reg(0xab000001, SH7751_PCICONF4);
mcr = inl(SH7751_MCR);
mcr = ctrl_inl(SH7751_MCR);
mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
pci_write_reg(mcr, SH4_PCIMCR);
......
......@@ -83,9 +83,9 @@ static int gapspci_read(struct pci_bus *bus, unsigned int devfn, int where, int
return PCIBIOS_DEVICE_NOT_FOUND;
switch (size) {
case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break;
case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break;
case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break;
case 1: *val = ctrl_inb(GAPSPCI_BBA_CONFIG+where); break;
case 2: *val = ctrl_inw(GAPSPCI_BBA_CONFIG+where); break;
case 4: *val = ctrl_inl(GAPSPCI_BBA_CONFIG+where); break;
}
return PCIBIOS_SUCCESSFUL;
......@@ -97,9 +97,9 @@ static int gapspci_write(struct pci_bus *bus, unsigned int devfn, int where, int
return PCIBIOS_DEVICE_NOT_FOUND;
switch (size) {
case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break;
case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break;
case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break;
case 1: ctrl_outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break;
case 2: ctrl_outw((u16)val, GAPSPCI_BBA_CONFIG+where); break;
case 4: ctrl_outl((u32)val, GAPSPCI_BBA_CONFIG+where); break;
}
return PCIBIOS_SUCCESSFUL;
......@@ -127,36 +127,36 @@ int __init gapspci_init(void)
*/
for (i=0; i<16; i++)
idbuf[i] = inb(GAPSPCI_REGS+i);
idbuf[i] = ctrl_inb(GAPSPCI_REGS+i);
if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
return -ENODEV;
outl(0x5a14a501, GAPSPCI_REGS+0x18);
ctrl_outl(0x5a14a501, GAPSPCI_REGS+0x18);
for (i=0; i<1000000; i++)
;
if (inl(GAPSPCI_REGS+0x18) != 1)
if (ctrl_inl(GAPSPCI_REGS+0x18) != 1)
return -EINVAL;
outl(0x01000000, GAPSPCI_REGS+0x20);
outl(0x01000000, GAPSPCI_REGS+0x24);
ctrl_outl(0x01000000, GAPSPCI_REGS+0x20);
ctrl_outl(0x01000000, GAPSPCI_REGS+0x24);
outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
ctrl_outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
ctrl_outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
outl(1, GAPSPCI_REGS+0x14);
outl(1, GAPSPCI_REGS+0x34);
ctrl_outl(1, GAPSPCI_REGS+0x14);
ctrl_outl(1, GAPSPCI_REGS+0x34);
/* Setting Broadband Adapter */
outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
ctrl_outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
ctrl_outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
ctrl_outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
ctrl_outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
ctrl_outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
ctrl_outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
ctrl_outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
return 0;
}
......
......@@ -33,7 +33,7 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
static struct resource sh7751_io_resource = {
.name = "SH7751_IO",
.start = 0x4000,
.end = 0x4000 + SH7751_PCI_IO_SIZE - 1,
.end = SH7751_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO
};
......@@ -68,6 +68,7 @@ static struct sh4_pci_address_map sh7751_pci_map = {
int __init pcibios_init_platform(void)
{
__set_io_port_base(SH7751_PCI_IO_BASE);
return sh7751_pcic_init(&sh7751_pci_map);
}
......@@ -172,11 +172,11 @@ struct sh4_pci_address_map {
static inline void pci_write_reg(unsigned long val, unsigned long reg)
{
outl(val, PCI_REG(reg));
ctrl_outl(val, PCI_REG(reg));
}
static inline unsigned long pci_read_reg(unsigned long reg)
{
return inl(PCI_REG(reg));
return ctrl_inl(PCI_REG(reg));
}
#endif /* __PCI_SH4_H */
......@@ -58,7 +58,7 @@ static int __init __area_sdram_check(unsigned int area)
{
u32 word;
word = inl(SH7751_BCR1);
word = ctrl_inl(SH7751_BCR1);
/* check BCR for SDRAM in area */
if (((word >> area) & 1) == 0) {
printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
......@@ -67,7 +67,7 @@ static int __init __area_sdram_check(unsigned int area)
}
pci_write_reg(word, SH4_PCIBCR1);
word = (u16)inw(SH7751_BCR2);
word = (u16)ctrl_inw(SH7751_BCR2);
/* check BCR2 for 32bit SDRAM interface*/
if (((word >> (area << 1)) & 0x3) != 0x3) {
printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
......@@ -85,9 +85,9 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
u32 word;
/* Set the BCR's to enable PCI access */
reg = inl(SH7751_BCR1);
reg = ctrl_inl(SH7751_BCR1);
reg |= 0x80000;
outl(reg, SH7751_BCR1);
ctrl_outl(reg, SH7751_BCR1);
/* Turn the clocks back on (not done in reset)*/
pci_write_reg(0, SH4_PCICLKR);
......@@ -179,13 +179,13 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
return 0;
/* configure the wait control registers */
word = inl(SH7751_WCR1);
word = ctrl_inl(SH7751_WCR1);
pci_write_reg(word, SH4_PCIWCR1);
word = inl(SH7751_WCR2);
word = ctrl_inl(SH7751_WCR2);
pci_write_reg(word, SH4_PCIWCR2);
word = inl(SH7751_WCR3);
word = ctrl_inl(SH7751_WCR3);
pci_write_reg(word, SH4_PCIWCR3);
word = inl(SH7751_MCR);
word = ctrl_inl(SH7751_MCR);
pci_write_reg(word, SH4_PCIMCR);
/* NOTE: I'm ignoring the PCI error IRQs for now..
......
......@@ -52,7 +52,7 @@ static int __init sh7780_pci_init(void)
pr_debug("PCI: Starting intialization.\n");
outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
/* check for SH7780/SH7780R hardware */
id = pci_read_reg(SH7780_PCIVID);
......
......@@ -22,5 +22,6 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_BINFMT_ELF) += dump_task.o
obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
EXTRA_CFLAGS += -Werror
......@@ -18,5 +18,6 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_BINFMT_ELF) += dump_task.o
obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
EXTRA_CFLAGS += -Werror
......@@ -6,4 +6,3 @@ obj-y += intc.o
obj-$(CONFIG_SUPERH32) += imask.o
obj-$(CONFIG_CPU_SH5) += intc-sh5.o
obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
......@@ -75,21 +75,6 @@ int intc_evt_to_irq[(0xE20/0x20)+1] = {
-1, -1 /* 0xE00 - 0xE20 */
};
/*
* Opposite mapper.
*/
static int IRQ_to_vectorN[NR_INTC_IRQS] = {
0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /* 0- 7 */
-1, -1, -1, -1, 0x50, 0x51, 0x52, 0x53, /* 8-15 */
0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36, -1, /* 16-23 */
-1, -1, -1, -1, -1, -1, -1, -1, /* 24-31 */
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
0x39, 0x3A, 0x3B, -1, -1, -1, -1, -1, /* 40-47 */
-1, -1, -1, -1, -1, -1, -1, -1, /* 48-55 */
-1, -1, -1, -1, -1, -1, -1, 0x2B, /* 56-63 */
};
static unsigned long intc_virt;
static unsigned int startup_intc_irq(unsigned int irq);
......@@ -176,6 +161,18 @@ void make_intc_irq(unsigned int irq)
}
#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
static int IRQ_to_vectorN[NR_INTC_IRQS] = {
0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /* 0- 7 */
-1, -1, -1, -1, 0x50, 0x51, 0x52, 0x53, /* 8-15 */
0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36, -1, /* 16-23 */
-1, -1, -1, -1, -1, -1, -1, -1, /* 24-31 */
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
0x39, 0x3A, 0x3B, -1, -1, -1, -1, -1, /* 40-47 */
-1, -1, -1, -1, -1, -1, -1, -1, /* 48-55 */
-1, -1, -1, -1, -1, -1, -1, 0x2B, /* 56-63 */
};
int intc_irq_describe(char* p, int irq)
{
if (irq < NR_INTC_IRQS)
......
/*
* Interrupt handling for Simple external interrupt mask register
*
* Copyright (C) 2001 A&D Co., Ltd. <http://www.aandd.co.jp>
*
* This is for the machine which have single 16 bit register
* for masking external IRQ individually.
* Each bit of the register is for masking each interrupt.
*
* This file may be copied or modified under the terms of the GNU
* General Public License. See linux/COPYING for more information.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/system.h>
#include <asm/io.h>
/* address of external interrupt mask register */
unsigned long irq_mask_register;
/* forward declaration */
static unsigned int startup_maskreg_irq(unsigned int irq);
static void shutdown_maskreg_irq(unsigned int irq);
static void enable_maskreg_irq(unsigned int irq);
static void disable_maskreg_irq(unsigned int irq);
static void mask_and_ack_maskreg(unsigned int);
static void end_maskreg_irq(unsigned int irq);
/* hw_interrupt_type */
static struct hw_interrupt_type maskreg_irq_type = {
.typename = "Mask Register",
.startup = startup_maskreg_irq,
.shutdown = shutdown_maskreg_irq,
.enable = enable_maskreg_irq,
.disable = disable_maskreg_irq,
.ack = mask_and_ack_maskreg,
.end = end_maskreg_irq
};
/* actual implementation */
static unsigned int startup_maskreg_irq(unsigned int irq)
{
enable_maskreg_irq(irq);
return 0; /* never anything pending */
}
static void shutdown_maskreg_irq(unsigned int irq)
{
disable_maskreg_irq(irq);
}
static void disable_maskreg_irq(unsigned int irq)
{
unsigned short val, mask = 0x01 << irq;
BUG_ON(!irq_mask_register);
/* Set "irq"th bit */
val = ctrl_inw(irq_mask_register);
val |= mask;
ctrl_outw(val, irq_mask_register);
}
static void enable_maskreg_irq(unsigned int irq)
{
unsigned short val, mask = ~(0x01 << irq);
BUG_ON(!irq_mask_register);
/* Clear "irq"th bit */
val = ctrl_inw(irq_mask_register);
val &= mask;
ctrl_outw(val, irq_mask_register);
}
static void mask_and_ack_maskreg(unsigned int irq)
{
disable_maskreg_irq(irq);
}
static void end_maskreg_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_maskreg_irq(irq);
}
void make_maskreg_irq(unsigned int irq)
{
disable_irq_nosync(irq);
irq_desc[irq].handler = &maskreg_irq_type;
disable_maskreg_irq(irq);
}
......@@ -126,12 +126,18 @@ int __init detect_cpu_and_cache_system(void)
CPU_HAS_LLSC;
break;
case 0x3008:
if (prr == 0xa0) {
if (prr == 0xa0 || prr == 0xa1) {
boot_cpu_data.type = CPU_SH7722;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.flags |= CPU_HAS_LLSC;
}
else if (prr == 0x70) {
boot_cpu_data.type = CPU_SH7366;
boot_cpu_data.icache.ways = 4;
boot_cpu_data.dcache.ways = 4;
boot_cpu_data.flags |= CPU_HAS_LLSC;
}
break;
case 0x4000: /* 1st cut */
case 0x4001: /* 2nd cut */
......
......@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
# SMP setup
......@@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
obj-y += $(clock-y)
......
/*
* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
*
* SH7722 support for the clock framework
* SH7722 & SH7366 support for the clock framework
*
* Copyright (c) 2006-2007 Nomad Global Solutions Inc
* Based on code for sh7343 by Paul Mundt
......@@ -417,15 +417,19 @@ static int sh7722_siu_which(struct clk *clk)
return 0;
if (!strcmp(clk->name, "siu_b_clk"))
return 1;
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
if (!strcmp(clk->name, "irda_clk"))
return 2;
#endif
return -EINVAL;
}
static unsigned long sh7722_siu_regs[] = {
[0] = SCLKACR,
[1] = SCLKBCR,
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
[2] = IrDACLKCR,
#endif
};
static int sh7722_siu_start_stop(struct clk *clk, int enable)
......@@ -571,10 +575,12 @@ static struct clk sh7722_siu_b_clock = {
.ops = &sh7722_siu_clk_ops,
};
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
static struct clk sh7722_irda_clock = {
.name = "irda_clk",
.ops = &sh7722_siu_clk_ops,
};
#endif
static struct clk sh7722_video_clock = {
.name = "video_clk",
......@@ -588,7 +594,9 @@ static struct clk *sh7722_clocks[] = {
&sh7722_sdram_clock,
&sh7722_siu_a_clock,
&sh7722_siu_b_clock,
#if defined(CONFIG_CPU_SUBTYPE_SH7722)
&sh7722_irda_clock,
#endif
&sh7722_video_clock,
};
......
/*
* SH7366 Setup
*
* Copyright (C) 2008 Renesas Solutions
*
* Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <asm/sci.h>
static struct plat_sci_port sci_platform_data[] = {
{
.mapbase = 0xffe00000,
.flags = UPF_BOOT_AUTOCONF,
.type = PORT_SCIF,
.irqs = { 80, 80, 80, 80 },
}, {
.flags = 0,
}
};
static struct platform_device sci_device = {
.name = "sh-sci",
.id = -1,
.dev = {
.platform_data = sci_platform_data,
},
};
static struct platform_device *sh7366_devices[] __initdata = {
&sci_device,
};
static int __init sh7366_devices_setup(void)
{
return platform_add_devices(sh7366_devices,
ARRAY_SIZE(sh7366_devices));
}
__initcall(sh7366_devices_setup);
enum {
UNUSED=0,
/* interrupt sources */
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
ICB,
DMAC0, DMAC1, DMAC2, DMAC3,
VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
MFI, VPU, USB,
MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
DMAC4, DMAC5, DMAC_DADERR,
SCIF, SCIFA1, SCIFA2,
DENC, MSIOF,
FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
SDHI0, SDHI1, SDHI2, SDHI3,
CMT, TSIF, SIU,
TMU0, TMU1, TMU2,
VEU2, LCDC,
/* interrupt groups */
DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI,
};
static struct intc_vect vectors[] __initdata = {
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
INTC_VECT(ICB, 0x700),
INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
INTC_VECT(MMC_MMC3I, 0xb40),
INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
INTC_VECT(DMAC_DADERR, 0xbc0),
INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
INTC_VECT(SCIFA2, 0xc40),
INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
INTC_VECT(SIU, 0xf80),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2, 0x440),
INTC_VECT(VEU2, 0x580), INTC_VECT(LCDC, 0x580),
};
static struct intc_group groups[] __initdata = {
INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
};
static struct intc_mask_reg mask_registers[] __initdata = {
{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
{ } },
{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
{ 0, 0, 0, ICB } },
{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
{ 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
{ 0, 0, 0, 0, 0, 0, 0, MSIOF } },
{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
{ 0, 0, 0, CMT, 0, USB, } },
{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
{ 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
{ 0, 0, 0, 0, 0, 0, 0, TSIF } },
{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_prio_reg prio_registers[] __initdata = {
{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static struct intc_sense_reg sense_registers[] __initdata = {
{ 0xa414001c, 16, 2, /* ICR1 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};
static DECLARE_INTC_DESC(intc_desc, "sh7366", vectors, groups,
mask_registers, prio_registers, sense_registers);
void __init plat_irq_setup(void)
{
register_intc_controller(&intc_desc);
}
void __init plat_mem_setup(void)
{
/* TODO: Register Node 1 */
}
......@@ -20,19 +20,18 @@ int __init detect_cpu_and_cache_system(void)
{
unsigned long long cir;
/* Do peeks in real mode to avoid having to set up a mapping for the
WPC registers. On SH5-101 cut2, such a mapping would be exposed to
an address translation erratum which would make it hard to set up
correctly. */
/*
* Do peeks in real mode to avoid having to set up a mapping for
* the WPC registers. On SH5-101 cut2, such a mapping would be
* exposed to an address translation erratum which would make it
* hard to set up correctly.
*/
cir = peek_real_address_q(0x0d000008);
if ((cir & 0xffff) == 0x5103) {
if ((cir & 0xffff) == 0x5103)
boot_cpu_data.type = CPU_SH5_103;
} else if (((cir >> 32) & 0xffff) == 0x51e2) {
else if (((cir >> 32) & 0xffff) == 0x51e2)
/* CPU.VCR aliased at CIR address on SH5-101 */
boot_cpu_data.type = CPU_SH5_101;
} else {
boot_cpu_data.type = CPU_SH_NONE;
}
/*
* First, setup some sane values for the I-cache.
......@@ -40,37 +39,33 @@ int __init detect_cpu_and_cache_system(void)
boot_cpu_data.icache.ways = 4;
boot_cpu_data.icache.sets = 256;
boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
boot_cpu_data.icache.way_incr = (1 << 13);
boot_cpu_data.icache.entry_shift = 5;
boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets *
boot_cpu_data.icache.linesz;
boot_cpu_data.icache.entry_mask = 0x1fe0;
boot_cpu_data.icache.flags = 0;
#if 0
/*
* FIXME: This can probably be cleaned up a bit as well.. for example,
* do we really need the way shift _and_ the way_step_shift ?? Judging
* by the existing code, I would guess no.. is there any valid reason
* why we need to be tracking this around?
* Next, setup some sane values for the D-cache.
*
* On the SH5, these are pretty consistent with the I-cache settings,
* so we just copy over the existing definitions.. these can be fixed
* up later, especially if we add runtime CPU probing.
*
* Though in the meantime it saves us from having to duplicate all of
* the above definitions..
*/
boot_cpu_data.icache.way_shift = 13;
boot_cpu_data.icache.entry_shift = 5;
boot_cpu_data.icache.set_shift = 4;
boot_cpu_data.icache.way_step_shift = 16;
boot_cpu_data.icache.asid_shift = 2;
boot_cpu_data.dcache = boot_cpu_data.icache;
/*
* way offset = cache size / associativity, so just don't factor in
* associativity in the first place..
* Setup any cache-related flags here
*/
boot_cpu_data.icache.way_ofs = boot_cpu_data.icache.sets *
boot_cpu_data.icache.linesz;
boot_cpu_data.icache.asid_mask = 0x3fc;
boot_cpu_data.icache.idx_mask = 0x1fe0;
boot_cpu_data.icache.epn_mask = 0xffffe000;
#if defined(CONFIG_CACHE_WRITETHROUGH)
set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags));
#elif defined(CONFIG_CACHE_WRITEBACK)
set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
#endif
boot_cpu_data.icache.flags = 0;
/* A trivial starting point.. */
memcpy(&boot_cpu_data.dcache,
&boot_cpu_data.icache, sizeof(struct cache_info));
return 0;
}
......@@ -63,7 +63,13 @@ EXPORT_SYMBOL(memset_io);
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return sh_mv.mv_ioport_map(port, nr);
void __iomem *ret;
ret = __ioport_map_trapped(port, nr);
if (ret)
return ret;
return __ioport_map(port, nr);
}
EXPORT_SYMBOL(ioport_map);
......
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......@@ -248,9 +248,6 @@ asmlinkage void do_softirq(void)
void __init init_IRQ(void)
{
#ifdef CONFIG_CPU_HAS_PINT_IRQ
init_IRQ_pint();
#endif
plat_irq_setup();
/* Perform the machine specific initialisation */
......
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......@@ -45,3 +45,5 @@ MAGICPANELR2 SH_MAGIC_PANEL_R2
R2D_PLUS RTS7751R2D_PLUS
R2D_1 RTS7751R2D_1
CAYMAN SH_CAYMAN
SDK7780 SH_SDK7780
MIGOR SH_MIGOR
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