Commit 52ccd492 authored by Shawn Guo's avatar Shawn Guo

ARM: dts: imx6q: sort iomuxc sub-nodes in name

Sort iomuxc sub-nodes in name so that the node can be located a little
bit easier.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent e30ba89f
...@@ -522,6 +522,16 @@ pinctrl_audmux_1: audmux-1 { ...@@ -522,6 +522,16 @@ pinctrl_audmux_1: audmux-1 {
}; };
}; };
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
>;
};
};
gpmi-nand { gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 { pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = < fsl,pins = <
...@@ -599,16 +609,6 @@ pinctrl_usdhc4_1: usdhc4grp-1 { ...@@ -599,16 +609,6 @@ pinctrl_usdhc4_1: usdhc4grp-1 {
>; >;
}; };
}; };
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
>;
};
};
}; };
dcic@020e4000 { /* DCIC1 */ dcic@020e4000 { /* DCIC1 */
......
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