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Commit 5344df63 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-arm64-dt-for-v4.12' of... 

Merge tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC DT Updates for v4.12

Cleanup:
* Drop superfluous status update for frequency override from all
  r8a779[56] boards
* Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
* Remove unit-address and reg from integrated cache on r8a779[56] SoCs

Enhancements:
* Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
* Add Cortex-A53 CPU cores to r8a7795 SoC
* Update memory node to 4 GiB map on h3ulcb board
* Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
* Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
* Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
* Set drive-strength for ravb pins for r8a7795/salvator-x board
* Enable gigabit ethernet on r8a779[56]/salvator-x boards
* Enable I2C for DVFS device r8a779[56]/salvator-x boards

* tag 'renesas-arm64-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
  arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override
  arm64: dts: m3ulcb: Drop superfluous status update for frequency override
  arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides
  arm64: dts: h3ulcb: Drop superfluous status update for frequency override
  arm64: dts: r8a7796: Add Cortex-A53 PMU node
  arm64: dts: r8a7796: Add Cortex-A53 CPU cores
  arm64: dts: r8a7796: Add CA53 L2 cache-controller node
  arm64: dts: r8a7796: Add Cortex-A57 PMU node
  arm64: dts: r8a7796: Add Cortex-A57 CPU cores
  arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC
  arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins
  arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
  arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches
  arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM
  arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM
  arm64: dts: r8a7795: Add Cortex-A53 PMU node
  arm64: dts: r8a7795: Add Cortex-A53 CPU cores
  arm64: dts: r8a7796: Enable HSCIF DMA
  arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1)
  arm64: dts: r8a7796: Enable SCIF DMA
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7df6fcfb 3cbe3336
Expand all Show whitespace changes
Inline Side-by-side
Showing with 384 additions and 66 deletions
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
View file @ 5344df63
...@@ -33,6 +33,21 @@ memory@48000000 { ...@@ -33,6 +33,21 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0x38000000>; reg = <0x0 0x48000000 0x0 0x38000000>;
}; };
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x40000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
...@@ -213,7 +228,6 @@ &scif2 { ...@@ -213,7 +228,6 @@ &scif2 {
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&i2c2 { &i2c2 {
...@@ -339,18 +353,7 @@ &avb { ...@@ -339,18 +353,7 @@ &avb {
status = "okay"; status = "okay";
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
rxc-skew-ps = <900>; rxc-skew-ps = <1500>;
rxdv-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txc-skew-ps = <900>;
txen-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
reg = <0>; reg = <0>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
......
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View file @ 5344df63
...@@ -247,10 +247,24 @@ i2c2_pins: i2c2 { ...@@ -247,10 +247,24 @@ i2c2_pins: i2c2 {
}; };
avb_pins: avb { avb_pins: avb {
groups = "avb_mdc"; mux {
groups = "avb_link", "avb_phy_int", "avb_mdc",
"avb_mii";
function = "avb"; function = "avb";
}; };
pins_mdc {
groups = "avb_mdc";
drive-strength = <24>;
};
pins_mii_tx {
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
drive-strength = <12>;
};
};
du_pins: du { du_pins: du {
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
function = "du"; function = "du";
...@@ -348,7 +362,6 @@ &scif2 { ...@@ -348,7 +362,6 @@ &scif2 {
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&i2c2 { &i2c2 {
...@@ -485,6 +498,10 @@ &audio_clk_a { ...@@ -485,6 +498,10 @@ &audio_clk_a {
clock-frequency = <22579200>; clock-frequency = <22579200>;
}; };
&i2c_dvfs {
status = "okay";
};
&avb { &avb {
pinctrl-0 = <&avb_pins>; pinctrl-0 = <&avb_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -493,18 +510,7 @@ &avb { ...@@ -493,18 +510,7 @@ &avb {
status = "okay"; status = "okay";
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
rxc-skew-ps = <900>; rxc-skew-ps = <1500>;
rxdv-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txc-skew-ps = <900>;
txen-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
reg = <0>; reg = <0>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
...@@ -567,7 +573,6 @@ &hsusb { ...@@ -567,7 +573,6 @@ &hsusb {
&pcie_bus_clk { &pcie_bus_clk {
clock-frequency = <100000000>; clock-frequency = <100000000>;
status = "okay";
}; };
&pciec0 { &pciec0 {
......
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 5344df63
...@@ -25,10 +25,11 @@ aliases { ...@@ -25,10 +25,11 @@ aliases {
i2c4 = &i2c4; i2c4 = &i2c4;
i2c5 = &i2c5; i2c5 = &i2c5;
i2c6 = &i2c6; i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
}; };
psci { psci {
compatible = "arm,psci-0.2"; compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc"; method = "smc";
}; };
...@@ -72,17 +73,51 @@ a57_3: cpu@3 { ...@@ -72,17 +73,51 @@ a57_3: cpu@3 {
enable-method = "psci"; enable-method = "psci";
}; };
L2_CA57: cache-controller@0 { a53_0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
a53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
a53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
a53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA57: cache-controller-0 {
compatible = "cache"; compatible = "cache";
reg = <0>;
power-domains = <&sysc R8A7795_PD_CA57_SCU>; power-domains = <&sysc R8A7795_PD_CA57_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
}; };
L2_CA53: cache-controller@100 { L2_CA53: cache-controller-1 {
compatible = "cache"; compatible = "cache";
reg = <0x100>;
power-domains = <&sysc R8A7795_PD_CA53_SCU>; power-domains = <&sysc R8A7795_PD_CA53_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
...@@ -165,7 +200,7 @@ gic: interrupt-controller@f1010000 { ...@@ -165,7 +200,7 @@ gic: interrupt-controller@f1010000 {
<0x0 0xf1040000 0 0x20000>, <0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>; <0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9 interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>; clocks = <&cpg CPG_MOD 408>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
...@@ -303,16 +338,28 @@ pmu_a57 { ...@@ -303,16 +338,28 @@ pmu_a57 {
<&a57_3>; <&a57_3>;
}; };
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>,
<&a53_1>,
<&a53_2>,
<&a53_3>;
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 <GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 <GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 <GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
}; };
cpg: clock-controller@e6150000 { cpg: clock-controller@e6150000 {
...@@ -563,7 +610,7 @@ avb: ethernet@e6800000 { ...@@ -563,7 +610,7 @@ avb: ethernet@e6800000 {
"ch24"; "ch24";
clocks = <&cpg CPG_MOD 812>; clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-txid";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
...@@ -793,6 +840,19 @@ scif5: serial@e6f30000 { ...@@ -793,6 +840,19 @@ scif5: serial@e6f30000 {
status = "disabled"; status = "disabled";
}; };
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7795",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "disabled";
};
i2c0: i2c@e6500000 { i2c0: i2c@e6500000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -1015,11 +1075,11 @@ rcar_sound: sound@ec500000 { ...@@ -1015,11 +1075,11 @@ rcar_sound: sound@ec500000 {
rcar_sound,dvc { rcar_sound,dvc {
dvc0: dvc-0 { dvc0: dvc-0 {
dmas = <&audma0 0xbc>; dmas = <&audma1 0xbc>;
dma-names = "tx"; dma-names = "tx";
}; };
dvc1: dvc-1 { dvc1: dvc-1 {
dmas = <&audma0 0xbe>; dmas = <&audma1 0xbe>;
dma-names = "tx"; dma-names = "tx";
}; };
}; };
......
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
View file @ 5344df63
...@@ -180,7 +180,6 @@ &scif2 { ...@@ -180,7 +180,6 @@ &scif2 {
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&wdt0 { &wdt0 {
......
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
View file @ 5344df63
...@@ -18,6 +18,7 @@ / { ...@@ -18,6 +18,7 @@ / {
aliases { aliases {
serial0 = &scif2; serial0 = &scif2;
serial1 = &scif1;
ethernet0 = &avb; ethernet0 = &avb;
}; };
...@@ -113,6 +114,11 @@ avb_pins: avb { ...@@ -113,6 +114,11 @@ avb_pins: avb {
function = "avb"; function = "avb";
}; };
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
};
scif2_pins: scif2 { scif2_pins: scif2 {
groups = "scif2_data_a"; groups = "scif2_data_a";
function = "scif2"; function = "scif2";
...@@ -172,18 +178,7 @@ &avb { ...@@ -172,18 +178,7 @@ &avb {
status = "okay"; status = "okay";
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
rxc-skew-ps = <900>; rxc-skew-ps = <1500>;
rxdv-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txc-skew-ps = <900>;
txen-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
reg = <0>; reg = <0>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
...@@ -239,6 +234,14 @@ &sdhi3 { ...@@ -239,6 +234,14 @@ &sdhi3 {
status = "okay"; status = "okay";
}; };
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif2 { &scif2 {
pinctrl-0 = <&scif2_pins>; pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -247,7 +250,6 @@ &scif2 { ...@@ -247,7 +250,6 @@ &scif2 {
&scif_clk { &scif_clk {
clock-frequency = <14745600>; clock-frequency = <14745600>;
status = "okay";
}; };
&i2c2 { &i2c2 {
...@@ -261,3 +263,7 @@ &wdt0 { ...@@ -261,3 +263,7 @@ &wdt0 {
timeout-sec = <60>; timeout-sec = <60>;
status = "okay"; status = "okay";
}; };
&i2c_dvfs {
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View file @ 5344df63
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