Commit 535a65db authored by Tomeu Vizoso's avatar Tomeu Vizoso Committed by Thierry Reding

drm/tegra: sor: Reset during initialization

As there isn't a way for the firmware on the Nyan Chromebooks to hand
over the display to the kernel, and the kernel isn't redoing the whole
configuration at present.

With this patch, the SOR is brought to a known state and we get correct
display on every boot.
Signed-off-by: default avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent bdf76507
...@@ -1512,12 +1512,30 @@ static int tegra_sor_init(struct host1x_client *client) ...@@ -1512,12 +1512,30 @@ static int tegra_sor_init(struct host1x_client *client)
} }
} }
/*
* XXX: Remove this reset once proper hand-over from firmware to
* kernel is possible.
*/
err = reset_control_assert(sor->rst);
if (err < 0) {
dev_err(sor->dev, "failed to assert SOR reset: %d\n", err);
return err;
}
err = clk_prepare_enable(sor->clk); err = clk_prepare_enable(sor->clk);
if (err < 0) { if (err < 0) {
dev_err(sor->dev, "failed to enable clock: %d\n", err); dev_err(sor->dev, "failed to enable clock: %d\n", err);
return err; return err;
} }
usleep_range(1000, 3000);
err = reset_control_deassert(sor->rst);
if (err < 0) {
dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err);
return err;
}
err = clk_prepare_enable(sor->clk_safe); err = clk_prepare_enable(sor->clk_safe);
if (err < 0) if (err < 0)
return err; return err;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment