Commit 535b4b0c authored by Radhey Shyam Pandey's avatar Radhey Shyam Pandey Committed by Vinod Koul

dt-bindings: dmaengine: xilinx_dma: Fix formatting and style

Trivial formatting(keep compatible string one per line, caps change etc).
It doesn't modify the content of the binding.
Signed-off-by: default avatarRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1571763622-29281-3-git-send-email-radhey.shyam.pandey@xilinx.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 96336cc0
...@@ -12,8 +12,10 @@ Xilinx AXI CDMA engine, it does transfers between memory-mapped source ...@@ -12,8 +12,10 @@ Xilinx AXI CDMA engine, it does transfers between memory-mapped source
address and a memory-mapped destination address. address and a memory-mapped destination address.
Required properties: Required properties:
- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or - compatible: Should be one of-
"xlnx,axi-cdma-1.00.a"" "xlnx,axi-vdma-1.00.a"
"xlnx,axi-dma-1.00.a"
"xlnx,axi-cdma-1.00.a"
- #dma-cells: Should be <1>, see "dmas" property below - #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain VDMA registers location and length. - reg: Should contain VDMA registers location and length.
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
...@@ -29,7 +31,7 @@ Required properties: ...@@ -29,7 +31,7 @@ Required properties:
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk" "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
For CDMA: For CDMA:
Required elements: "s_axi_lite_aclk", "m_axi_aclk" Required elements: "s_axi_lite_aclk", "m_axi_aclk"
FOR AXIDMA: For AXIDMA:
Required elements: "s_axi_lite_aclk" Required elements: "s_axi_lite_aclk"
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
"m_axi_sg_aclk" "m_axi_sg_aclk"
......
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