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Commit 5474405f authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz Committed by Greg Kroah-Hartman
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Staging: rtl8187se: remove CONFIG_RTL818x_S ifdefs 

CONFIG_RTL818x_S is defined in drivers/staging/rtl8187se/r8180_hw.h.
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 9a5aabff
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drivers/staging/rtl8187se/Makefile
View file @ 5474405f
...@@ -5,7 +5,6 @@ ...@@ -5,7 +5,6 @@
#EXTRA_CFLAGS += -O2 #EXTRA_CFLAGS += -O2
#CC = gcc #CC = gcc
#CFLAGS += -DCONFIG_RTL8185B #CFLAGS += -DCONFIG_RTL8185B
#CFLAGS += -DCONFIG_RTL818x_S
#added for EeePC testing #added for EeePC testing
EXTRA_CFLAGS += -DENABLE_IPS EXTRA_CFLAGS += -DENABLE_IPS
......
drivers/staging/rtl8187se/r8180_core.c
View file @ 5474405f
...@@ -2479,9 +2479,7 @@ void rtl8180_rx(struct net_device *dev) ...@@ -2479,9 +2479,7 @@ void rtl8180_rx(struct net_device *dev)
}else { }else {
padding = 0; padding = 0;
} }
#ifdef CONFIG_RTL818X_S
padding = 0; padding = 0;
#endif
#endif #endif
priv->rx_prevlen+=len; priv->rx_prevlen+=len;
...@@ -3862,13 +3860,11 @@ void watch_dog_adaptive(unsigned long data) ...@@ -3862,13 +3860,11 @@ void watch_dog_adaptive(unsigned long data)
} }
#endif #endif
#ifdef CONFIG_RTL818X_S
// Tx Power Tracking on 87SE. // Tx Power Tracking on 87SE.
#ifdef TX_TRACK #ifdef TX_TRACK
//if( priv->bTxPowerTrack ) //lzm mod 080826 //if( priv->bTxPowerTrack ) //lzm mod 080826
if( CheckTxPwrTracking((struct net_device *)data)); if( CheckTxPwrTracking((struct net_device *)data));
TxPwrTracking87SE((struct net_device *)data); TxPwrTracking87SE((struct net_device *)data);
#endif
#endif #endif
// Perform DIG immediately. // Perform DIG immediately.
...@@ -4024,11 +4020,7 @@ short rtl8180_init(struct net_device *dev) ...@@ -4024,11 +4020,7 @@ short rtl8180_init(struct net_device *dev)
*/ */
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
priv->RegThreeWireMode = HW_THREE_WIRE_SI; priv->RegThreeWireMode = HW_THREE_WIRE_SI;
#else
priv->RegThreeWireMode = SW_THREE_WIRE;
#endif
#endif #endif
//Add for RF power on power off by lizhaoming 080512 //Add for RF power on power off by lizhaoming 080512
...@@ -4269,10 +4261,6 @@ short rtl8180_init(struct net_device *dev) ...@@ -4269,10 +4261,6 @@ short rtl8180_init(struct net_device *dev)
(0 ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them (0 ? TCR_SAT : 0); // FALSE: HW provies PLCP length and LENGEXT, TURE: SW proiveds them
priv->ReceiveConfig = priv->ReceiveConfig =
#ifdef CONFIG_RTL818X_S
#else
priv->CSMethod |
#endif
// RCR_ENMARP | // RCR_ENMARP |
RCR_AMF | RCR_ADF | //accept management/data RCR_AMF | RCR_ADF | //accept management/data
RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko. RCR_ACF | //accept control frame for SW AP needs PS-poll, 2005.07.07, by rcnjko.
...@@ -4300,17 +4288,10 @@ short rtl8180_init(struct net_device *dev) ...@@ -4300,17 +4288,10 @@ short rtl8180_init(struct net_device *dev)
switch (hw_version){ switch (hw_version){
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
case HW_VERID_R8185B_B: case HW_VERID_R8185B_B:
#ifdef CONFIG_RTL818X_S
priv->card_8185 = VERSION_8187S_C; priv->card_8185 = VERSION_8187S_C;
DMESG("MAC controller is a RTL8187SE b/g"); DMESG("MAC controller is a RTL8187SE b/g");
priv->phy_ver = 2; priv->phy_ver = 2;
break; break;
#else
DMESG("MAC controller is a RTL8185B b/g");
priv->card_8185 = 3;
priv->phy_ver = 2;
break;
#endif
#endif #endif
case HW_VERID_R8185_ABC: case HW_VERID_R8185_ABC:
DMESG("MAC controller is a RTL8185 b/g"); DMESG("MAC controller is a RTL8185 b/g");
...@@ -4350,24 +4331,9 @@ short rtl8180_init(struct net_device *dev) ...@@ -4350,24 +4331,9 @@ short rtl8180_init(struct net_device *dev)
priv->card_8185_Bversion = 0; priv->card_8185_Bversion = 0;
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
// just for sync 85 // just for sync 85
priv->card_type = PCI; priv->card_type = PCI;
DMESG("This is a PCI NIC"); DMESG("This is a PCI NIC");
#else
config3 = read_nic_byte(dev, CONFIG3);
if(config3 & 0x8){
priv->card_type = CARDBUS;
DMESG("This is a CARDBUS NIC");
}
else if( config3 & 0x4){
priv->card_type = MINIPCI;
DMESG("This is a MINI-PCI NIC");
}else{
priv->card_type = PCI;
DMESG("This is a PCI NIC");
}
#endif
#endif #endif
priv->enable_gpio0 = 0; priv->enable_gpio0 = 0;
...@@ -4375,7 +4341,6 @@ short rtl8180_init(struct net_device *dev) ...@@ -4375,7 +4341,6 @@ short rtl8180_init(struct net_device *dev)
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
usValue = eprom_read(dev, EEPROM_SW_REVD_OFFSET); usValue = eprom_read(dev, EEPROM_SW_REVD_OFFSET);
DMESG("usValue is 0x%x\n",usValue); DMESG("usValue is 0x%x\n",usValue);
#ifdef CONFIG_RTL818X_S
//3Read AntennaDiversity //3Read AntennaDiversity
// SW Antenna Diversity. // SW Antenna Diversity.
if( (usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE ) if( (usValue & EEPROM_SW_AD_MASK) != EEPROM_SW_AD_ENABLE )
...@@ -4427,7 +4392,6 @@ short rtl8180_init(struct net_device *dev) ...@@ -4427,7 +4392,6 @@ short rtl8180_init(struct net_device *dev)
} }
//printk("bDefaultAntenna1 = %d\n", priv->bDefaultAntenna1); //printk("bDefaultAntenna1 = %d\n", priv->bDefaultAntenna1);
#endif #endif
#endif
//by amy for antenna //by amy for antenna
/* rtl8185 can calc plcp len in HW.*/ /* rtl8185 can calc plcp len in HW.*/
priv->hw_plcp_len = 1; priv->hw_plcp_len = 1;
...@@ -4537,13 +4501,9 @@ DMESG output to andreamrl@tiscali.it THANKS"); ...@@ -4537,13 +4501,9 @@ DMESG output to andreamrl@tiscali.it THANKS");
} }
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
priv->rf_chip = RF_ZEBRA4; priv->rf_chip = RF_ZEBRA4;
priv->rf_sleep = rtl8225z4_rf_sleep; priv->rf_sleep = rtl8225z4_rf_sleep;
priv->rf_wakeup = rtl8225z4_rf_wakeup; priv->rf_wakeup = rtl8225z4_rf_wakeup;
#else
priv->rf_chip = RF_ZEBRA2;
#endif
//DMESG("Card reports RF frontend Realtek 8225z2"); //DMESG("Card reports RF frontend Realtek 8225z2");
//DMESGW("This driver has EXPERIMENTAL support for this chipset."); //DMESGW("This driver has EXPERIMENTAL support for this chipset.");
//DMESGW("use it with care and at your own risk and"); //DMESGW("use it with care and at your own risk and");
......
drivers/staging/rtl8187se/r8180_dm.c
View file @ 5474405f
...@@ -517,7 +517,6 @@ MgntIsCckRate( ...@@ -517,7 +517,6 @@ MgntIsCckRate(
return bReturn; return bReturn;
} }
#ifdef CONFIG_RTL818X_S
// //
// Description: // Description:
// Tx Power tracking mechanism routine on 87SE. // Tx Power tracking mechanism routine on 87SE.
...@@ -1233,7 +1232,6 @@ StaRateAdaptive87SE( ...@@ -1233,7 +1232,6 @@ StaRateAdaptive87SE(
priv->LastTxThroughput = TxThroughput; priv->LastTxThroughput = TxThroughput;
priv->ieee80211->rate = priv->CurrentOperaRate * 5; priv->ieee80211->rate = priv->CurrentOperaRate * 5;
} }
#endif
void rtl8180_rate_adapter(struct work_struct * work) void rtl8180_rate_adapter(struct work_struct * work)
{ {
...@@ -1259,10 +1257,8 @@ void timer_rate_adaptive(unsigned long data) ...@@ -1259,10 +1257,8 @@ void timer_rate_adaptive(unsigned long data)
(priv->ForcedDataRate == 0) ) (priv->ForcedDataRate == 0) )
{ {
// DMESG("timer_rate_adaptive():schedule rate_adapter_wq\n"); // DMESG("timer_rate_adaptive():schedule rate_adapter_wq\n");
#ifdef CONFIG_RTL818X_S
queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->rate_adapter_wq); queue_work(priv->ieee80211->wq, (void *)&priv->ieee80211->rate_adapter_wq);
// StaRateAdaptive87SE((struct net_device *)data); // StaRateAdaptive87SE((struct net_device *)data);
#endif
} }
priv->rateadapter_timer.expires = jiffies + MSECS(priv->RateAdaptivePeriod); priv->rateadapter_timer.expires = jiffies + MSECS(priv->RateAdaptivePeriod);
add_timer(&priv->rateadapter_timer); add_timer(&priv->rateadapter_timer);
...@@ -1320,20 +1316,12 @@ SetAntenna8185( ...@@ -1320,20 +1316,12 @@ SetAntenna8185(
case RF_ZEBRA2: case RF_ZEBRA2:
case RF_ZEBRA4: case RF_ZEBRA4:
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
// Mac register, main antenna // Mac register, main antenna
write_nic_byte(dev, ANTSEL, 0x03); write_nic_byte(dev, ANTSEL, 0x03);
//base band //base band
write_phy_cck(dev,0x11, 0x9b); // Config CCK RX antenna. write_phy_cck(dev,0x11, 0x9b); // Config CCK RX antenna.
write_phy_ofdm(dev, 0x0d, 0x5c); // Config OFDM RX antenna. write_phy_ofdm(dev, 0x0d, 0x5c); // Config OFDM RX antenna.
#else
// Mac register, main antenna
write_nic_byte(dev, ANTSEL, 0x03);
//base band
write_phy_cck(dev, 0x10, 0x9b); // Config CCK RX antenna.
write_phy_ofdm(dev, 0x0d, 0x5c); // Config OFDM RX antenna.
#endif
#endif #endif
bAntennaSwitched = true; bAntennaSwitched = true;
...@@ -1351,19 +1339,11 @@ SetAntenna8185( ...@@ -1351,19 +1339,11 @@ SetAntenna8185(
case RF_ZEBRA2: case RF_ZEBRA2:
case RF_ZEBRA4: case RF_ZEBRA4:
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
// Mac register, aux antenna // Mac register, aux antenna
write_nic_byte(dev, ANTSEL, 0x00); write_nic_byte(dev, ANTSEL, 0x00);
//base band //base band
write_phy_cck(dev, 0x11, 0xbb); // Config CCK RX antenna. write_phy_cck(dev, 0x11, 0xbb); // Config CCK RX antenna.
write_phy_ofdm(dev, 0x0d, 0x54); // Config OFDM RX antenna. write_phy_ofdm(dev, 0x0d, 0x54); // Config OFDM RX antenna.
#else
// Mac register, aux antenna
write_nic_byte(dev, ANTSEL, 0x00);
//base band
write_phy_cck(dev, 0x10, 0xbb); // Config CCK RX antenna.
write_phy_ofdm(dev, 0x0d, 0x54); // Config OFDM RX antenna.
#endif
#endif #endif
bAntennaSwitched = true; bAntennaSwitched = true;
...@@ -1406,11 +1386,9 @@ SwitchAntenna( ...@@ -1406,11 +1386,9 @@ SwitchAntenna(
{ {
#if 0//lzm del 080826 #if 0//lzm del 080826
//by amy 080312 //by amy 080312
#ifdef CONFIG_RTL818X_S
if(priv->bSwAntennaDiverity) if(priv->bSwAntennaDiverity)
bResult = SetAntennaConfig87SE(dev, 1, true); bResult = SetAntennaConfig87SE(dev, 1, true);
else else
#endif
#endif #endif
bResult = SetAntenna8185(dev, 1); bResult = SetAntenna8185(dev, 1);
//by amy 080312 //by amy 080312
...@@ -1421,11 +1399,9 @@ SwitchAntenna( ...@@ -1421,11 +1399,9 @@ SwitchAntenna(
{ {
#if 0//lzm del 080826 #if 0//lzm del 080826
//by amy 080312 //by amy 080312
#ifdef CONFIG_RTL818X_S
if(priv->bSwAntennaDiverity) if(priv->bSwAntennaDiverity)
bResult = SetAntennaConfig87SE(dev, 0, true); bResult = SetAntennaConfig87SE(dev, 0, true);
else else
#endif
#endif #endif
bResult = SetAntenna8185(dev, 0); bResult = SetAntenna8185(dev, 0);
//by amy 080312 //by amy 080312
......
drivers/staging/rtl8187se/r8180_hw.h
View file @ 5474405f
...@@ -21,7 +21,6 @@ ...@@ -21,7 +21,6 @@
#define R8180_HW #define R8180_HW
#define CONFIG_RTL8185B //support for rtl8185B, xiong-2006-11-15 #define CONFIG_RTL8185B //support for rtl8185B, xiong-2006-11-15
#define CONFIG_RTL818X_S
#define BIT0 0x00000001 #define BIT0 0x00000001
#define BIT1 0x00000002 #define BIT1 0x00000002
...@@ -300,7 +299,6 @@ ...@@ -300,7 +299,6 @@
#define CONFIG3 0x0059 #define CONFIG3 0x0059
#define CONFIG4 0x005A #define CONFIG4 0x005A
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
// SD3 szuyitasi: Mac0x57= CC -> B0 Mac0x60= D1 -> C6 // SD3 szuyitasi: Mac0x57= CC -> B0 Mac0x60= D1 -> C6
// Mac0x60 = 0x000004C6 power save parameters // Mac0x60 = 0x000004C6 power save parameters
#define ANAPARM_ASIC_ON 0xB0054D00 #define ANAPARM_ASIC_ON 0xB0054D00
...@@ -308,14 +306,6 @@ ...@@ -308,14 +306,6 @@
#define ANAPARM_ON ANAPARM_ASIC_ON #define ANAPARM_ON ANAPARM_ASIC_ON
#define ANAPARM2_ON ANAPARM2_ASIC_ON #define ANAPARM2_ON ANAPARM2_ASIC_ON
#else
// SD3 CMLin:
#define ANAPARM_ASIC_ON 0x45090658
#define ANAPARM2_ASIC_ON 0x727f3f52
#define ANAPARM_ON ANAPARM_ASIC_ON
#define ANAPARM2_ON ANAPARM2_ASIC_ON
#endif
#endif #endif
#define TESTR 0x005B #define TESTR 0x005B
...@@ -453,9 +443,7 @@ ...@@ -453,9 +443,7 @@
/* 0x00DA - 0x00DB - reserved */ /* 0x00DA - 0x00DB - reserved */
#ifdef CONFIG_RTL818X_S
#define PHYPR 0xDA //0xDA - 0x0B PHY Parameter Register. #define PHYPR 0xDA //0xDA - 0x0B PHY Parameter Register.
#endif
#define CWR 0x00DC #define CWR 0x00DC
#define CWR_END 0x00DD #define CWR_END 0x00DD
...@@ -468,9 +456,7 @@ ...@@ -468,9 +456,7 @@
#define RDSAR_END 0x00E7 #define RDSAR_END 0x00E7
/* 0x00E8 - 0x00EF - reserved */ /* 0x00E8 - 0x00EF - reserved */
#ifdef CONFIG_RTL818X_S
#define LED_CONTROL 0xED #define LED_CONTROL 0xED
#endif
#define FER 0x00F0 #define FER 0x00F0
#define FER_END 0x00F3 #define FER_END 0x00F3
...@@ -827,11 +813,9 @@ ...@@ -827,11 +813,9 @@
#define AC_BE_PARAM 0xF8 // AC_BE Parameters Record #define AC_BE_PARAM 0xF8 // AC_BE Parameters Record
#define AC_BK_PARAM 0xFC // AC_BK Parameters Record #define AC_BK_PARAM 0xFC // AC_BK Parameters Record
#ifdef CONFIG_RTL818X_S
#define BcnTimingAdjust 0x16A // Beacon Timing Adjust Register. #define BcnTimingAdjust 0x16A // Beacon Timing Adjust Register.
#define GPIOCtrl 0x16B // GPIO Control Register. #define GPIOCtrl 0x16B // GPIO Control Register.
#define PSByGC 0x180 // 0x180 - 0x183 Power Saving by Gated Clock. #define PSByGC 0x180 // 0x180 - 0x183 Power Saving by Gated Clock.
#endif
#define ARFR 0x1E0 // Auto Rate Fallback Register (0x1e0 ~ 0x1e2) #define ARFR 0x1E0 // Auto Rate Fallback Register (0x1e0 ~ 0x1e2)
#define RFSW_CTRL 0x272 // 0x272-0x273. #define RFSW_CTRL 0x272 // 0x272-0x273.
...@@ -840,10 +824,8 @@ ...@@ -840,10 +824,8 @@
#define SW_3W_CMD0 0x27C // Software 3-wire Control/Status Register. #define SW_3W_CMD0 0x27C // Software 3-wire Control/Status Register.
#define SW_3W_CMD1 0x27D // Software 3-wire Control/Status Register. #define SW_3W_CMD1 0x27D // Software 3-wire Control/Status Register.
#ifdef CONFIG_RTL818X_S
#define PI_DATA_READ 0X360 // 0x360 - 0x361 Parallel Interface Data Register. #define PI_DATA_READ 0X360 // 0x360 - 0x361 Parallel Interface Data Register.
#define SI_DATA_READ 0x362 // 0x362 - 0x363 Serial Interface Data Register. #define SI_DATA_READ 0x362 // 0x362 - 0x363 Serial Interface Data Register.
#endif
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// 8185B TPPoll bits (offset 0xd9, 1 byte) // 8185B TPPoll bits (offset 0xd9, 1 byte)
......
drivers/staging/rtl8187se/r8180_rtl8225.c
View file @ 5474405f
...@@ -38,7 +38,6 @@ u8 rtl8225_init_gain[]={ ...@@ -38,7 +38,6 @@ u8 rtl8225_init_gain[]={
0x93,0x38,0x5a,0xc5,//0x00,0x31,0x06,0x99,//Gain = 6 ~ -54dbm 0x93,0x38,0x5a,0xc5,//0x00,0x31,0x06,0x99,//Gain = 6 ~ -54dbm
}; };
#endif #endif
#ifdef CONFIG_RTL818X_S
u32 rtl8225_chan[] ={ u32 rtl8225_chan[] ={
0, 0,
0x0080, //ch1 0x0080, //ch1
...@@ -56,26 +55,6 @@ u32 rtl8225_chan[] ={ ...@@ -56,26 +55,6 @@ u32 rtl8225_chan[] ={
0x0680, 0x0680,
0x074A, //ch14 0x074A, //ch14
}; };
#else
u32 rtl8225_chan[] = {
0, //dummy channel 0
0x085c, //1
0x08dc, //2
0x095c, //3
0x09dc, //4
0x0a5c, //5
0x0adc, //6
0x0b5c, //7
0x0bdc, //8
0x0c5c, //9
0x0cdc, //10
0x0d5c, //11
0x0ddc, //12
0x0e5c, //13
//0x0f5c, //14
0x0f72, // 14
};
#endif
u16 rtl8225bcd_rxgain[]={ u16 rtl8225bcd_rxgain[]={
0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
......
drivers/staging/rtl8187se/r8180_rtl8225z2.c
View file @ 5474405f
...@@ -445,7 +445,6 @@ DbmToTxPwrIdx( ...@@ -445,7 +445,6 @@ DbmToTxPwrIdx(
bool bUseDefault = true; bool bUseDefault = true;
s8 TxPwrIdx = 0; s8 TxPwrIdx = 0;
#ifdef CONFIG_RTL818X_S
// //
// 071011, SD3 SY: // 071011, SD3 SY:
// OFDM Power in dBm = Index * 0.5 + 0 // OFDM Power in dBm = Index * 0.5 + 0
...@@ -480,7 +479,6 @@ DbmToTxPwrIdx( ...@@ -480,7 +479,6 @@ DbmToTxPwrIdx(
TxPwrIdx = (s8)tmp; TxPwrIdx = (s8)tmp;
} }
} }
#endif
// //
// TRUE if we want to use a default implementation. // TRUE if we want to use a default implementation.
...@@ -577,7 +575,6 @@ void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch) ...@@ -577,7 +575,6 @@ void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
min_ofdm_power_level = 10; min_ofdm_power_level = 10;
#ifdef CONFIG_RTL8185B #ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
if(cck_power_level > 35) if(cck_power_level > 35)
{ {
...@@ -590,36 +587,6 @@ void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch) ...@@ -590,36 +587,6 @@ void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
//printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level])); //printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]));
force_pci_posting(dev); force_pci_posting(dev);
mdelay(1); mdelay(1);
#else
/* CCK power setting */
if(cck_power_level > max_cck_power_level)
cck_power_level = max_cck_power_level;
cck_power_level += priv->cck_txpwr_base;
if(cck_power_level > 35)
cck_power_level = 35;
if(ch == 14)
cck_power_table = rtl8225z2_tx_power_cck_ch14;
else
cck_power_table = rtl8225z2_tx_power_cck;
for(i=0;i<8;i++){
power = cck_power_table[i];
write_phy_cck(dev, 0x44 + i, power);
}
//write_nic_byte(dev, TX_GAIN_CCK, power);
//2005.11.17,
write_nic_byte(dev, CCK_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]);
force_pci_posting(dev);
mdelay(1);
#endif
#endif #endif
/* OFDM power setting */ /* OFDM power setting */
// Old: // Old:
...@@ -652,11 +619,7 @@ void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch) ...@@ -652,11 +619,7 @@ void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
//write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level); //write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
//2005.11.17, //2005.11.17,
#ifdef CONFIG_RTL818X_S
write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]); write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
#else
write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]*2);
#endif
if(ofdm_power_level<=11) if(ofdm_power_level<=11)
{ {
// write_nic_dword(dev,PHY_ADR,0x00005c87); // write_nic_dword(dev,PHY_ADR,0x00005c87);
...@@ -1137,11 +1100,7 @@ void rtl8225z2_rf_init(struct net_device *dev) ...@@ -1137,11 +1100,7 @@ void rtl8225z2_rf_init(struct net_device *dev)
// //} // //}
rtl8225z2_SetTXPowerLevel(dev, channel); rtl8225z2_SetTXPowerLevel(dev, channel);
#ifdef CONFIG_RTL818X_S
write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */ write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
#else
write_phy_cck(dev, 0x10, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
#endif
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* Rx ant A, 0x10 for B */ write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* Rx ant A, 0x10 for B */
rtl8185_tx_antenna(dev, 0x3); /* TX ant A, 0x0 for B */ rtl8185_tx_antenna(dev, 0x3); /* TX ant A, 0x0 for B */
......
drivers/staging/rtl8187se/r8185b_init.c
View file @ 5474405f
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