Commit 55ab3ecb authored by Bjorn Helgaas's avatar Bjorn Helgaas

Merge branch 'pci/virtualization'

  - Fix problem with caching VF config space size (Alex Williamson)

* pci/virtualization:
  PCI/IOV: Assume SR-IOV VFs support extended config space.
  Revert "PCI/IOV: Use VF0 cached config space size for other VFs"
parents 8c6af6f0 06013b64
...@@ -132,8 +132,6 @@ static void pci_read_vf_config_common(struct pci_dev *virtfn) ...@@ -132,8 +132,6 @@ static void pci_read_vf_config_common(struct pci_dev *virtfn)
&physfn->sriov->subsystem_vendor); &physfn->sriov->subsystem_vendor);
pci_read_config_word(virtfn, PCI_SUBSYSTEM_ID, pci_read_config_word(virtfn, PCI_SUBSYSTEM_ID,
&physfn->sriov->subsystem_device); &physfn->sriov->subsystem_device);
physfn->sriov->cfg_size = pci_cfg_space_size(virtfn);
} }
int pci_iov_add_virtfn(struct pci_dev *dev, int id) int pci_iov_add_virtfn(struct pci_dev *dev, int id)
......
...@@ -293,7 +293,6 @@ struct pci_sriov { ...@@ -293,7 +293,6 @@ struct pci_sriov {
u16 driver_max_VFs; /* Max num VFs driver supports */ u16 driver_max_VFs; /* Max num VFs driver supports */
struct pci_dev *dev; /* Lowest numbered PF */ struct pci_dev *dev; /* Lowest numbered PF */
struct pci_dev *self; /* This PF */ struct pci_dev *self; /* This PF */
u32 cfg_size; /* VF config space size */
u32 class; /* VF device */ u32 class; /* VF device */
u8 hdr_type; /* VF header type */ u8 hdr_type; /* VF header type */
u16 subsystem_vendor; /* VF subsystem vendor */ u16 subsystem_vendor; /* VF subsystem vendor */
......
...@@ -1555,17 +1555,6 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev) ...@@ -1555,17 +1555,6 @@ static int pci_cfg_space_size_ext(struct pci_dev *dev)
return PCI_CFG_SPACE_EXP_SIZE; return PCI_CFG_SPACE_EXP_SIZE;
} }
#ifdef CONFIG_PCI_IOV
static bool is_vf0(struct pci_dev *dev)
{
if (pci_iov_virtfn_devfn(dev->physfn, 0) == dev->devfn &&
pci_iov_virtfn_bus(dev->physfn, 0) == dev->bus->number)
return true;
return false;
}
#endif
int pci_cfg_space_size(struct pci_dev *dev) int pci_cfg_space_size(struct pci_dev *dev)
{ {
int pos; int pos;
...@@ -1573,9 +1562,18 @@ int pci_cfg_space_size(struct pci_dev *dev) ...@@ -1573,9 +1562,18 @@ int pci_cfg_space_size(struct pci_dev *dev)
u16 class; u16 class;
#ifdef CONFIG_PCI_IOV #ifdef CONFIG_PCI_IOV
/* Read cached value for all VFs except for VF0 */ /*
if (dev->is_virtfn && !is_vf0(dev)) * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
return dev->physfn->sriov->cfg_size; * implement a PCIe capability and therefore must implement extended
* config space. We can skip the NO_EXTCFG test below and the
* reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
* the fact that the SR-IOV capability on the PF resides in extended
* config space and must be accessible and non-aliased to have enabled
* support for this VF. This is a micro performance optimization for
* systems supporting many VFs.
*/
if (dev->is_virtfn)
return PCI_CFG_SPACE_EXP_SIZE;
#endif #endif
if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
......
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