Commit 5736f96d authored by Christophe Leroy's avatar Christophe Leroy Committed by Scott Wood

powerpc32: Remove clear_pages() and define clear_page() inline

clear_pages() is never used expect by clear_page, and PPC32 is the
only architecture (still) having this function. Neither PPC64 nor
any other architecture has it.

This patch removes clear_pages() and moves clear_page() function
inline (same as PPC64) as it only is a few isns
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent d6bfa02f
#ifndef _ASM_POWERPC_PAGE_32_H #ifndef _ASM_POWERPC_PAGE_32_H
#define _ASM_POWERPC_PAGE_32_H #define _ASM_POWERPC_PAGE_32_H
#include <asm/cache.h>
#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0) #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN" #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
...@@ -36,9 +38,18 @@ typedef unsigned long long pte_basic_t; ...@@ -36,9 +38,18 @@ typedef unsigned long long pte_basic_t;
typedef unsigned long pte_basic_t; typedef unsigned long pte_basic_t;
#endif #endif
struct page; /*
extern void clear_pages(void *page, int order); * Clear page using the dcbz instruction, which doesn't cause any
static inline void clear_page(void *page) { clear_pages(page, 0); } * memory traffic (except to write out any cache lines which get
* displaced). This only works on cacheable memory.
*/
static inline void clear_page(void *addr)
{
unsigned int i;
for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
dcbz(addr);
}
extern void copy_page(void *to, void *from); extern void copy_page(void *to, void *from);
#include <asm-generic/getorder.h> #include <asm-generic/getorder.h>
......
...@@ -516,22 +516,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) ...@@ -516,22 +516,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
blr blr
#endif /* CONFIG_BOOKE */ #endif /* CONFIG_BOOKE */
/*
* Clear pages using the dcbz instruction, which doesn't cause any
* memory traffic (except to write out any cache lines which get
* displaced). This only works on cacheable memory.
*
* void clear_pages(void *page, int order) ;
*/
_GLOBAL(clear_pages)
li r0,PAGE_SIZE/L1_CACHE_BYTES
slw r0,r0,r4
mtctr r0
1: dcbz 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
blr
/* /*
* Copy a whole page. We use the dcbz instruction on the destination * Copy a whole page. We use the dcbz instruction on the destination
* to reduce memory traffic (it eliminates the unnecessary reads of * to reduce memory traffic (it eliminates the unnecessary reads of
......
...@@ -10,7 +10,6 @@ ...@@ -10,7 +10,6 @@
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/dcr.h> #include <asm/dcr.h>
EXPORT_SYMBOL(clear_pages);
EXPORT_SYMBOL(ISA_DMA_THRESHOLD); EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
EXPORT_SYMBOL(DMA_MODE_READ); EXPORT_SYMBOL(DMA_MODE_READ);
EXPORT_SYMBOL(DMA_MODE_WRITE); EXPORT_SYMBOL(DMA_MODE_WRITE);
......
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