Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
nexedi
linux
Commits
5906487e
Commit
5906487e
authored
Aug 29, 2003
by
Dave Jones
Committed by
Dave Jones
Aug 29, 2003
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[AGPGART] Use generic AGP_APBASE define instead of per vendor _APBASE.
parent
f4d5e3d2
Changes
7
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
18 additions
and
25 deletions
+18
-25
drivers/char/agp/agp.h
drivers/char/agp/agp.h
+3
-9
drivers/char/agp/ali-agp.c
drivers/char/agp/ali-agp.c
+1
-1
drivers/char/agp/amd-k7-agp.c
drivers/char/agp/amd-k7-agp.c
+1
-1
drivers/char/agp/ati-agp.c
drivers/char/agp/ati-agp.c
+2
-2
drivers/char/agp/intel-agp.c
drivers/char/agp/intel-agp.c
+9
-9
drivers/char/agp/nvidia-agp.c
drivers/char/agp/nvidia-agp.c
+1
-2
drivers/char/agp/sis-agp.c
drivers/char/agp/sis-agp.c
+1
-1
No files found.
drivers/char/agp/agp.h
View file @
5906487e
...
@@ -167,8 +167,10 @@ struct agp_bridge_data {
...
@@ -167,8 +167,10 @@ struct agp_bridge_data {
#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page)
#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page)
/* Chipset independant registers (from AGP Spec) */
#define AGP_APBASE 0x10
/* intel register */
/* intel register */
#define INTEL_APBASE 0x10
#define INTEL_APSIZE 0xb4
#define INTEL_APSIZE 0xb4
#define INTEL_ATTBASE 0xb8
#define INTEL_ATTBASE 0xb8
#define INTEL_AGPCTRL 0xb0
#define INTEL_AGPCTRL 0xb0
...
@@ -176,7 +178,6 @@ struct agp_bridge_data {
...
@@ -176,7 +178,6 @@ struct agp_bridge_data {
#define INTEL_ERRSTS 0x91
#define INTEL_ERRSTS 0x91
/* Intel 460GX Registers */
/* Intel 460GX Registers */
#define INTEL_I460_APBASE 0x10
#define INTEL_I460_BAPBASE 0x98
#define INTEL_I460_BAPBASE 0x98
#define INTEL_I460_GXBCTL 0xa0
#define INTEL_I460_GXBCTL 0xa0
#define INTEL_I460_AGPSIZ 0xa2
#define INTEL_I460_AGPSIZ 0xa2
...
@@ -261,7 +262,6 @@ struct agp_bridge_data {
...
@@ -261,7 +262,6 @@ struct agp_bridge_data {
#define I810_DRAM_ROW_0_SDRAM 0x00000001
#define I810_DRAM_ROW_0_SDRAM 0x00000001
/* Intel 7505 registers */
/* Intel 7505 registers */
#define INTEL_I7505_NAPBASELO 0x10
#define INTEL_I7505_APSIZE 0x74
#define INTEL_I7505_APSIZE 0x74
#define INTEL_I7505_NCAPID 0x60
#define INTEL_I7505_NCAPID 0x60
#define INTEL_I7505_NISTAT 0x6c
#define INTEL_I7505_NISTAT 0x6c
...
@@ -271,7 +271,6 @@ struct agp_bridge_data {
...
@@ -271,7 +271,6 @@ struct agp_bridge_data {
#define INTEL_I7505_MCHCFG 0x50
#define INTEL_I7505_MCHCFG 0x50
/* VIA register */
/* VIA register */
#define VIA_APBASE 0x10
#define VIA_GARTCTRL 0x80
#define VIA_GARTCTRL 0x80
#define VIA_APSIZE 0x84
#define VIA_APSIZE 0x84
#define VIA_ATTBASE 0x88
#define VIA_ATTBASE 0x88
...
@@ -283,14 +282,12 @@ struct agp_bridge_data {
...
@@ -283,14 +282,12 @@ struct agp_bridge_data {
#define VIA_AGPSEL 0xfd
#define VIA_AGPSEL 0xfd
/* SiS registers */
/* SiS registers */
#define SIS_APBASE 0x10
#define SIS_ATTBASE 0x90
#define SIS_ATTBASE 0x90
#define SIS_APSIZE 0x94
#define SIS_APSIZE 0x94
#define SIS_TLBCNTRL 0x97
#define SIS_TLBCNTRL 0x97
#define SIS_TLBFLUSH 0x98
#define SIS_TLBFLUSH 0x98
/* AMD registers */
/* AMD registers */
#define AMD_APBASE 0x10
#define AMD_MMBASE 0x14
#define AMD_MMBASE 0x14
#define AMD_APSIZE 0xac
#define AMD_APSIZE 0xac
#define AMD_MODECNTL 0xb0
#define AMD_MODECNTL 0xb0
...
@@ -309,7 +306,6 @@ struct agp_bridge_data {
...
@@ -309,7 +306,6 @@ struct agp_bridge_data {
#define AMD_X86_64_GARTCACHECTL 0x9c
#define AMD_X86_64_GARTCACHECTL 0x9c
#define AMD_X86_64_GARTEN 1<<0
#define AMD_X86_64_GARTEN 1<<0
#define AMD_8151_VMAPERTURE 0x10
#define AMD_8151_AGP_CTL 0xb0
#define AMD_8151_AGP_CTL 0xb0
#define AMD_8151_APERTURESIZE 0xb4
#define AMD_8151_APERTURESIZE 0xb4
#define AMD_8151_GARTPTR 0xb8
#define AMD_8151_GARTPTR 0xb8
...
@@ -317,7 +313,6 @@ struct agp_bridge_data {
...
@@ -317,7 +313,6 @@ struct agp_bridge_data {
#define AMD_8151_APEREN 1<<8
#define AMD_8151_APEREN 1<<8
/* ALi registers */
/* ALi registers */
#define ALI_APBASE 0x10
#define ALI_AGPCTRL 0xb8
#define ALI_AGPCTRL 0xb8
#define ALI_ATTBASE 0xbc
#define ALI_ATTBASE 0xbc
#define ALI_TLBCTRL 0xc0
#define ALI_TLBCTRL 0xc0
...
@@ -327,7 +322,6 @@ struct agp_bridge_data {
...
@@ -327,7 +322,6 @@ struct agp_bridge_data {
#define ALI_CACHE_FLUSH_EN 0x100
#define ALI_CACHE_FLUSH_EN 0x100
/* ATI register */
/* ATI register */
#define ATI_APBASE 0x10
#define ATI_GART_MMBASE_ADDR 0x14
#define ATI_GART_MMBASE_ADDR 0x14
#define ATI_RS100_APSIZE 0xac
#define ATI_RS100_APSIZE 0xac
#define ATI_RS300_APSIZE 0xf8
#define ATI_RS300_APSIZE 0xf8
...
...
drivers/char/agp/ali-agp.c
View file @
5906487e
...
@@ -76,7 +76,7 @@ static int ali_configure(void)
...
@@ -76,7 +76,7 @@ static int ali_configure(void)
pci_write_config_dword
(
agp_bridge
->
dev
,
ALI_TLBCTRL
,
((
temp
&
0xffffff00
)
|
0x00000010
));
pci_write_config_dword
(
agp_bridge
->
dev
,
ALI_TLBCTRL
,
((
temp
&
0xffffff00
)
|
0x00000010
));
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
A
LI
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
A
GP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
#if 0
#if 0
...
...
drivers/char/agp/amd-k7-agp.c
View file @
5906487e
...
@@ -148,7 +148,7 @@ static int amd_create_gatt_table(void)
...
@@ -148,7 +148,7 @@ static int amd_create_gatt_table(void)
* used to program the agp master not the cpu
* used to program the agp master not the cpu
*/
*/
pci_read_config_dword
(
agp_bridge
->
dev
,
A
MD
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
A
GP
_APBASE
,
&
temp
);
addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
addr
;
agp_bridge
->
gart_bus_addr
=
addr
;
...
...
drivers/char/agp/ati-agp.c
View file @
5906487e
...
@@ -212,7 +212,7 @@ static int ati_configure(void)
...
@@ -212,7 +212,7 @@ static int ati_configure(void)
/* address to map too */
/* address to map too */
/*
/*
pci_read_config_dword(agp_bridge.dev, A
TI
_APBASE, &temp);
pci_read_config_dword(agp_bridge.dev, A
GP
_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
printk(KERN_INFO "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr);
printk(KERN_INFO "IGP320 gart_bus_addr: %x\n", agp_bridge.gart_bus_addr);
*/
*/
...
@@ -355,7 +355,7 @@ static int ati_create_gatt_table(void)
...
@@ -355,7 +355,7 @@ static int ati_create_gatt_table(void)
* This is a bus address even on the alpha, b/c its
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
* used to program the agp master not the cpu
*/
*/
pci_read_config_dword
(
agp_bridge
->
dev
,
A
TI
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
A
GP
_APBASE
,
&
temp
);
addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
addr
;
agp_bridge
->
gart_bus_addr
=
addr
;
...
...
drivers/char/agp/intel-agp.c
View file @
5906487e
...
@@ -618,7 +618,7 @@ static int intel_configure(void)
...
@@ -618,7 +618,7 @@ static int intel_configure(void)
pci_write_config_word
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_word
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -657,7 +657,7 @@ static int intel_815_configure(void)
...
@@ -657,7 +657,7 @@ static int intel_815_configure(void)
current_size
->
size_value
);
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL_ATTBASE
,
&
addr
);
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL_ATTBASE
,
&
addr
);
...
@@ -708,7 +708,7 @@ static int intel_820_configure(void)
...
@@ -708,7 +708,7 @@ static int intel_820_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -739,7 +739,7 @@ static int intel_840_configure(void)
...
@@ -739,7 +739,7 @@ static int intel_840_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -768,7 +768,7 @@ static int intel_845_configure(void)
...
@@ -768,7 +768,7 @@ static int intel_845_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -797,7 +797,7 @@ static int intel_850_configure(void)
...
@@ -797,7 +797,7 @@ static int intel_850_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -826,7 +826,7 @@ static int intel_860_configure(void)
...
@@ -826,7 +826,7 @@ static int intel_860_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -855,7 +855,7 @@ static int intel_830mp_configure(void)
...
@@ -855,7 +855,7 @@ static int intel_830mp_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
@@ -884,7 +884,7 @@ static int intel_7505_configure(void)
...
@@ -884,7 +884,7 @@ static int intel_7505_configure(void)
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
pci_write_config_byte
(
agp_bridge
->
dev
,
INTEL_APSIZE
,
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
INTEL
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
/* attbase - aperture base */
/* attbase - aperture base */
...
...
drivers/char/agp/nvidia-agp.c
View file @
5906487e
...
@@ -15,7 +15,6 @@
...
@@ -15,7 +15,6 @@
/* registers */
/* registers */
#define NVIDIA_0_APBASE 0x10
#define NVIDIA_0_APSIZE 0x80
#define NVIDIA_0_APSIZE 0x80
#define NVIDIA_1_WBC 0xf0
#define NVIDIA_1_WBC 0xf0
#define NVIDIA_2_GARTCTRL 0xd0
#define NVIDIA_2_GARTCTRL 0xd0
...
@@ -73,7 +72,7 @@ static int nvidia_configure(void)
...
@@ -73,7 +72,7 @@ static int nvidia_configure(void)
current_size
->
size_value
);
current_size
->
size_value
);
/* address to map to */
/* address to map to */
pci_read_config_dword
(
agp_bridge
->
dev
,
NVIDIA_0
_APBASE
,
&
apbase
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
apbase
);
apbase
&=
PCI_BASE_ADDRESS_MEM_MASK
;
apbase
&=
PCI_BASE_ADDRESS_MEM_MASK
;
agp_bridge
->
gart_bus_addr
=
apbase
;
agp_bridge
->
gart_bus_addr
=
apbase
;
aplimit
=
apbase
+
(
current_size
->
size
*
1024
*
1024
)
-
1
;
aplimit
=
apbase
+
(
current_size
->
size
*
1024
*
1024
)
-
1
;
...
...
drivers/char/agp/sis-agp.c
View file @
5906487e
...
@@ -43,7 +43,7 @@ static int sis_configure(void)
...
@@ -43,7 +43,7 @@ static int sis_configure(void)
current_size
=
A_SIZE_8
(
agp_bridge
->
current_size
);
current_size
=
A_SIZE_8
(
agp_bridge
->
current_size
);
pci_write_config_byte
(
agp_bridge
->
dev
,
SIS_TLBCNTRL
,
0x05
);
pci_write_config_byte
(
agp_bridge
->
dev
,
SIS_TLBCNTRL
,
0x05
);
pci_read_config_dword
(
agp_bridge
->
dev
,
SIS
_APBASE
,
&
temp
);
pci_read_config_dword
(
agp_bridge
->
dev
,
AGP
_APBASE
,
&
temp
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
agp_bridge
->
gart_bus_addr
=
(
temp
&
PCI_BASE_ADDRESS_MEM_MASK
);
pci_write_config_dword
(
agp_bridge
->
dev
,
SIS_ATTBASE
,
pci_write_config_dword
(
agp_bridge
->
dev
,
SIS_ATTBASE
,
agp_bridge
->
gatt_bus_addr
);
agp_bridge
->
gatt_bus_addr
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment