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Commit 590a94d9 authored by Russell King's avatar Russell King Committed by Russell King
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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

parents 6973ee7e c35d3a41
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arch/arm/Makefile
View file @ 590a94d9
...@@ -142,6 +142,7 @@ machine-$(CONFIG_ARCH_MSM) := msm ...@@ -142,6 +142,7 @@ machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := mx1 machine-$(CONFIG_ARCH_MX1) := mx1
machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX2) := mx2
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
...@@ -165,6 +166,7 @@ machine-$(CONFIG_ARCH_U300) := u300 ...@@ -165,6 +166,7 @@ machine-$(CONFIG_ARCH_U300) := u300
machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_FOOTBRIDGE) := footbridge machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
# Platform directory name. This list is sorted alphanumerically # Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name. # by CONFIG_* macro name.
......
arch/arm/mach-mx1/clock.c
View file @ 590a94d9
...@@ -18,11 +18,14 @@ ...@@ -18,11 +18,14 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/list.h>
#include <linux/math64.h> #include <linux/math64.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/clkdev.h>
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/common.h> #include <mach/common.h>
...@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk) ...@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
} }
static struct clk clk16m = { static struct clk clk16m = {
.name = "CLK16M",
.get_rate = clk16m_get_rate, .get_rate = clk16m_get_rate,
.enable = _clk_enable, .enable = _clk_enable,
.enable_reg = CCM_CSCR, .enable_reg = CCM_CSCR,
...@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk) ...@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
} }
static struct clk clk32 = { static struct clk clk32 = {
.name = "CLK32",
.get_rate = clk32_get_rate, .get_rate = clk32_get_rate,
}; };
...@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk) ...@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
} }
static struct clk clk32_premult = { static struct clk clk32_premult = {
.name = "CLK32_premultiplier",
.parent = &clk32, .parent = &clk32,
.get_rate = clk32_premult_get_rate, .get_rate = clk32_premult_get_rate,
}; };
...@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent) ...@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
} }
static struct clk prem_clk = { static struct clk prem_clk = {
.name = "prem_clk",
.set_parent = prem_clk_set_parent, .set_parent = prem_clk_set_parent,
}; };
...@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk) ...@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
} }
static struct clk system_clk = { static struct clk system_clk = {
.name = "system_clk",
.parent = &prem_clk, .parent = &prem_clk,
.get_rate = system_clk_get_rate, .get_rate = system_clk_get_rate,
}; };
...@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk) ...@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
} }
static struct clk mcu_clk = { static struct clk mcu_clk = {
.name = "mcu_clk",
.parent = &clk32_premult, .parent = &clk32_premult,
.get_rate = mcu_clk_get_rate, .get_rate = mcu_clk_get_rate,
}; };
...@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk) ...@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
} }
static struct clk fclk = { static struct clk fclk = {
.name = "fclk",
.parent = &mcu_clk, .parent = &mcu_clk,
.get_rate = fclk_get_rate, .get_rate = fclk_get_rate,
}; };
...@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate) ...@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
} }
static struct clk hclk = { static struct clk hclk = {
.name = "hclk",
.parent = &system_clk, .parent = &system_clk,
.get_rate = hclk_get_rate, .get_rate = hclk_get_rate,
.round_rate = hclk_round_rate, .round_rate = hclk_round_rate,
...@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate) ...@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
} }
static struct clk clk48m = { static struct clk clk48m = {
.name = "CLK48M",
.parent = &system_clk, .parent = &system_clk,
.get_rate = clk48m_get_rate, .get_rate = clk48m_get_rate,
.round_rate = clk48m_round_rate, .round_rate = clk48m_round_rate,
...@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate) ...@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
static struct clk perclk[] = { static struct clk perclk[] = {
{ {
.name = "perclk",
.id = 0, .id = 0,
.parent = &system_clk, .parent = &system_clk,
.get_rate = perclk1_get_rate, .get_rate = perclk1_get_rate,
.round_rate = perclk1_round_rate, .round_rate = perclk1_round_rate,
.set_rate = perclk1_set_rate, .set_rate = perclk1_set_rate,
}, { }, {
.name = "perclk",
.id = 1, .id = 1,
.parent = &system_clk, .parent = &system_clk,
.get_rate = perclk2_get_rate, .get_rate = perclk2_get_rate,
.round_rate = perclk2_round_rate, .round_rate = perclk2_round_rate,
.set_rate = perclk2_set_rate, .set_rate = perclk2_set_rate,
}, { }, {
.name = "perclk",
.id = 2, .id = 2,
.parent = &system_clk, .parent = &system_clk,
.get_rate = perclk3_get_rate, .get_rate = perclk3_get_rate,
...@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent) ...@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
} }
static struct clk clko_clk = { static struct clk clko_clk = {
.name = "clko_clk",
.set_parent = clko_set_parent, .set_parent = clko_set_parent,
}; };
static struct clk dma_clk = { static struct clk dma_clk = {
.name = "dma",
.parent = &hclk, .parent = &hclk,
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
...@@ -473,7 +462,6 @@ static struct clk dma_clk = { ...@@ -473,7 +462,6 @@ static struct clk dma_clk = {
}; };
static struct clk csi_clk = { static struct clk csi_clk = {
.name = "csi_clk",
.parent = &hclk, .parent = &hclk,
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
...@@ -484,7 +472,6 @@ static struct clk csi_clk = { ...@@ -484,7 +472,6 @@ static struct clk csi_clk = {
}; };
static struct clk mma_clk = { static struct clk mma_clk = {
.name = "mma_clk",
.parent = &hclk, .parent = &hclk,
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
...@@ -495,7 +482,6 @@ static struct clk mma_clk = { ...@@ -495,7 +482,6 @@ static struct clk mma_clk = {
}; };
static struct clk usbd_clk = { static struct clk usbd_clk = {
.name = "usbd_clk",
.parent = &clk48m, .parent = &clk48m,
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
...@@ -506,99 +492,85 @@ static struct clk usbd_clk = { ...@@ -506,99 +492,85 @@ static struct clk usbd_clk = {
}; };
static struct clk gpt_clk = { static struct clk gpt_clk = {
.name = "gpt_clk",
.parent = &perclk[0], .parent = &perclk[0],
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk uart_clk = { static struct clk uart_clk = {
.name = "uart",
.parent = &perclk[0], .parent = &perclk[0],
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk i2c_clk = { static struct clk i2c_clk = {
.name = "i2c_clk",
.parent = &hclk, .parent = &hclk,
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk spi_clk = { static struct clk spi_clk = {
.name = "spi_clk",
.parent = &perclk[1], .parent = &perclk[1],
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk sdhc_clk = { static struct clk sdhc_clk = {
.name = "sdhc_clk",
.parent = &perclk[1], .parent = &perclk[1],
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk lcdc_clk = { static struct clk lcdc_clk = {
.name = "lcdc_clk",
.parent = &perclk[1], .parent = &perclk[1],
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk mshc_clk = { static struct clk mshc_clk = {
.name = "mshc_clk",
.parent = &hclk, .parent = &hclk,
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk ssi_clk = { static struct clk ssi_clk = {
.name = "ssi_clk",
.parent = &perclk[2], .parent = &perclk[2],
.round_rate = _clk_parent_round_rate, .round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate, .set_rate = _clk_parent_set_rate,
}; };
static struct clk rtc_clk = { static struct clk rtc_clk = {
.name = "rtc_clk",
.parent = &clk32, .parent = &clk32,
}; };
static struct clk *mxc_clks[] = { #define _REGISTER_CLOCK(d, n, c) \
&clk16m, { \
&clk32, .dev_id = d, \
&clk32_premult, .con_id = n, \
&prem_clk, .clk = &c, \
&system_clk, },
&mcu_clk, static struct clk_lookup lookups[] __initdata = {
&fclk, _REGISTER_CLOCK(NULL, "dma", dma_clk)
&hclk, _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
&clk48m, _REGISTER_CLOCK(NULL, "mma", mma_clk)
&perclk[0], _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
&perclk[1], _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
&perclk[2], _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
&clko_clk, _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
&dma_clk, _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
&csi_clk, _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
&mma_clk, _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
&usbd_clk, _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
&gpt_clk, _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
&uart_clk, _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
&i2c_clk, _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
&spi_clk, _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
&sdhc_clk,
&lcdc_clk,
&mshc_clk,
&ssi_clk,
&rtc_clk,
}; };
int __init mx1_clocks_init(unsigned long fref) int __init mx1_clocks_init(unsigned long fref)
{ {
struct clk **clkp;
unsigned int reg; unsigned int reg;
int i;
/* disable clocks we are able to */ /* disable clocks we are able to */
__raw_writel(0, SCM_GCCR); __raw_writel(0, SCM_GCCR);
...@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref) ...@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref)
reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET; reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
clko_clk.parent = (struct clk *)clko_clocks[reg]; clko_clk.parent = (struct clk *)clko_clocks[reg];
for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) for (i = 0; i < ARRAY_SIZE(lookups); i++)
clk_register(*clkp); clkdev_add(&lookups[i]);
clk_enable(&hclk); clk_enable(&hclk);
clk_enable(&fclk); clk_enable(&fclk);
mxc_timer_init(&gpt_clk); mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
return 0; return 0;
} }
arch/arm/mach-mx1/devices.c
View file @ 590a94d9
...@@ -29,12 +29,11 @@ ...@@ -29,12 +29,11 @@
#include "devices.h" #include "devices.h"
static struct resource imx_csi_resources[] = { static struct resource imx_csi_resources[] = {
[0] = { {
.start = 0x00224000, .start = 0x00224000,
.end = 0x00224010, .end = 0x00224010,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = CSI_INT, .start = CSI_INT,
.end = CSI_INT, .end = CSI_INT,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -55,12 +54,11 @@ struct platform_device imx_csi_device = { ...@@ -55,12 +54,11 @@ struct platform_device imx_csi_device = {
}; };
static struct resource imx_i2c_resources[] = { static struct resource imx_i2c_resources[] = {
[0] = { {
.start = 0x00217000, .start = 0x00217000,
.end = 0x00217010, .end = 0x00217010,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = I2C_INT, .start = I2C_INT,
.end = I2C_INT, .end = I2C_INT,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -75,22 +73,19 @@ struct platform_device imx_i2c_device = { ...@@ -75,22 +73,19 @@ struct platform_device imx_i2c_device = {
}; };
static struct resource imx_uart1_resources[] = { static struct resource imx_uart1_resources[] = {
[0] = { {
.start = UART1_BASE_ADDR, .start = UART1_BASE_ADDR,
.end = UART1_BASE_ADDR + 0xD0, .end = UART1_BASE_ADDR + 0xD0,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = UART1_MINT_RX, .start = UART1_MINT_RX,
.end = UART1_MINT_RX, .end = UART1_MINT_RX,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[2] = {
.start = UART1_MINT_TX, .start = UART1_MINT_TX,
.end = UART1_MINT_TX, .end = UART1_MINT_TX,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[3] = {
.start = UART1_MINT_RTS, .start = UART1_MINT_RTS,
.end = UART1_MINT_RTS, .end = UART1_MINT_RTS,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -105,22 +100,19 @@ struct platform_device imx_uart1_device = { ...@@ -105,22 +100,19 @@ struct platform_device imx_uart1_device = {
}; };
static struct resource imx_uart2_resources[] = { static struct resource imx_uart2_resources[] = {
[0] = { {
.start = UART2_BASE_ADDR, .start = UART2_BASE_ADDR,
.end = UART2_BASE_ADDR + 0xD0, .end = UART2_BASE_ADDR + 0xD0,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = UART2_MINT_RX, .start = UART2_MINT_RX,
.end = UART2_MINT_RX, .end = UART2_MINT_RX,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[2] = {
.start = UART2_MINT_TX, .start = UART2_MINT_TX,
.end = UART2_MINT_TX, .end = UART2_MINT_TX,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[3] = {
.start = UART2_MINT_RTS, .start = UART2_MINT_RTS,
.end = UART2_MINT_RTS, .end = UART2_MINT_RTS,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -135,17 +127,15 @@ struct platform_device imx_uart2_device = { ...@@ -135,17 +127,15 @@ struct platform_device imx_uart2_device = {
}; };
static struct resource imx_rtc_resources[] = { static struct resource imx_rtc_resources[] = {
[0] = { {
.start = 0x00204000, .start = 0x00204000,
.end = 0x00204024, .end = 0x00204024,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = RTC_INT, .start = RTC_INT,
.end = RTC_INT, .end = RTC_INT,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[2] = {
.start = RTC_SAMINT, .start = RTC_SAMINT,
.end = RTC_SAMINT, .end = RTC_SAMINT,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -160,12 +150,11 @@ struct platform_device imx_rtc_device = { ...@@ -160,12 +150,11 @@ struct platform_device imx_rtc_device = {
}; };
static struct resource imx_wdt_resources[] = { static struct resource imx_wdt_resources[] = {
[0] = { {
.start = 0x00201000, .start = 0x00201000,
.end = 0x00201008, .end = 0x00201008,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = WDT_INT, .start = WDT_INT,
.end = WDT_INT, .end = WDT_INT,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -180,42 +169,35 @@ struct platform_device imx_wdt_device = { ...@@ -180,42 +169,35 @@ struct platform_device imx_wdt_device = {
}; };
static struct resource imx_usb_resources[] = { static struct resource imx_usb_resources[] = {
[0] = { {
.start = 0x00212000, .start = 0x00212000,
.end = 0x00212148, .end = 0x00212148,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = USBD_INT0, .start = USBD_INT0,
.end = USBD_INT0, .end = USBD_INT0,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[2] = {
.start = USBD_INT1, .start = USBD_INT1,
.end = USBD_INT1, .end = USBD_INT1,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[3] = {
.start = USBD_INT2, .start = USBD_INT2,
.end = USBD_INT2, .end = USBD_INT2,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[4] = {
.start = USBD_INT3, .start = USBD_INT3,
.end = USBD_INT3, .end = USBD_INT3,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[5] = {
.start = USBD_INT4, .start = USBD_INT4,
.end = USBD_INT4, .end = USBD_INT4,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[6] = {
.start = USBD_INT5, .start = USBD_INT5,
.end = USBD_INT5, .end = USBD_INT5,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[7] = {
.start = USBD_INT6, .start = USBD_INT6,
.end = USBD_INT6, .end = USBD_INT6,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -231,29 +213,26 @@ struct platform_device imx_usb_device = { ...@@ -231,29 +213,26 @@ struct platform_device imx_usb_device = {
/* GPIO port description */ /* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = { static struct mxc_gpio_port imx_gpio_ports[] = {
[0] = { {
.chip.label = "gpio-0", .chip.label = "gpio-0",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
.irq = GPIO_INT_PORTA, .irq = GPIO_INT_PORTA,
.virtual_irq_start = MXC_GPIO_IRQ_START .virtual_irq_start = MXC_GPIO_IRQ_START,
}, }, {
[1] = {
.chip.label = "gpio-1", .chip.label = "gpio-1",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.irq = GPIO_INT_PORTB, .irq = GPIO_INT_PORTB,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, }, {
[2] = {
.chip.label = "gpio-2", .chip.label = "gpio-2",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
.irq = GPIO_INT_PORTC, .irq = GPIO_INT_PORTC,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, }, {
[3] = {
.chip.label = "gpio-3", .chip.label = "gpio-3",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300), .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.irq = GPIO_INT_PORTD, .irq = GPIO_INT_PORTD,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
} }
}; };
......
arch/arm/mach-mx1/generic.c
View file @ 590a94d9
...@@ -41,6 +41,13 @@ static struct map_desc imx_io_desc[] __initdata = { ...@@ -41,6 +41,13 @@ static struct map_desc imx_io_desc[] __initdata = {
void __init mx1_map_io(void) void __init mx1_map_io(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX1); mxc_set_cpu_type(MXC_CPU_MX1);
mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
} }
void __init mx1_init_irq(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
}
arch/arm/mach-mx1/mx1ads.c
View file @ 590a94d9
...@@ -104,12 +104,10 @@ static struct imxi2c_platform_data mx1ads_i2c_data = { ...@@ -104,12 +104,10 @@ static struct imxi2c_platform_data mx1ads_i2c_data = {
static struct i2c_board_info mx1ads_i2c_devices[] = { static struct i2c_board_info mx1ads_i2c_devices[] = {
{ {
I2C_BOARD_INFO("pcf857x", 0x22), I2C_BOARD_INFO("pcf8575", 0x22),
.type = "pcf8575",
.platform_data = &pcf857x_data[0], .platform_data = &pcf857x_data[0],
}, { }, {
I2C_BOARD_INFO("pcf857x", 0x24), I2C_BOARD_INFO("pcf8575", 0x24),
.type = "pcf8575",
.platform_data = &pcf857x_data[1], .platform_data = &pcf857x_data[1],
}, },
}; };
...@@ -151,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") ...@@ -151,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx1_map_io, .map_io = mx1_map_io,
.init_irq = mxc_init_irq, .init_irq = mx1_init_irq,
.timer = &mx1ads_timer, .timer = &mx1ads_timer,
.init_machine = mx1ads_init, .init_machine = mx1ads_init,
MACHINE_END MACHINE_END
...@@ -161,7 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS") ...@@ -161,7 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx1_map_io, .map_io = mx1_map_io,
.init_irq = mxc_init_irq, .init_irq = mx1_init_irq,
.timer = &mx1ads_timer, .timer = &mx1ads_timer,
.init_machine = mx1ads_init, .init_machine = mx1ads_init,
MACHINE_END MACHINE_END
arch/arm/mach-mx1/scb9328.c
View file @ 590a94d9
...@@ -68,22 +68,20 @@ static struct dm9000_plat_data dm9000_platdata = { ...@@ -68,22 +68,20 @@ static struct dm9000_plat_data dm9000_platdata = {
* to gain access to address latch registers and the data path. * to gain access to address latch registers and the data path.
*/ */
static struct resource dm9000x_resources[] = { static struct resource dm9000x_resources[] = {
[0] = { {
.name = "address area", .name = "address area",
.start = IMX_CS5_PHYS, .start = IMX_CS5_PHYS,
.end = IMX_CS5_PHYS + 1, .end = IMX_CS5_PHYS + 1,
.flags = IORESOURCE_MEM /* address access */ .flags = IORESOURCE_MEM, /* address access */
}, }, {
[1] = {
.name = "data area", .name = "data area",
.start = IMX_CS5_PHYS + 4, .start = IMX_CS5_PHYS + 4,
.end = IMX_CS5_PHYS + 5, .end = IMX_CS5_PHYS + 5,
.flags = IORESOURCE_MEM /* data access */ .flags = IORESOURCE_MEM, /* data access */
}, }, {
[2] = {
.start = IRQ_GPIOC(3), .start = IRQ_GPIOC(3),
.end = IRQ_GPIOC(3), .end = IRQ_GPIOC(3),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
}, },
}; };
...@@ -154,7 +152,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328") ...@@ -154,7 +152,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
.io_pg_offst = ((0xe0200000) >> 18) & 0xfffc, .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc,
.boot_params = 0x08000100, .boot_params = 0x08000100,
.map_io = mx1_map_io, .map_io = mx1_map_io,
.init_irq = mxc_init_irq, .init_irq = mx1_init_irq,
.timer = &scb9328_timer, .timer = &scb9328_timer,
.init_machine = scb9328_init, .init_machine = scb9328_init,
MACHINE_END MACHINE_END
arch/arm/mach-mx2/Kconfig
View file @ 590a94d9
...@@ -53,6 +53,34 @@ config MACH_PCM970_BASEBOARD ...@@ -53,6 +53,34 @@ config MACH_PCM970_BASEBOARD
endchoice endchoice
config MACH_EUKREA_CPUIMX27
bool "Eukrea CPUIMX27 module"
depends on MACH_MX27
help
Include support for Eukrea CPUIMX27 platform. This includes
specific configurations for the module and its peripherals.
config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_EUKREA_CPUIMX27
help
This adds support for the internal SDHC2 used on CPUIMX27 used
for wifi or eMMC.
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX27
default MACH_EUKREA_MBIMX27_BASEBOARD
config MACH_EUKREA_MBIMX27_BASEBOARD
prompt "Eukrea MBIMX27 development board"
bool
help
This adds board specific devices that can be found on Eukrea's
MBIMX27 evaluation board.
endchoice
config MACH_MX27_3DS config MACH_MX27_3DS
bool "MX27PDK platform" bool "MX27PDK platform"
depends on MACH_MX27 depends on MACH_MX27
...@@ -67,4 +95,11 @@ config MACH_MX27LITE ...@@ -67,4 +95,11 @@ config MACH_MX27LITE
Include support for MX27 LITEKIT platform. This includes specific Include support for MX27 LITEKIT platform. This includes specific
configurations for the board and its peripherals. configurations for the board and its peripherals.
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
depends on MACH_MX27
help
Include support for phyCARD-s (aka pca100) platform. This
includes specific configurations for the module and its peripherals.
endif endif
arch/arm/mach-mx2/Makefile
View file @ 590a94d9
...@@ -17,4 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o ...@@ -17,4 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += pca100.o
arch/arm/mach-mx2/clock_imx21.c
View file @ 590a94d9
...@@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) ...@@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_enable(&uart_clk[0]); clk_enable(&uart_clk[0]);
#endif #endif
mxc_timer_init(&gpt_clk[0]); mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
return 0; return 0;
} }
arch/arm/mach-mx2/clock_imx27.c
View file @ 590a94d9
...@@ -643,7 +643,14 @@ static struct clk_lookup lookups[] = { ...@@ -643,7 +643,14 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "cspi3", cspi3_clk) _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK(NULL, "csi", csi_clk) _REGISTER_CLOCK(NULL, "csi", csi_clk)
_REGISTER_CLOCK(NULL, "usb", usb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
_REGISTER_CLOCK(NULL, "ssi1", ssi1_clk) _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
_REGISTER_CLOCK(NULL, "ssi2", ssi2_clk) _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
...@@ -748,7 +755,7 @@ int __init mx27_clocks_init(unsigned long fref) ...@@ -748,7 +755,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk_enable(&uart1_clk); clk_enable(&uart1_clk);
#endif #endif
mxc_timer_init(&gpt1_clk); mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
return 0; return 0;
} }
......
arch/arm/mach-mx2/devices.c
View file @ 590a94d9
...@@ -40,45 +40,87 @@ ...@@ -40,45 +40,87 @@
#include "devices.h" #include "devices.h"
/* /*
* Resource definition for the MXC IrDA * SPI master controller
*
* - i.MX1: 2 channel (slighly different register setting)
* - i.MX21: 2 channel
* - i.MX27: 3 channel
*/ */
static struct resource mxc_irda_resources[] = { static struct resource mxc_spi_resources0[] = {
[0] = { {
.start = UART3_BASE_ADDR, .start = CSPI1_BASE_ADDR,
.end = UART3_BASE_ADDR + SZ_4K - 1, .end = CSPI1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI1,
.end = MXC_INT_CSPI1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxc_spi_resources1[] = {
{
.start = CSPI2_BASE_ADDR,
.end = CSPI2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI2,
.end = MXC_INT_CSPI2,
.flags = IORESOURCE_IRQ,
}, },
[1] = { };
.start = MXC_INT_UART3,
.end = MXC_INT_UART3, #ifdef CONFIG_MACH_MX27
static struct resource mxc_spi_resources2[] = {
{
.start = CSPI3_BASE_ADDR,
.end = CSPI3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI3,
.end = MXC_INT_CSPI3,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
#endif
/* Platform Data for MXC IrDA */ struct platform_device mxc_spi_device0 = {
struct platform_device mxc_irda_device = { .name = "spi_imx",
.name = "mxc_irda",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(mxc_irda_resources), .num_resources = ARRAY_SIZE(mxc_spi_resources0),
.resource = mxc_irda_resources, .resource = mxc_spi_resources0,
}; };
struct platform_device mxc_spi_device1 = {
.name = "spi_imx",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_spi_resources1),
.resource = mxc_spi_resources1,
};
#ifdef CONFIG_MACH_MX27
struct platform_device mxc_spi_device2 = {
.name = "spi_imx",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_spi_resources2),
.resource = mxc_spi_resources2,
};
#endif
/* /*
* General Purpose Timer * General Purpose Timer
* - i.MX1: 2 timer (slighly different register handling) * - i.MX21: 3 timers
* - i.MX21: 3 timer * - i.MX27: 6 timers
* - i.MX27: 6 timer
*/ */
/* We use gpt0 as system timer, so do not add a device for this one */ /* We use gpt0 as system timer, so do not add a device for this one */
static struct resource timer1_resources[] = { static struct resource timer1_resources[] = {
[0] = { {
.start = GPT2_BASE_ADDR, .start = GPT2_BASE_ADDR,
.end = GPT2_BASE_ADDR + 0x17, .end = GPT2_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_GPT2, .start = MXC_INT_GPT2,
.end = MXC_INT_GPT2, .end = MXC_INT_GPT2,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = { ...@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = {
.name = "imx_gpt", .name = "imx_gpt",
.id = 1, .id = 1,
.num_resources = ARRAY_SIZE(timer1_resources), .num_resources = ARRAY_SIZE(timer1_resources),
.resource = timer1_resources .resource = timer1_resources,
}; };
static struct resource timer2_resources[] = { static struct resource timer2_resources[] = {
[0] = { {
.start = GPT3_BASE_ADDR, .start = GPT3_BASE_ADDR,
.end = GPT3_BASE_ADDR + 0x17, .end = GPT3_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_GPT3, .start = MXC_INT_GPT3,
.end = MXC_INT_GPT3, .end = MXC_INT_GPT3,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = { ...@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = {
.name = "imx_gpt", .name = "imx_gpt",
.id = 2, .id = 2,
.num_resources = ARRAY_SIZE(timer2_resources), .num_resources = ARRAY_SIZE(timer2_resources),
.resource = timer2_resources .resource = timer2_resources,
}; };
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = { static struct resource timer3_resources[] = {
[0] = { {
.start = GPT4_BASE_ADDR, .start = GPT4_BASE_ADDR,
.end = GPT4_BASE_ADDR + 0x17, .end = GPT4_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_GPT4, .start = MXC_INT_GPT4,
.end = MXC_INT_GPT4, .end = MXC_INT_GPT4,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = { ...@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = {
.name = "imx_gpt", .name = "imx_gpt",
.id = 3, .id = 3,
.num_resources = ARRAY_SIZE(timer3_resources), .num_resources = ARRAY_SIZE(timer3_resources),
.resource = timer3_resources .resource = timer3_resources,
}; };
static struct resource timer4_resources[] = { static struct resource timer4_resources[] = {
[0] = { {
.start = GPT5_BASE_ADDR, .start = GPT5_BASE_ADDR,
.end = GPT5_BASE_ADDR + 0x17, .end = GPT5_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_GPT5, .start = MXC_INT_GPT5,
.end = MXC_INT_GPT5, .end = MXC_INT_GPT5,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = { ...@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = {
.name = "imx_gpt", .name = "imx_gpt",
.id = 4, .id = 4,
.num_resources = ARRAY_SIZE(timer4_resources), .num_resources = ARRAY_SIZE(timer4_resources),
.resource = timer4_resources .resource = timer4_resources,
}; };
static struct resource timer5_resources[] = { static struct resource timer5_resources[] = {
[0] = { {
.start = GPT6_BASE_ADDR, .start = GPT6_BASE_ADDR,
.end = GPT6_BASE_ADDR + 0x17, .end = GPT6_BASE_ADDR + 0x17,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_GPT6, .start = MXC_INT_GPT6,
.end = MXC_INT_GPT6, .end = MXC_INT_GPT6,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = { ...@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = {
.name = "imx_gpt", .name = "imx_gpt",
.id = 5, .id = 5,
.num_resources = ARRAY_SIZE(timer5_resources), .num_resources = ARRAY_SIZE(timer5_resources),
.resource = timer5_resources .resource = timer5_resources,
}; };
#endif #endif
...@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = { ...@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = {
{ {
.start = NFC_BASE_ADDR, .start = NFC_BASE_ADDR,
.end = NFC_BASE_ADDR + 0xfff, .end = NFC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_NANDFC, .start = MXC_INT_NANDFC,
.end = MXC_INT_NANDFC, .end = MXC_INT_NANDFC,
.flags = IORESOURCE_IRQ .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = { ...@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = {
.start = LCDC_BASE_ADDR, .start = LCDC_BASE_ADDR,
.end = LCDC_BASE_ADDR + 0xFFF, .end = LCDC_BASE_ADDR + 0xFFF,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
{
.start = MXC_INT_LCDC, .start = MXC_INT_LCDC,
.end = MXC_INT_LCDC, .end = MXC_INT_LCDC,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = { ...@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = {
{ {
.start = FEC_BASE_ADDR, .start = FEC_BASE_ADDR,
.end = FEC_BASE_ADDR + 0xfff, .end = FEC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_FEC, .start = MXC_INT_FEC,
.end = MXC_INT_FEC, .end = MXC_INT_FEC,
.flags = IORESOURCE_IRQ .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = { ...@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = {
#endif #endif
static struct resource mxc_i2c_1_resources[] = { static struct resource mxc_i2c_1_resources[] = {
[0] = { {
.start = I2C_BASE_ADDR, .start = I2C_BASE_ADDR,
.end = I2C_BASE_ADDR + 0x0fff, .end = I2C_BASE_ADDR + 0x0fff,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_I2C, .start = MXC_INT_I2C,
.end = MXC_INT_I2C, .end = MXC_INT_I2C,
.flags = IORESOURCE_IRQ .flags = IORESOURCE_IRQ,
} }
}; };
...@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = { ...@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = {
.name = "imx-i2c", .name = "imx-i2c",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(mxc_i2c_1_resources), .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
.resource = mxc_i2c_1_resources .resource = mxc_i2c_1_resources,
}; };
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = { static struct resource mxc_i2c_2_resources[] = {
[0] = { {
.start = I2C2_BASE_ADDR, .start = I2C2_BASE_ADDR,
.end = I2C2_BASE_ADDR + 0x0fff, .end = I2C2_BASE_ADDR + 0x0fff,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_I2C2, .start = MXC_INT_I2C2,
.end = MXC_INT_I2C2, .end = MXC_INT_I2C2,
.flags = IORESOURCE_IRQ .flags = IORESOURCE_IRQ,
} }
}; };
...@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = { ...@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = {
.name = "imx-i2c", .name = "imx-i2c",
.id = 1, .id = 1,
.num_resources = ARRAY_SIZE(mxc_i2c_2_resources), .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
.resource = mxc_i2c_2_resources .resource = mxc_i2c_2_resources,
}; };
#endif #endif
static struct resource mxc_pwm_resources[] = { static struct resource mxc_pwm_resources[] = {
[0] = { {
.start = PWM_BASE_ADDR, .start = PWM_BASE_ADDR,
.end = PWM_BASE_ADDR + 0x0fff, .end = PWM_BASE_ADDR + 0x0fff,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_PWM, .start = MXC_INT_PWM,
.end = MXC_INT_PWM, .end = MXC_INT_PWM,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -339,27 +373,25 @@ struct platform_device mxc_pwm_device = { ...@@ -339,27 +373,25 @@ struct platform_device mxc_pwm_device = {
.name = "mxc_pwm", .name = "mxc_pwm",
.id = 0, .id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources), .num_resources = ARRAY_SIZE(mxc_pwm_resources),
.resource = mxc_pwm_resources .resource = mxc_pwm_resources,
}; };
/* /*
* Resource definition for the MXC SDHC * Resource definition for the MXC SDHC
*/ */
static struct resource mxc_sdhc1_resources[] = { static struct resource mxc_sdhc1_resources[] = {
[0] = { {
.start = SDHC1_BASE_ADDR, .start = SDHC1_BASE_ADDR,
.end = SDHC1_BASE_ADDR + SZ_4K - 1, .end = SDHC1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_SDHC1, .start = MXC_INT_SDHC1,
.end = MXC_INT_SDHC1, .end = MXC_INT_SDHC1,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[2] = {
.start = DMA_REQ_SDHC1, .start = DMA_REQ_SDHC1,
.end = DMA_REQ_SDHC1, .end = DMA_REQ_SDHC1,
.flags = IORESOURCE_DMA .flags = IORESOURCE_DMA,
}, },
}; };
...@@ -377,20 +409,18 @@ struct platform_device mxc_sdhc_device0 = { ...@@ -377,20 +409,18 @@ struct platform_device mxc_sdhc_device0 = {
}; };
static struct resource mxc_sdhc2_resources[] = { static struct resource mxc_sdhc2_resources[] = {
[0] = { {
.start = SDHC2_BASE_ADDR, .start = SDHC2_BASE_ADDR,
.end = SDHC2_BASE_ADDR + SZ_4K - 1, .end = SDHC2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = MXC_INT_SDHC2, .start = MXC_INT_SDHC2,
.end = MXC_INT_SDHC2, .end = MXC_INT_SDHC2,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, }, {
[2] = {
.start = DMA_REQ_SDHC2, .start = DMA_REQ_SDHC2,
.end = DMA_REQ_SDHC2, .end = DMA_REQ_SDHC2,
.flags = IORESOURCE_DMA .flags = IORESOURCE_DMA,
}, },
}; };
...@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = { ...@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = {
.resource = mxc_sdhc2_resources, .resource = mxc_sdhc2_resources,
}; };
#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
{
.start = OTG_BASE_ADDR,
.end = OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB3,
.end = MXC_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = 0xffffffffUL;
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = 0xffffffffUL,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = 0xffffffffUL;
static struct resource mxc_usbh1_resources[] = {
{
.start = OTG_BASE_ADDR + 0x200,
.end = OTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB1,
.end = MXC_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = 0xffffffffUL;
static struct resource mxc_usbh2_resources[] = {
{
.start = OTG_BASE_ADDR + 0x400,
.end = OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB2,
.end = MXC_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif
/* GPIO port description */ /* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = { static struct mxc_gpio_port imx_gpio_ports[] = {
[0] = { {
.chip.label = "gpio-0", .chip.label = "gpio-0",
.irq = MXC_INT_GPIO, .irq = MXC_INT_GPIO,
.base = IO_ADDRESS(GPIO_BASE_ADDR), .base = IO_ADDRESS(GPIO_BASE_ADDR),
.virtual_irq_start = MXC_GPIO_IRQ_START, .virtual_irq_start = MXC_GPIO_IRQ_START,
}, }, {
[1] = {
.chip.label = "gpio-1", .chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.virtual_irq_start = MXC_GPIO_IRQ_START + 32, .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, }, {
[2] = {
.chip.label = "gpio-2", .chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
.virtual_irq_start = MXC_GPIO_IRQ_START + 64, .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, }, {
[3] = {
.chip.label = "gpio-3", .chip.label = "gpio-3",
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.virtual_irq_start = MXC_GPIO_IRQ_START + 96, .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}, }, {
[4] = {
.chip.label = "gpio-4", .chip.label = "gpio-4",
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
.virtual_irq_start = MXC_GPIO_IRQ_START + 128, .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
}, }, {
[5] = {
.chip.label = "gpio-5", .chip.label = "gpio-5",
.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
.virtual_irq_start = MXC_GPIO_IRQ_START + 160, .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
......
arch/arm/mach-mx2/devices.h
View file @ 590a94d9
...@@ -4,7 +4,6 @@ extern struct platform_device mxc_gpt3; ...@@ -4,7 +4,6 @@ extern struct platform_device mxc_gpt3;
extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt4;
extern struct platform_device mxc_gpt5; extern struct platform_device mxc_gpt5;
extern struct platform_device mxc_wdt; extern struct platform_device mxc_wdt;
extern struct platform_device mxc_irda_device;
extern struct platform_device mxc_uart_device0; extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1; extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2; extern struct platform_device mxc_uart_device2;
...@@ -20,3 +19,11 @@ extern struct platform_device mxc_i2c_device0; ...@@ -20,3 +19,11 @@ extern struct platform_device mxc_i2c_device0;
extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device1;
extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_spi_device0;
extern struct platform_device mxc_spi_device1;
extern struct platform_device mxc_spi_device2;
arch/arm/mach-mx2/eukrea_cpuimx27.c 0 → 100644
View file @ 590a94d9
/*
* Copyright (C) 2009 Eric Benard - eric@eukrea.com
*
* Based on pcm038.c which is :
* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/mtd/plat-ram.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/board-eukrea_cpuimx27.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/iomux.h>
#include <mach/imx-uart.h>
#include <mach/mxc_nand.h>
#include "devices.h"
static int eukrea_cpuimx27_pins[] = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* UART4 */
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
PB31_AF_UART4_RXD,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* I2C1 */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* SDHC2 */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/* Quad UART's IRQ */
GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
#endif
};
static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
.width = 2,
};
static struct resource eukrea_cpuimx27_flash_resource = {
.start = 0xc0000000,
.end = 0xc3ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &eukrea_cpuimx27_flash_data,
},
.num_resources = 1,
.resource = &eukrea_cpuimx27_flash_resource,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
}, {
.flags = IMXUART_HAVE_RTSCTS,
},
};
static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
.width = 1,
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_fec_device,
};
static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
.bitrate = 100000,
};
static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
{
I2C_BOARD_INFO("pcf8563", 0x51),
},
};
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
static struct plat_serial8250_port serial_platform_data[] = {
{
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000),
.irq = IRQ_GPIOB(23),
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000),
.irq = IRQ_GPIOB(22),
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000),
.irq = IRQ_GPIOB(27),
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000),
.irq = IRQ_GPIOB(30),
.uartclk = 14745600,
.regshift = 1,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
}
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = serial_platform_data,
},
};
#endif
static void __init eukrea_cpuimx27_init(void)
{
mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
/* SDHC2 can be used for Wifi */
mxc_register_device(&mxc_sdhc_device1, NULL);
/* in which case UART4 is also used for Bluetooth */
mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
#endif
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
platform_device_register(&serial_device);
#endif
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();
#endif
}
static void __init eukrea_cpuimx27_timer_init(void)
{
mx27_clocks_init(26000000);
}
static struct sys_timer eukrea_cpuimx27_timer = {
.init = eukrea_cpuimx27_timer_init,
};
MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
.phys_io = AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27_map_io,
.init_irq = mx27_init_irq,
.init_machine = eukrea_cpuimx27_init,
.timer = &eukrea_cpuimx27_timer,
MACHINE_END
arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c 0 → 100644
View file @ 590a94d9
/*
* Copyright (C) 2009 Eric Benard - eric@eukrea.com
*
* Based on pcm970-baseboard.c which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/iomux.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/imx-uart.h>
#include "devices.h"
static int eukrea_mbimx27_pins[] = {
/* UART2 */
PE3_PF_UART2_CTS,
PE4_PF_UART2_RTS,
PE6_PF_UART2_TXD,
PE7_PF_UART2_RXD,
/* UART3 */
PE8_PF_UART3_TXD,
PE9_PF_UART3_RXD,
PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS,
/* UART4 */
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
PB31_AF_UART4_RXD,
/* SDHC1*/
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* SPI1 */
PD28_PF_CSPI1_SS0,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
};
static struct gpio_led gpio_leds[] = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = GPIO_PORTF | 16,
},
{
.name = "led2",
.default_trigger = "none",
.active_low = 1,
.gpio = GPIO_PORTF | 19,
},
{
.name = "backlight",
.default_trigger = "backlight",
.active_low = 0,
.gpio = GPIO_PORTE | 5,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
{
.mode = {
.name = "CMO-QGVA",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = 156000,
.hsync_len = 30,
.left_margin = 38,
.right_margin = 20,
.vsync_len = 3,
.upper_margin = 15,
.lower_margin = 4,
},
.pcr = 0xFAD08B80,
.bpp = 16,
},
};
static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
.mode = eukrea_mbimx27_modes,
.num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00040060,
};
static struct imxuart_platform_data uart_pdata[] = {
{
.flags = IMXUART_HAVE_RTSCTS,
},
{
.flags = IMXUART_HAVE_RTSCTS,
},
};
#if defined(CONFIG_TOUCHSCREEN_ADS7846)
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
#define ADS7846_PENDOWN (GPIO_PORTD | 25)
static void ads7846_dev_init(void)
{
if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
printk(KERN_ERR "can't get ads746 pen down GPIO\n");
return;
}
gpio_direction_input(ADS7846_PENDOWN);
}
static int ads7846_get_pendown_state(void)
{
return !gpio_get_value(ADS7846_PENDOWN);
}
static struct ads7846_platform_data ads7846_config __initdata = {
.get_pendown_state = ads7846_get_pendown_state,
.keep_vref_on = 1,
};
static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
[0] = {
.modalias = "ads7846",
.bus_num = 0,
.chip_select = 0,
.max_speed_hz = 1500000,
.irq = IRQ_GPIOD(25),
.platform_data = &ads7846_config,
.mode = SPI_MODE_2,
},
};
static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
.chipselect = eukrea_mbimx27_spi_cs,
.num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
};
#endif
static struct platform_device *platform_devices[] __initdata = {
&leds_gpio,
};
/*
* system init for baseboard usage. Will be called by cpuimx27 init.
*
* Add platform devices present on this baseboard and init
* them from CPU side as far as required to use them later on
*/
void __init eukrea_mbimx27_baseboard_init(void)
{
mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
mxc_register_device(&mxc_sdhc_device0, NULL);
#if defined(CONFIG_TOUCHSCREEN_ADS7846)
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/* SPI and ADS7846 Touchscreen controler init */
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
spi_register_board_info(eukrea_mbimx27_spi_board_info,
ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
ads7846_dev_init();
#endif
/* Leds configuration */
mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
/* Backlight */
mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
arch/arm/mach-mx2/generic.c
View file @ 590a94d9
...@@ -72,6 +72,7 @@ static struct map_desc mxc_io_desc[] __initdata = { ...@@ -72,6 +72,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
void __init mx21_map_io(void) void __init mx21_map_io(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX21); mxc_set_cpu_type(MXC_CPU_MX21);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
} }
...@@ -79,7 +80,18 @@ void __init mx21_map_io(void) ...@@ -79,7 +80,18 @@ void __init mx21_map_io(void)
void __init mx27_map_io(void) void __init mx27_map_io(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX27); mxc_set_cpu_type(MXC_CPU_MX27);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
} }
void __init mx27_init_irq(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
}
void __init mx21_init_irq(void)
{
mx27_init_irq();
}
arch/arm/mach-mx2/mx21ads.c
View file @ 590a94d9
...@@ -164,23 +164,31 @@ static void mx21ads_fb_exit(struct platform_device *pdev) ...@@ -164,23 +164,31 @@ static void mx21ads_fb_exit(struct platform_device *pdev)
* Connected is a portrait Sharp-QVGA display * Connected is a portrait Sharp-QVGA display
* of type: LQ035Q7DB02 * of type: LQ035Q7DB02
*/ */
static struct imx_fb_platform_data mx21ads_fb_data = { static struct imx_fb_videomode mx21ads_modes[] = {
.pixclock = 188679, /* in ps */ {
.mode = {
.name = "Sharp-LQ035Q7",
.refresh = 60,
.xres = 240, .xres = 240,
.yres = 320, .yres = 320,
.pixclock = 188679, /* in ps (5.3MHz) */
.bpp = 16,
.hsync_len = 2, .hsync_len = 2,
.left_margin = 6, .left_margin = 6,
.right_margin = 16, .right_margin = 16,
.vsync_len = 1, .vsync_len = 1,
.upper_margin = 8, .upper_margin = 8,
.lower_margin = 10, .lower_margin = 10,
.fixed_screen_cpu = 0, },
.pcr = 0xfb108bc7,
.bpp = 16,
},
};
static struct imx_fb_platform_data mx21ads_fb_data = {
.mode = mx21ads_modes,
.num_modes = ARRAY_SIZE(mx21ads_modes),
.pcr = 0xFB108BC7, .pwmr = 0x00a903ff,
.pwmr = 0x00A901ff,
.lscr1 = 0x00120300, .lscr1 = 0x00120300,
.dmacr = 0x00020008, .dmacr = 0x00020008,
...@@ -280,7 +288,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS") ...@@ -280,7 +288,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx21ads_map_io, .map_io = mx21ads_map_io,
.init_irq = mxc_init_irq, .init_irq = mx21_init_irq,
.init_machine = mx21ads_board_init, .init_machine = mx21ads_board_init,
.timer = &mx21ads_timer, .timer = &mx21ads_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx2/mx27ads.c
View file @ 590a94d9
...@@ -183,20 +183,29 @@ void lcd_power(int on) ...@@ -183,20 +183,29 @@ void lcd_power(int on)
__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
} }
static struct imx_fb_platform_data mx27ads_fb_data = { static struct imx_fb_videomode mx27ads_modes[] = {
.pixclock = 188679, {
.mode = {
.name = "Sharp-LQ035Q7",
.refresh = 60,
.xres = 240, .xres = 240,
.yres = 320, .yres = 320,
.pixclock = 188679, /* in ps (5.3MHz) */
.bpp = 16,
.hsync_len = 1, .hsync_len = 1,
.left_margin = 9, .left_margin = 9,
.right_margin = 16, .right_margin = 16,
.vsync_len = 1, .vsync_len = 1,
.upper_margin = 7, .upper_margin = 7,
.lower_margin = 9, .lower_margin = 9,
.fixed_screen_cpu = 0, },
.bpp = 16,
.pcr = 0xFB008BC0,
},
};
static struct imx_fb_platform_data mx27ads_fb_data = {
.mode = mx27ads_modes,
.num_modes = ARRAY_SIZE(mx27ads_modes),
/* /*
* - HSYNC active high * - HSYNC active high
...@@ -207,7 +216,6 @@ static struct imx_fb_platform_data mx27ads_fb_data = { ...@@ -207,7 +216,6 @@ static struct imx_fb_platform_data mx27ads_fb_data = {
* - data enable low active * - data enable low active
* - enable sharp mode * - enable sharp mode
*/ */
.pcr = 0xFB008BC0,
.pwmr = 0x00A903FF, .pwmr = 0x00A903FF,
.lscr1 = 0x00120300, .lscr1 = 0x00120300,
.dmacr = 0x00020010, .dmacr = 0x00020010,
...@@ -330,7 +338,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") ...@@ -330,7 +338,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27ads_map_io, .map_io = mx27ads_map_io,
.init_irq = mxc_init_irq, .init_irq = mx27_init_irq,
.init_machine = mx27ads_board_init, .init_machine = mx27ads_board_init,
.timer = &mx27ads_timer, .timer = &mx27ads_timer,
MACHINE_END MACHINE_END
......
arch/arm/mach-mx2/mx27lite.c
View file @ 590a94d9
...@@ -89,7 +89,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") ...@@ -89,7 +89,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mxc_init_irq, .init_irq = mx27_init_irq,
.init_machine = mx27lite_init, .init_machine = mx27lite_init,
.timer = &mx27lite_timer, .timer = &mx27lite_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx2/mx27pdk.c
View file @ 590a94d9
...@@ -89,7 +89,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK") ...@@ -89,7 +89,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mxc_init_irq, .init_irq = mx27_init_irq,
.init_machine = mx27pdk_init, .init_machine = mx27pdk_init,
.timer = &mx27pdk_timer, .timer = &mx27pdk_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx2/pca100.c 0 → 100644
View file @ 590a94d9
/*
* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
* Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/dma-mapping.h>
#include <linux/spi/spi.h>
#include <linux/spi/eeprom.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux.h>
#include <mach/i2c.h>
#include <asm/mach/time.h>
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
#include <mach/spi.h>
#endif
#include <mach/imx-uart.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
#include "devices.h"
static int pca100_pins[] = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* SDHC */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* SSI1 */
PC20_PF_SSI1_FS,
PC21_PF_SSI1_RXD,
PC22_PF_SSI1_TXD,
PC23_PF_SSI1_CLK,
/* onboard I2C */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
/* external I2C */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* SPI1 */
PD25_PF_CSPI1_RDY,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
};
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct mxc_nand_platform_data pca100_nand_board_info = {
.width = 1,
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
&mxc_fec_device,
};
static struct imxi2c_platform_data pca100_i2c_1_data = {
.bitrate = 100000,
};
static struct at24_platform_data board_eeprom = {
.byte_len = 4096,
.page_size = 32,
.flags = AT24_FLAG_ADDR16,
};
static struct i2c_board_info pca100_i2c_devices[] = {
{
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom,
}, {
I2C_BOARD_INFO("rtc-pcf8563", 0x51),
.type = "pcf8563"
}, {
I2C_BOARD_INFO("lm75", 0x4a),
.type = "lm75"
}
};
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
static struct spi_eeprom at25320 = {
.name = "at25320an",
.byte_len = 4096,
.page_size = 32,
.flags = EE_ADDR2,
};
static struct spi_board_info pca100_spi_board_info[] __initdata = {
{
.modalias = "at25",
.max_speed_hz = 30000,
.bus_num = 0,
.chip_select = 1,
.platform_data = &at25320,
},
};
static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
static struct spi_imx_master pca100_spi_0_data = {
.chipselect = pca100_spi_cs,
.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
};
#endif
static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
int ret;
ret = request_irq(IRQ_GPIOC(29), detect_irq,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"imx-mmc-detect", data);
if (ret)
printk(KERN_ERR
"pca100: Failed to reuest irq for sd/mmc detection\n");
return ret;
}
static void pca100_sdhc2_exit(struct device *dev, void *data)
{
free_irq(IRQ_GPIOC(29), data);
}
static struct imxmmc_platform_data sdhc_pdata = {
.init = pca100_sdhc2_init,
.exit = pca100_sdhc2_exit,
};
static void __init pca100_init(void)
{
int ret;
ret = mxc_gpio_setup_multiple_pins(pca100_pins,
ARRAY_SIZE(pca100_pins), "PCA100");
if (ret)
printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
mxc_register_device(&mxc_nand_device, &pca100_nand_board_info);
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, pca100_i2c_devices,
ARRAY_SIZE(pca100_i2c_devices));
mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
/* GPIO0_IRQ */
mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
/* GPIO1_IRQ */
mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
/* GPIO2_IRQ */
mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
spi_register_board_info(pca100_spi_board_info,
ARRAY_SIZE(pca100_spi_board_info));
mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
#endif
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
static void __init pca100_timer_init(void)
{
mx27_clocks_init(26000000);
}
static struct sys_timer pca100_timer = {
.init = pca100_timer_init,
};
MACHINE_START(PCA100, "phyCARD-i.MX27")
.phys_io = AIPI_BASE_ADDR,
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27_map_io,
.init_irq = mxc_init_irq,
.init_machine = pca100_init,
.timer = &pca100_timer,
MACHINE_END
arch/arm/mach-mx2/pcm038.c
View file @ 590a94d9
...@@ -186,17 +186,13 @@ static struct at24_platform_data board_eeprom = { ...@@ -186,17 +186,13 @@ static struct at24_platform_data board_eeprom = {
}; };
static struct i2c_board_info pcm038_i2c_devices[] = { static struct i2c_board_info pcm038_i2c_devices[] = {
[0] = { {
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom, .platform_data = &board_eeprom,
}, }, {
[1] = { I2C_BOARD_INFO("pcf8563", 0x51),
I2C_BOARD_INFO("rtc-pcf8563", 0x51), }, {
.type = "pcf8563"
},
[2] = {
I2C_BOARD_INFO("lm75", 0x4a), I2C_BOARD_INFO("lm75", 0x4a),
.type = "lm75"
} }
}; };
...@@ -220,6 +216,9 @@ static void __init pcm038_init(void) ...@@ -220,6 +216,9 @@ static void __init pcm038_init(void)
mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
/* PE18 for user-LED D40 */
mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#ifdef CONFIG_MACH_PCM970_BASEBOARD #ifdef CONFIG_MACH_PCM970_BASEBOARD
...@@ -241,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27") ...@@ -241,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx27_map_io, .map_io = mx27_map_io,
.init_irq = mxc_init_irq, .init_irq = mx27_init_irq,
.init_machine = pcm038_init, .init_machine = pcm038_init,
.timer = &pcm038_timer, .timer = &pcm038_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx2/pcm970-baseboard.c
View file @ 590a94d9
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/can/platform/sja1000.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -125,25 +126,21 @@ static struct imxmmc_platform_data sdhc_pdata = { ...@@ -125,25 +126,21 @@ static struct imxmmc_platform_data sdhc_pdata = {
.exit = pcm970_sdhc2_exit, .exit = pcm970_sdhc2_exit,
}; };
/* static struct imx_fb_videomode pcm970_modes[] = {
* Connected is a portrait Sharp-QVGA display {
* of type: LQ035Q7DH06 .mode = {
*/ .name = "Sharp-LQ035Q7",
static struct imx_fb_platform_data pcm038_fb_data = { .refresh = 60,
.pixclock = 188679, /* in ps (5.3MHz) */
.xres = 240, .xres = 240,
.yres = 320, .yres = 320,
.pixclock = 188679, /* in ps (5.3MHz) */
.bpp = 16,
.hsync_len = 7, .hsync_len = 7,
.left_margin = 5, .left_margin = 5,
.right_margin = 16, .right_margin = 16,
.vsync_len = 1, .vsync_len = 1,
.upper_margin = 7, .upper_margin = 7,
.lower_margin = 9, .lower_margin = 9,
.fixed_screen_cpu = 0, },
/* /*
* - HSYNC active high * - HSYNC active high
* - VSYNC active high * - VSYNC active high
...@@ -153,12 +150,72 @@ static struct imx_fb_platform_data pcm038_fb_data = { ...@@ -153,12 +150,72 @@ static struct imx_fb_platform_data pcm038_fb_data = {
* - data enable low active * - data enable low active
* - enable sharp mode * - enable sharp mode
*/ */
.pcr = 0xFA0080C0, .pcr = 0xF00080C0,
.bpp = 16,
}, {
.mode = {
.name = "TX090",
.refresh = 60,
.xres = 240,
.yres = 320,
.pixclock = 38255,
.left_margin = 144,
.right_margin = 0,
.upper_margin = 7,
.lower_margin = 40,
.hsync_len = 96,
.vsync_len = 1,
},
/*
* - HSYNC active low (1 << 22)
* - VSYNC active low (1 << 23)
* - clk notenabled while idle
* - clock not inverted
* - data not inverted
* - data enable low active
* - enable sharp mode
*/
.pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
.bpp = 32,
},
};
static struct imx_fb_platform_data pcm038_fb_data = {
.mode = pcm970_modes,
.num_modes = ARRAY_SIZE(pcm970_modes),
.pwmr = 0x00A903FF, .pwmr = 0x00A903FF,
.lscr1 = 0x00120300, .lscr1 = 0x00120300,
.dmacr = 0x00020010, .dmacr = 0x00020010,
}; };
static struct resource pcm970_sja1000_resources[] = {
{
.start = CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_GPIOE(19),
.end = IRQ_GPIOE(19),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
struct sja1000_platform_data pcm970_sja1000_platform_data = {
.clock = 16000000 / 2,
.ocr = 0x40 | 0x18,
.cdr = 0x40,
};
static struct platform_device pcm970_sja1000 = {
.name = "sja1000_platform",
.dev = {
.platform_data = &pcm970_sja1000_platform_data,
},
.resource = pcm970_sja1000_resources,
.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
};
/* /*
* system init for baseboard usage. Will be called by pcm038 init. * system init for baseboard usage. Will be called by pcm038 init.
* *
...@@ -172,4 +229,5 @@ void __init pcm970_baseboard_init(void) ...@@ -172,4 +229,5 @@ void __init pcm970_baseboard_init(void)
mxc_register_device(&mxc_fb_device, &pcm038_fb_data); mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
platform_device_register(&pcm970_sja1000);
} }
arch/arm/mach-mx25/Kconfig 0 → 100644
View file @ 590a94d9
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
select ARCH_MXC_IOMUX_V3
bool "Support MX25PDK (3DS) Platform"
endif
arch/arm/mach-mx25/Makefile 0 → 100644
View file @ 590a94d9
obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX25) += clock.o
obj-$(CONFIG_MACH_MX25_3DS) += mx25pdk.o
arch/arm/mach-mx25/Makefile.boot 0 → 100644
View file @ 590a94d9
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000
arch/arm/mach-mx25/clock.c 0 → 100644
View file @ 590a94d9
/*
* Copyright (C) 2009 by Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/clkdev.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mx25.h>
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
#define CCM_MPCTL 0x00
#define CCM_UPCTL 0x04
#define CCM_CCTL 0x08
#define CCM_CGCR0 0x0C
#define CCM_CGCR1 0x10
#define CCM_CGCR2 0x14
#define CCM_PCDR0 0x18
#define CCM_PCDR1 0x1C
#define CCM_PCDR2 0x20
#define CCM_PCDR3 0x24
#define CCM_RCSR 0x28
#define CCM_CRDR 0x2C
#define CCM_DCVR0 0x30
#define CCM_DCVR1 0x34
#define CCM_DCVR2 0x38
#define CCM_DCVR3 0x3c
#define CCM_LTR0 0x40
#define CCM_LTR1 0x44
#define CCM_LTR2 0x48
#define CCM_LTR3 0x4c
static unsigned long get_rate_mpll(void)
{
ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
return mxc_decode_pll(mpctl, 24000000);
}
static unsigned long get_rate_upll(void)
{
ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
return mxc_decode_pll(mpctl, 24000000);
}
unsigned long get_rate_arm(struct clk *clk)
{
unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
unsigned long rate = get_rate_mpll();
if (cctl & (1 << 14))
rate = (rate * 3) >> 1;
return rate / ((cctl >> 30) + 1);
}
static unsigned long get_rate_ahb(struct clk *clk)
{
unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
}
static unsigned long get_rate_ipg(struct clk *clk)
{
return get_rate_ahb(NULL) >> 1;
}
static unsigned long get_rate_per(int per)
{
unsigned long ofs = (per & 0x3) * 8;
unsigned long reg = per & ~0x3;
unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
unsigned long fref;
if (readl(CRM_BASE + 0x64) & (1 << per))
fref = get_rate_upll();
else
fref = get_rate_ipg(NULL);
return fref / (val + 1);
}
static unsigned long get_rate_uart(struct clk *clk)
{
return get_rate_per(15);
}
static unsigned long get_rate_i2c(struct clk *clk)
{
return get_rate_per(6);
}
static unsigned long get_rate_nfc(struct clk *clk)
{
return get_rate_per(8);
}
static unsigned long get_rate_otg(struct clk *clk)
{
return 48000000; /* FIXME */
}
static int clk_cgcr_enable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= 1 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void clk_cgcr_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(1 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
static struct clk name = { \
.id = i, \
.enable_reg = CRM_BASE + er, \
.enable_shift = es, \
.get_rate = gr, \
.set_rate = sr, \
.enable = clk_cgcr_enable, \
.disable = clk_cgcr_disable, \
}
DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL);
DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL);
DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL);
DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL);
DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL);
DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL);
DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);
DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL);
DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL);
DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL);
DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL);
DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL);
DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL);
DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL);
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
_REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
_REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
_REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
_REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
_REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
_REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
_REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
};
int __init mx25_clocks_init(unsigned long fref)
{
int i;
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
return 0;
}
arch/arm/mach-mx25/devices.c 0 → 100644
View file @ 590a94d9
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <mach/mx25.h>
#include <mach/irqs.h>
static struct resource uart0[] = {
{
.start = 0x43f90000,
.end = 0x43f93fff,
.flags = IORESOURCE_MEM,
}, {
.start = 45,
.end = 45,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device0 = {
.name = "imx-uart",
.id = 0,
.resource = uart0,
.num_resources = ARRAY_SIZE(uart0),
};
static struct resource uart1[] = {
{
.start = 0x43f94000,
.end = 0x43f97fff,
.flags = IORESOURCE_MEM,
}, {
.start = 32,
.end = 32,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device1 = {
.name = "imx-uart",
.id = 1,
.resource = uart1,
.num_resources = ARRAY_SIZE(uart1),
};
static struct resource uart2[] = {
{
.start = 0x5000c000,
.end = 0x5000ffff,
.flags = IORESOURCE_MEM,
}, {
.start = 18,
.end = 18,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device2 = {
.name = "imx-uart",
.id = 2,
.resource = uart2,
.num_resources = ARRAY_SIZE(uart2),
};
static struct resource uart3[] = {
{
.start = 0x50008000,
.end = 0x5000bfff,
.flags = IORESOURCE_MEM,
}, {
.start = 5,
.end = 5,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device3 = {
.name = "imx-uart",
.id = 3,
.resource = uart3,
.num_resources = ARRAY_SIZE(uart3),
};
static struct resource uart4[] = {
{
.start = 0x5002c000,
.end = 0x5002ffff,
.flags = IORESOURCE_MEM,
}, {
.start = 40,
.end = 40,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device4 = {
.name = "imx-uart",
.id = 4,
.resource = uart4,
.num_resources = ARRAY_SIZE(uart4),
};
#define MX25_OTG_BASE_ADDR 0x53FF4000
static u64 otg_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_otg_resources[] = {
{
.start = MX25_OTG_BASE_ADDR,
.end = MX25_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = 37,
.end = 37,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_otg = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
/* OTG gadget device */
struct platform_device otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX25_OTG_BASE_ADDR + 0x400,
.end = MX25_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = 35,
.end = 35,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource mxc_spi_resources0[] = {
{
.start = 0x43fa4000,
.end = 0x43fa7fff,
.flags = IORESOURCE_MEM,
}, {
.start = 14,
.end = 14,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_spi_device0 = {
.name = "spi_imx",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_spi_resources0),
.resource = mxc_spi_resources0,
};
static struct resource mxc_spi_resources1[] = {
{
.start = 0x50010000,
.end = 0x50013fff,
.flags = IORESOURCE_MEM,
}, {
.start = 13,
.end = 13,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_spi_device1 = {
.name = "spi_imx",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_spi_resources1),
.resource = mxc_spi_resources1,
};
static struct resource mxc_spi_resources2[] = {
{
.start = 0x50004000,
.end = 0x50007fff,
.flags = IORESOURCE_MEM,
}, {
.start = 0,
.end = 0,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_spi_device2 = {
.name = "spi_imx",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_spi_resources2),
.resource = mxc_spi_resources2,
};
static struct resource mxc_pwm_resources0[] = {
{
.start = 0x53fe0000,
.end = 0x53fe3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 26,
.end = 26,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device0 = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources0),
.resource = mxc_pwm_resources0,
};
static struct resource mxc_pwm_resources1[] = {
{
.start = 0x53fa0000,
.end = 0x53fa3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 36,
.end = 36,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device1 = {
.name = "mxc_pwm",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_pwm_resources1),
.resource = mxc_pwm_resources1,
};
static struct resource mxc_pwm_resources2[] = {
{
.start = 0x53fa8000,
.end = 0x53fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 41,
.end = 41,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device2 = {
.name = "mxc_pwm",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_pwm_resources2),
.resource = mxc_pwm_resources2,
};
static struct resource mxc_keypad_resources[] = {
{
.start = 0x43fa8000,
.end = 0x43fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 24,
.end = 24,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_keypad_device = {
.name = "mxc-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mxc_keypad_resources),
.resource = mxc_keypad_resources,
};
static struct resource mxc_pwm_resources3[] = {
{
.start = 0x53fc8000,
.end = 0x53fcbfff,
.flags = IORESOURCE_MEM,
}, {
.start = 42,
.end = 42,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device3 = {
.name = "mxc_pwm",
.id = 3,
.num_resources = ARRAY_SIZE(mxc_pwm_resources3),
.resource = mxc_pwm_resources3,
};
static struct resource mxc_i2c_1_resources[] = {
{
.start = 0x43f80000,
.end = 0x43f83fff,
.flags = IORESOURCE_MEM,
}, {
.start = 3,
.end = 3,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_i2c_device0 = {
.name = "imx-i2c",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
.resource = mxc_i2c_1_resources,
};
static struct resource mxc_i2c_2_resources[] = {
{
.start = 0x43f98000,
.end = 0x43f9bfff,
.flags = IORESOURCE_MEM,
}, {
.start = 4,
.end = 4,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_i2c_device1 = {
.name = "imx-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
.resource = mxc_i2c_2_resources,
};
static struct resource mxc_i2c_3_resources[] = {
{
.start = 0x43f84000,
.end = 0x43f87fff,
.flags = IORESOURCE_MEM,
}, {
.start = 10,
.end = 10,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_i2c_device2 = {
.name = "imx-i2c",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
.resource = mxc_i2c_3_resources,
};
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
.irq = 52,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
.irq = 51,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
.irq = 16,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
.irq = 23,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init mxc_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
arch/arm/mach-mx25/devices.h 0 → 100644
View file @ 590a94d9
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2;
extern struct platform_device mxc_uart_device3;
extern struct platform_device mxc_uart_device4;
extern struct platform_device mxc_otg;
extern struct platform_device otg_udc_device;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_spi_device0;
extern struct platform_device mxc_spi_device1;
extern struct platform_device mxc_spi_device2;
extern struct platform_device mxc_pwm_device0;
extern struct platform_device mxc_pwm_device1;
extern struct platform_device mxc_pwm_device2;
extern struct platform_device mxc_pwm_device3;
extern struct platform_device mxc_keypad_device;
extern struct platform_device mxc_i2c_device0;
extern struct platform_device mxc_i2c_device1;
extern struct platform_device mxc_i2c_device2;
arch/arm/mach-mx25/mm.c 0 → 100644
View file @ 590a94d9
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/mx25.h>
#include <mach/iomux-v3.h>
/*
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX25_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
.length = MX25_AVIC_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
.length = MX25_AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
.length = MX25_AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
},
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx25_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX25);
mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
void __init mx25_init_irq(void)
{
mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
}
arch/arm/mach-mx25/mx25pdk.c 0 → 100644
View file @ 590a94d9
#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/mx25.h>
#include <mach/mxc_nand.h>
#include "devices.h"
#include <mach/iomux-v3.h>
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct mxc_nand_platform_data nand_board_info = {
.width = 1,
.hw_ecc = 1,
};
static void __init mx25pdk_init(void)
{
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_usbh2, NULL);
mxc_register_device(&mxc_nand_device, &nand_board_info);
}
static void __init mx25pdk_timer_init(void)
{
mx25_clocks_init(26000000);
}
static struct sys_timer mx25pdk_timer = {
.init = mx25pdk_timer_init,
};
MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = MX25_AIPS1_BASE_ADDR,
.io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx25_map_io,
.init_irq = mx25_init_irq,
.init_machine = mx25pdk_init,
.timer = &mx25pdk_timer,
MACHINE_END
arch/arm/mach-mx3/armadillo5x0.c
View file @ 590a94d9
...@@ -352,7 +352,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500") ...@@ -352,7 +352,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x00000100, .boot_params = PHYS_OFFSET + 0x00000100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.timer = &armadillo5x0_timer, .timer = &armadillo5x0_timer,
.init_machine = armadillo5x0_init, .init_machine = armadillo5x0_init,
MACHINE_END MACHINE_END
arch/arm/mach-mx3/clock-imx35.c
View file @ 590a94d9
...@@ -273,6 +273,19 @@ static unsigned long get_rate_csi(struct clk *clk) ...@@ -273,6 +273,19 @@ static unsigned long get_rate_csi(struct clk *clk)
return rate / get_3_3_div((pdr2 >> 16) & 0x3f); return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
} }
static unsigned long get_rate_otg(struct clk *clk)
{
unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
unsigned long rate;
if (pdr4 & (1 << 9))
rate = get_rate_arm();
else
rate = get_rate_ppll();
return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
}
static unsigned long get_rate_ipg_per(struct clk *clk) static unsigned long get_rate_ipg_per(struct clk *clk)
{ {
unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
...@@ -365,7 +378,7 @@ DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL); ...@@ -365,7 +378,7 @@ DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL); DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL); DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL); DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL);
...@@ -426,7 +439,10 @@ static struct clk_lookup lookups[] = { ...@@ -426,7 +439,10 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK(NULL, "usbotg", usbotg_clk) _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk) _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk)
_REGISTER_CLOCK(NULL, "max", max_clk) _REGISTER_CLOCK(NULL, "max", max_clk)
_REGISTER_CLOCK(NULL, "admux", admux_clk) _REGISTER_CLOCK(NULL, "admux", admux_clk)
...@@ -456,7 +472,7 @@ int __init mx35_clocks_init() ...@@ -456,7 +472,7 @@ int __init mx35_clocks_init()
__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
__raw_writel(0, CCM_BASE + CCM_CGR3); __raw_writel(0, CCM_BASE + CCM_CGR3);
mxc_timer_init(&gpt_clk); mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
return 0; return 0;
} }
......
arch/arm/mach-mx3/clock.c
View file @ 590a94d9
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/mx31.h>
#include <mach/common.h> #include <mach/common.h>
#include "crm_regs.h" #include "crm_regs.h"
...@@ -402,6 +403,11 @@ static unsigned long clk_ckih_get_rate(struct clk *clk) ...@@ -402,6 +403,11 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
return ckih_rate; return ckih_rate;
} }
static unsigned long clk_ckil_get_rate(struct clk *clk)
{
return CKIL_CLK_FREQ;
}
static struct clk ckih_clk = { static struct clk ckih_clk = {
.get_rate = clk_ckih_get_rate, .get_rate = clk_ckih_get_rate,
}; };
...@@ -508,6 +514,7 @@ DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk) ...@@ -508,6 +514,7 @@ DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk)
DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk); DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
#define _REGISTER_CLOCK(d, n, c) \ #define _REGISTER_CLOCK(d, n, c) \
{ \ { \
...@@ -518,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); ...@@ -518,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
static struct clk_lookup lookups[] = { static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "emi", emi_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk)
_REGISTER_CLOCK(NULL, "cspi", cspi1_clk) _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
_REGISTER_CLOCK(NULL, "cspi", cspi2_clk) _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
_REGISTER_CLOCK(NULL, "cspi", cspi3_clk) _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
_REGISTER_CLOCK(NULL, "pwm", pwm_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
_REGISTER_CLOCK(NULL, "wdog", wdog_clk) _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
...@@ -531,6 +538,12 @@ static struct clk_lookup lookups[] = { ...@@ -531,6 +538,12 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("ipu-core", NULL, ipu_clk) _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
_REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
_REGISTER_CLOCK(NULL, "kpp", kpp_clk) _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
_REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
_REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk) _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
...@@ -559,6 +572,7 @@ static struct clk_lookup lookups[] = { ...@@ -559,6 +572,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "iim", iim_clk) _REGISTER_CLOCK(NULL, "iim", iim_clk)
_REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk) _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
_REGISTER_CLOCK(NULL, "mbx", mbx_clk) _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
_REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
}; };
int __init mx31_clocks_init(unsigned long fref) int __init mx31_clocks_init(unsigned long fref)
...@@ -609,7 +623,7 @@ int __init mx31_clocks_init(unsigned long fref) ...@@ -609,7 +623,7 @@ int __init mx31_clocks_init(unsigned long fref)
__raw_writel(reg, MXC_CCM_PMCR1); __raw_writel(reg, MXC_CCM_PMCR1);
} }
mxc_timer_init(&ipg_clk); mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
return 0; return 0;
} }
......
arch/arm/mach-mx3/devices.c
View file @ 590a94d9
...@@ -129,19 +129,17 @@ struct platform_device mxc_uart_device4 = { ...@@ -129,19 +129,17 @@ struct platform_device mxc_uart_device4 = {
/* GPIO port description */ /* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = { static struct mxc_gpio_port imx_gpio_ports[] = {
[0] = { {
.chip.label = "gpio-0", .chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR), .base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1, .irq = MXC_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_IRQ_START, .virtual_irq_start = MXC_GPIO_IRQ_START,
}, }, {
[1] = {
.chip.label = "gpio-1", .chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR), .base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2, .irq = MXC_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32, .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, }, {
[2] = {
.chip.label = "gpio-2", .chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR), .base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3, .irq = MXC_INT_GPIO3,
...@@ -173,11 +171,11 @@ static struct resource mxc_nand_resources[] = { ...@@ -173,11 +171,11 @@ static struct resource mxc_nand_resources[] = {
{ {
.start = 0, /* runtime dependent */ .start = 0, /* runtime dependent */
.end = 0, .end = 0,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_NANDFC, .start = MXC_INT_NANDFC,
.end = MXC_INT_NANDFC, .end = MXC_INT_NANDFC,
.flags = IORESOURCE_IRQ .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -193,8 +191,7 @@ static struct resource mxc_i2c0_resources[] = { ...@@ -193,8 +191,7 @@ static struct resource mxc_i2c0_resources[] = {
.start = I2C_BASE_ADDR, .start = I2C_BASE_ADDR,
.end = I2C_BASE_ADDR + SZ_4K - 1, .end = I2C_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
{
.start = MXC_INT_I2C, .start = MXC_INT_I2C,
.end = MXC_INT_I2C, .end = MXC_INT_I2C,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -213,8 +210,7 @@ static struct resource mxc_i2c1_resources[] = { ...@@ -213,8 +210,7 @@ static struct resource mxc_i2c1_resources[] = {
.start = I2C2_BASE_ADDR, .start = I2C2_BASE_ADDR,
.end = I2C2_BASE_ADDR + SZ_4K - 1, .end = I2C2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
{
.start = MXC_INT_I2C2, .start = MXC_INT_I2C2,
.end = MXC_INT_I2C2, .end = MXC_INT_I2C2,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -233,8 +229,7 @@ static struct resource mxc_i2c2_resources[] = { ...@@ -233,8 +229,7 @@ static struct resource mxc_i2c2_resources[] = {
.start = I2C3_BASE_ADDR, .start = I2C3_BASE_ADDR,
.end = I2C3_BASE_ADDR + SZ_4K - 1, .end = I2C3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
{
.start = MXC_INT_I2C3, .start = MXC_INT_I2C3,
.end = MXC_INT_I2C3, .end = MXC_INT_I2C3,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -371,8 +366,8 @@ struct platform_device mx3_camera = { ...@@ -371,8 +366,8 @@ struct platform_device mx3_camera = {
static struct resource otg_resources[] = { static struct resource otg_resources[] = {
{ {
.start = OTG_BASE_ADDR, .start = MX31_OTG_BASE_ADDR,
.end = OTG_BASE_ADDR + 0x1ff, .end = MX31_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_USB3, .start = MXC_INT_USB3,
...@@ -395,16 +390,142 @@ struct platform_device mxc_otg_udc_device = { ...@@ -395,16 +390,142 @@ struct platform_device mxc_otg_udc_device = {
.num_resources = ARRAY_SIZE(otg_resources), .num_resources = ARRAY_SIZE(otg_resources),
}; };
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = ~(u32)0;
static struct resource mxc_usbh1_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x200,
.end = MX31_OTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB1,
.end = MXC_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;
static struct resource mxc_usbh2_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x400,
.end = MX31_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB2,
.end = MXC_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
/*
* SPI master controller
* 3 channels
*/
static struct resource imx_spi_0_resources[] = {
{
.start = CSPI1_BASE_ADDR,
.end = CSPI1_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI1,
.end = MXC_INT_CSPI1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource imx_spi_1_resources[] = {
{
.start = CSPI2_BASE_ADDR,
.end = CSPI2_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI2,
.end = MXC_INT_CSPI2,
.flags = IORESOURCE_IRQ,
},
};
static struct resource imx_spi_2_resources[] = {
{
.start = CSPI3_BASE_ADDR,
.end = CSPI3_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_CSPI3,
.end = MXC_INT_CSPI3,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_spi_device0 = {
.name = "spi_imx",
.id = 0,
.num_resources = ARRAY_SIZE(imx_spi_0_resources),
.resource = imx_spi_0_resources,
};
struct platform_device imx_spi_device1 = {
.name = "spi_imx",
.id = 1,
.num_resources = ARRAY_SIZE(imx_spi_1_resources),
.resource = imx_spi_1_resources,
};
struct platform_device imx_spi_device2 = {
.name = "spi_imx",
.id = 2,
.num_resources = ARRAY_SIZE(imx_spi_2_resources),
.resource = imx_spi_2_resources,
};
#ifdef CONFIG_ARCH_MX35 #ifdef CONFIG_ARCH_MX35
static struct resource mxc_fec_resources[] = { static struct resource mxc_fec_resources[] = {
{ {
.start = MXC_FEC_BASE_ADDR, .start = MXC_FEC_BASE_ADDR,
.end = MXC_FEC_BASE_ADDR + 0xfff, .end = MXC_FEC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM .flags = IORESOURCE_MEM,
}, { }, {
.start = MXC_INT_FEC, .start = MXC_INT_FEC,
.end = MXC_INT_FEC, .end = MXC_INT_FEC,
.flags = IORESOURCE_IRQ .flags = IORESOURCE_IRQ,
}, },
}; };
...@@ -426,6 +547,14 @@ static int mx3_devices_init(void) ...@@ -426,6 +547,14 @@ static int mx3_devices_init(void)
if (cpu_is_mx35()) { if (cpu_is_mx35()) {
mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
otg_resources[0].start = MX35_OTG_BASE_ADDR;
otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
otg_resources[1].start = MXC_INT_USBOTG;
otg_resources[1].end = MXC_INT_USBOTG;
mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
mxc_usbh1_resources[1].start = MXC_INT_USBHS;
mxc_usbh1_resources[1].end = MXC_INT_USBHS;
} }
return 0; return 0;
......
arch/arm/mach-mx3/devices.h
View file @ 590a94d9
...@@ -16,5 +16,11 @@ extern struct platform_device mxc_fec_device; ...@@ -16,5 +16,11 @@ extern struct platform_device mxc_fec_device;
extern struct platform_device mxcsdhc_device0; extern struct platform_device mxcsdhc_device0;
extern struct platform_device mxcsdhc_device1; extern struct platform_device mxcsdhc_device1;
extern struct platform_device mxc_otg_udc_device; extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_rnga_device; extern struct platform_device mxc_rnga_device;
extern struct platform_device imx_spi_device0;
extern struct platform_device imx_spi_device1;
extern struct platform_device imx_spi_device2;
arch/arm/mach-mx3/mm.c
View file @ 590a94d9
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <mach/common.h> #include <mach/common.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/iomux-v3.h>
/*! /*!
* @file mm.c * @file mm.c
...@@ -75,6 +76,7 @@ static struct map_desc mxc_io_desc[] __initdata = { ...@@ -75,6 +76,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
void __init mx31_map_io(void) void __init mx31_map_io(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX31); mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
} }
...@@ -82,10 +84,22 @@ void __init mx31_map_io(void) ...@@ -82,10 +84,22 @@ void __init mx31_map_io(void)
void __init mx35_map_io(void) void __init mx35_map_io(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX35); mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
} }
void __init mx31_init_irq(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
}
void __init mx35_init_irq(void)
{
mx31_init_irq();
}
#ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void) static int mxc_init_l2x0(void)
{ {
......
arch/arm/mach-mx3/mx31ads.c
View file @ 590a94d9
...@@ -517,7 +517,7 @@ static void __init mx31ads_map_io(void) ...@@ -517,7 +517,7 @@ static void __init mx31ads_map_io(void)
static void __init mx31ads_init_irq(void) static void __init mx31ads_init_irq(void)
{ {
mxc_init_irq(); mx31_init_irq();
mx31ads_init_expio(); mx31ads_init_expio();
} }
......
arch/arm/mach-mx3/mx31lilly.c
View file @ 590a94d9
...@@ -148,7 +148,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131") ...@@ -148,7 +148,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.init_machine = mx31lilly_board_init, .init_machine = mx31lilly_board_init,
.timer = &mx31lilly_timer, .timer = &mx31lilly_timer,
MACHINE_END MACHINE_END
......
arch/arm/mach-mx3/mx31lite.c
View file @ 590a94d9
...@@ -71,12 +71,11 @@ static struct smsc911x_platform_config smsc911x_config = { ...@@ -71,12 +71,11 @@ static struct smsc911x_platform_config smsc911x_config = {
}; };
static struct resource smsc911x_resources[] = { static struct resource smsc911x_resources[] = {
[0] = { {
.start = CS4_BASE_ADDR, .start = CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 0x100, .end = CS4_BASE_ADDR + 0x100,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = IOMUX_TO_IRQ(MX31_PIN_SFS6), .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
.end = IOMUX_TO_IRQ(MX31_PIN_SFS6), .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -162,7 +161,7 @@ MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT") ...@@ -162,7 +161,7 @@ MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31lite_map_io, .map_io = mx31lite_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &mx31lite_timer, .timer = &mx31lite_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx3/mx31moboard-devboard.c
View file @ 590a94d9
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
#include <linux/fsl_devices.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -40,18 +39,6 @@ static unsigned int devboard_pins[] = { ...@@ -40,18 +39,6 @@ static unsigned int devboard_pins[] = {
MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
/* USB OTG */
MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
MX31_PIN_USB_OC__GPIO1_30,
}; };
static struct imxuart_platform_data uart_pdata = { static struct imxuart_platform_data uart_pdata = {
...@@ -111,33 +98,6 @@ static struct imxmmc_platform_data sdhc2_pdata = { ...@@ -111,33 +98,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
.exit = devboard_sdhc2_exit, .exit = devboard_sdhc2_exit,
}; };
static struct fsl_usb2_platform_data usb_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
static void devboard_usbotg_init(void)
{
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
gpio_request(OTG_EN_B, "usb-udc-en");
gpio_direction_output(OTG_EN_B, 0);
}
/* /*
* system init for baseboard usage. Will be called by mx31moboard init. * system init for baseboard usage. Will be called by mx31moboard init.
*/ */
...@@ -151,7 +111,4 @@ void __init mx31moboard_devboard_init(void) ...@@ -151,7 +111,4 @@ void __init mx31moboard_devboard_init(void)
mxc_register_device(&mxc_uart_device1, &uart_pdata); mxc_register_device(&mxc_uart_device1, &uart_pdata);
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
devboard_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
} }
arch/arm/mach-mx3/mx31moboard-marxbot.c
View file @ 590a94d9
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
#include <linux/fsl_devices.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -48,18 +47,8 @@ static unsigned int marxbot_pins[] = { ...@@ -48,18 +47,8 @@ static unsigned int marxbot_pins[] = {
MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
MX31_PIN_TXD2__GPIO1_28, MX31_PIN_TXD2__GPIO1_28,
/* USB OTG */ /* dsPIC resets */
MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
MX31_PIN_USB_OC__GPIO1_30,
}; };
#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
...@@ -115,31 +104,20 @@ static struct imxmmc_platform_data sdhc2_pdata = { ...@@ -115,31 +104,20 @@ static struct imxmmc_platform_data sdhc2_pdata = {
.exit = marxbot_sdhc2_exit, .exit = marxbot_sdhc2_exit,
}; };
static struct fsl_usb2_platform_data usb_pdata = { #define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5)
.operating_mode = FSL_USB2_DR_DEVICE, #define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5)
.phy_mode = FSL_USB2_PHY_ULPI,
};
#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
static void marxbot_usbotg_init(void) static void dspics_resets_init(void)
{ {
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG); if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG); gpio_direction_output(TRSLAT_RST_B, 1);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG); gpio_export(TRSLAT_RST_B, false);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG); }
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG); if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG); gpio_direction_output(DSPICS_RST_B, 1);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG); gpio_export(DSPICS_RST_B, false);
mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG); }
mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
gpio_request(OTG_EN_B, "usb-udc-en");
gpio_direction_output(OTG_EN_B, 0);
} }
/* /*
...@@ -152,8 +130,7 @@ void __init mx31moboard_marxbot_init(void) ...@@ -152,8 +130,7 @@ void __init mx31moboard_marxbot_init(void)
mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
"marxbot"); "marxbot");
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); dspics_resets_init();
marxbot_usbotg_init(); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
} }
arch/arm/mach-mx3/mx31moboard.c
View file @ 590a94d9
...@@ -16,9 +16,12 @@ ...@@ -16,9 +16,12 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/ */
#include <linux/delay.h>
#include <linux/fsl_devices.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/leds.h>
#include <linux/memory.h> #include <linux/memory.h>
#include <linux/mtd/physmap.h> #include <linux/mtd/physmap.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
...@@ -36,6 +39,7 @@ ...@@ -36,6 +39,7 @@
#include <mach/iomux-mx3.h> #include <mach/iomux-mx3.h>
#include <mach/i2c.h> #include <mach/i2c.h>
#include <mach/mmc.h> #include <mach/mmc.h>
#include <mach/mx31.h>
#include "devices.h" #include "devices.h"
...@@ -55,6 +59,26 @@ static unsigned int moboard_pins[] = { ...@@ -55,6 +59,26 @@ static unsigned int moboard_pins[] = {
MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
/* USB reset */
MX31_PIN_GPIO1_0__GPIO1_0,
/* USB OTG */
MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
MX31_PIN_USB_OC__GPIO1_30,
/* LEDs */
MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
/* SEL */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
}; };
static struct physmap_flash_data mx31moboard_flash_data = { static struct physmap_flash_data mx31moboard_flash_data = {
...@@ -142,8 +166,109 @@ static struct imxmmc_platform_data sdhc1_pdata = { ...@@ -142,8 +166,109 @@ static struct imxmmc_platform_data sdhc1_pdata = {
.exit = moboard_sdhc1_exit, .exit = moboard_sdhc1_exit,
}; };
/*
* this pin is dedicated for all mx31moboard systems, so we do it here
*/
#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
static void usb_xcvr_reset(void)
{
gpio_request(USB_RESET_B, "usb-reset");
gpio_direction_output(USB_RESET_B, 0);
mdelay(1);
gpio_set_value(USB_RESET_B, 1);
}
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
static void moboard_usbotg_init(void)
{
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
gpio_request(OTG_EN_B, "usb-udc-en");
gpio_direction_output(OTG_EN_B, 0);
}
static struct fsl_usb2_platform_data usb_pdata = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static struct gpio_led mx31moboard_leds[] = {
{
.name = "coreboard-led-0:red:running",
.default_trigger = "heartbeat",
.gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
}, {
.name = "coreboard-led-1:red",
.gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
}, {
.name = "coreboard-led-2:red",
.gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0),
}, {
.name = "coreboard-led-3:red",
.gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
},
};
static struct gpio_led_platform_data mx31moboard_led_pdata = {
.num_leds = ARRAY_SIZE(mx31moboard_leds),
.leds = mx31moboard_leds,
};
static struct platform_device mx31moboard_leds_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &mx31moboard_led_pdata,
},
};
#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
static void mx31moboard_init_sel_gpios(void)
{
if (!gpio_request(SEL0, "sel0")) {
gpio_direction_input(SEL0);
gpio_export(SEL0, true);
}
if (!gpio_request(SEL1, "sel1")) {
gpio_direction_input(SEL1);
gpio_export(SEL1, true);
}
if (!gpio_request(SEL2, "sel2")) {
gpio_direction_input(SEL2);
gpio_export(SEL2, true);
}
if (!gpio_request(SEL3, "sel3")) {
gpio_direction_input(SEL3);
gpio_export(SEL3, true);
}
}
static struct platform_device *devices[] __initdata = { static struct platform_device *devices[] __initdata = {
&mx31moboard_flash, &mx31moboard_flash,
&mx31moboard_leds_device,
}; };
static int mx31moboard_baseboard; static int mx31moboard_baseboard;
...@@ -162,11 +287,18 @@ static void __init mxc_board_init(void) ...@@ -162,11 +287,18 @@ static void __init mxc_board_init(void)
mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_uart_device4, &uart_pdata); mxc_register_device(&mxc_uart_device4, &uart_pdata);
mx31moboard_init_sel_gpios();
mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
usb_xcvr_reset();
moboard_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
switch (mx31moboard_baseboard) { switch (mx31moboard_baseboard) {
case MX31NOBOARD: case MX31NOBOARD:
break; break;
...@@ -197,7 +329,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") ...@@ -197,7 +329,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &mx31moboard_timer, .timer = &mx31moboard_timer,
MACHINE_END MACHINE_END
......
arch/arm/mach-mx3/mx31pdk.c
View file @ 590a94d9
...@@ -265,7 +265,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") ...@@ -265,7 +265,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31pdk_map_io, .map_io = mx31pdk_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &mx31pdk_timer, .timer = &mx31pdk_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx3/mx35pdk.c
View file @ 590a94d9
...@@ -98,7 +98,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK") ...@@ -98,7 +98,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx35_map_io, .map_io = mx35_map_io,
.init_irq = mxc_init_irq, .init_irq = mx35_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &mx35pdk_timer, .timer = &mx35pdk_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx3/pcm037.c
View file @ 590a94d9
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <linux/spi/spi.h> #include <linux/spi/spi.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/fsl_devices.h> #include <linux/fsl_devices.h>
#include <linux/can/platform/sja1000.h>
#include <media/soc_camera.h> #include <media/soc_camera.h>
...@@ -169,6 +170,8 @@ static unsigned int pcm037_pins[] = { ...@@ -169,6 +170,8 @@ static unsigned int pcm037_pins[] = {
MX31_PIN_CSI_MCLK__CSI_MCLK, MX31_PIN_CSI_MCLK__CSI_MCLK,
MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
MX31_PIN_CSI_VSYNC__CSI_VSYNC, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
/* GPIO */
IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
}; };
static struct physmap_flash_data pcm037_flash_data = { static struct physmap_flash_data pcm037_flash_data = {
...@@ -244,12 +247,11 @@ static struct imxuart_platform_data uart_pdata = { ...@@ -244,12 +247,11 @@ static struct imxuart_platform_data uart_pdata = {
}; };
static struct resource smsc911x_resources[] = { static struct resource smsc911x_resources[] = {
[0] = { {
.start = CS1_BASE_ADDR + 0x300, .start = CS1_BASE_ADDR + 0x300,
.end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
...@@ -339,8 +341,7 @@ static struct i2c_board_info pcm037_i2c_devices[] = { ...@@ -339,8 +341,7 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom, .platform_data = &board_eeprom,
}, { }, {
I2C_BOARD_INFO("rtc-pcf8563", 0x51), I2C_BOARD_INFO("pcf8563", 0x51),
.type = "pcf8563",
} }
}; };
...@@ -515,6 +516,33 @@ static struct mx3fb_platform_data mx3fb_pdata = { ...@@ -515,6 +516,33 @@ static struct mx3fb_platform_data mx3fb_pdata = {
.num_modes = ARRAY_SIZE(fb_modedb), .num_modes = ARRAY_SIZE(fb_modedb),
}; };
static struct resource pcm970_sja1000_resources[] = {
{
.start = CS5_BASE_ADDR,
.end = CS5_BASE_ADDR + 0x100 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
.end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
};
struct sja1000_platform_data pcm970_sja1000_platform_data = {
.clock = 16000000 / 2,
.ocr = 0x40 | 0x18,
.cdr = 0x40,
};
static struct platform_device pcm970_sja1000 = {
.name = "sja1000_platform",
.dev = {
.platform_data = &pcm970_sja1000_platform_data,
},
.resource = pcm970_sja1000_resources,
.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
};
/* /*
* Board specific initialization. * Board specific initialization.
*/ */
...@@ -575,6 +603,8 @@ static void __init mxc_board_init(void) ...@@ -575,6 +603,8 @@ static void __init mxc_board_init(void)
if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
mxc_register_device(&mx3_camera, &camera_pdata); mxc_register_device(&mx3_camera, &camera_pdata);
platform_device_register(&pcm970_sja1000);
} }
static void __init pcm037_timer_init(void) static void __init pcm037_timer_init(void)
...@@ -592,7 +622,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") ...@@ -592,7 +622,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &pcm037_timer, .timer = &pcm037_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mx3/pcm043.c
View file @ 590a94d9
...@@ -133,8 +133,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = { ...@@ -133,8 +133,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom, .platform_data = &board_eeprom,
}, { }, {
I2C_BOARD_INFO("rtc-pcf8563", 0x51), I2C_BOARD_INFO("pcf8563", 0x51),
.type = "pcf8563",
} }
}; };
#endif #endif
...@@ -203,7 +202,8 @@ static struct pad_desc pcm043_pads[] = { ...@@ -203,7 +202,8 @@ static struct pad_desc pcm043_pads[] = {
MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
MX35_PAD_D3_REV__IPU_DISPB_D3_REV, MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL /* gpio */
MX35_PAD_ATA_CS0__GPIO2_6,
}; };
/* /*
...@@ -245,7 +245,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043") ...@@ -245,7 +245,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx35_map_io, .map_io = mx35_map_io,
.init_irq = mxc_init_irq, .init_irq = mx35_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &pcm043_timer, .timer = &pcm043_timer,
MACHINE_END MACHINE_END
......
arch/arm/mach-mx3/qong.c
View file @ 590a94d9
...@@ -81,13 +81,12 @@ static inline void mxc_init_imx_uart(void) ...@@ -81,13 +81,12 @@ static inline void mxc_init_imx_uart(void)
} }
static struct resource dnet_resources[] = { static struct resource dnet_resources[] = {
[0] = { {
.name = "dnet-memory", .name = "dnet-memory",
.start = QONG_DNET_BASEADDR, .start = QONG_DNET_BASEADDR,
.end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1, .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, }, {
[1] = {
.start = QONG_FPGA_IRQ, .start = QONG_FPGA_IRQ,
.end = QONG_FPGA_IRQ, .end = QONG_FPGA_IRQ,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
...@@ -280,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") ...@@ -280,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100, .boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31_map_io, .map_io = mx31_map_io,
.init_irq = mxc_init_irq, .init_irq = mx31_init_irq,
.init_machine = mxc_board_init, .init_machine = mxc_board_init,
.timer = &qong_timer, .timer = &qong_timer,
MACHINE_END MACHINE_END
arch/arm/mach-mxc91231/Kconfig 0 → 100644
View file @ 590a94d9
if ARCH_MXC91231
comment "MXC91231 platforms:"
config MACH_MAGX_ZN5
bool "Support Motorola Zn5 GSM phone"
default n
help
Include support for Motorola Zn5 GSM phone.
endif
arch/arm/mach-mxc91231/Makefile 0 → 100644
View file @ 590a94d9
obj-y := mm.o clock.o devices.o system.o iomux.o
obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
arch/arm/mach-mxc91231/Makefile.boot 0 → 100644
View file @ 590a94d9
zreladdr-y := 0x90008000
params_phys-y := 0x90000100
initrd_phys-y := 0x90800000
arch/arm/mach-mxc91231/clock.c 0 → 100644
View file @ 590a94d9
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/clkdev.h>
#include <asm/bug.h>
#include <asm/div64.h>
#include "crm_regs.h"
#define CRM_SMALL_DIVIDER(base, name) \
crm_small_divider(base, \
base ## _ ## name ## _OFFSET, \
base ## _ ## name ## _MASK)
#define CRM_1DIVIDER(base, name) \
crm_divider(base, \
base ## _ ## name ## _OFFSET, \
base ## _ ## name ## _MASK, 1)
#define CRM_16DIVIDER(base, name) \
crm_divider(base, \
base ## _ ## name ## _OFFSET, \
base ## _ ## name ## _MASK, 16)
static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
{
static const u32 crm_small_dividers[] = {
2, 3, 4, 5, 6, 8, 10, 12
};
u8 idx;
idx = (__raw_readl(reg) & mask) >> offset;
if (idx > 7)
return 1;
return crm_small_dividers[idx];
}
static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
{
u32 div;
div = (__raw_readl(reg) & mask) >> offset;
return div ? div : z;
}
static int _clk_1bit_enable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= 1 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void _clk_1bit_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(1 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
static int _clk_3bit_enable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= 0x7 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void _clk_3bit_disable(struct clk *clk)
{
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(0x7 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
static unsigned long ckih_rate;
static unsigned long clk_ckih_get_rate(struct clk *clk)
{
return ckih_rate;
}
static struct clk ckih_clk = {
.get_rate = clk_ckih_get_rate,
};
static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
{
return 2 * clk_get_rate(clk->parent);
}
static struct clk ckih_x2_clk = {
.parent = &ckih_clk,
.get_rate = clk_ckih_x2_get_rate,
};
static unsigned long clk_ckil_get_rate(struct clk *clk)
{
return CKIL_CLK_FREQ;
}
static struct clk ckil_clk = {
.get_rate = clk_ckil_get_rate,
};
/* plls stuff */
static struct clk mcu_pll_clk;
static struct clk dsp_pll_clk;
static struct clk usb_pll_clk;
static struct clk *pll_clk(u8 sel)
{
switch (sel) {
case 0:
return &mcu_pll_clk;
case 1:
return &dsp_pll_clk;
case 2:
return &usb_pll_clk;
}
BUG();
}
static void __iomem *pll_base(struct clk *clk)
{
if (clk == &mcu_pll_clk)
return MXC_PLL0_BASE;
else if (clk == &dsp_pll_clk)
return MXC_PLL1_BASE;
else if (clk == &usb_pll_clk)
return MXC_PLL2_BASE;
BUG();
}
static unsigned long clk_pll_get_rate(struct clk *clk)
{
const void __iomem *pllbase;
unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
long mfn, mfn_abs, mfd, pdf;
s64 temp;
pllbase = pll_base(clk);
pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
if (pll_hfsm == 0) {
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
} else {
dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
}
pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
mfi = (mfi <= 5) ? 5 : mfi;
mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
if (mfn < 0)
mfn_abs = -mfn;
else
mfn_abs = mfn;
/* XXX: actually this asumes that ckih is fed to pll, but spec says
* that ckih_x2 is also possible. need to check this out.
*/
ref_clk = clk_get_rate(&ckih_clk);
ref_clk *= 2;
ref_clk /= pdf + 1;
temp = (u64) ref_clk * mfn_abs;
do_div(temp, mfd);
if (mfn < 0)
temp = -temp;
temp += ref_clk * mfi;
return temp;
}
static int clk_pll_enable(struct clk *clk)
{
void __iomem *ctl;
u32 reg;
ctl = pll_base(clk);
reg = __raw_readl(ctl);
reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
__raw_writel(reg, ctl);
do {
reg = __raw_readl(ctl);
} while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
return 0;
}
static void clk_pll_disable(struct clk *clk)
{
void __iomem *ctl;
u32 reg;
ctl = pll_base(clk);
reg = __raw_readl(ctl);
reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
__raw_writel(reg, ctl);
}
static struct clk mcu_pll_clk = {
.parent = &ckih_clk,
.get_rate = clk_pll_get_rate,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
};
static struct clk dsp_pll_clk = {
.parent = &ckih_clk,
.get_rate = clk_pll_get_rate,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
};
static struct clk usb_pll_clk = {
.parent = &ckih_clk,
.get_rate = clk_pll_get_rate,
.enable = clk_pll_enable,
.disable = clk_pll_disable,
};
/* plls stuff end */
/* ap_ref_clk stuff */
static struct clk ap_ref_clk;
static unsigned long clk_ap_ref_get_rate(struct clk *clk)
{
u32 ascsr, acsr;
u8 ap_pat_ref_div_2, ap_isel, acs, ads;
ascsr = __raw_readl(MXC_CRMAP_ASCSR);
acsr = __raw_readl(MXC_CRMAP_ACSR);
/* 0 for ckih, 1 for ckih*2 */
ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
/* reg divider */
ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
/* undocumented, 1 for disabling divider */
ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
/* 0 for pat_ref, 1 for divider out */
acs = acsr & MXC_CRMAP_ACSR_ACS;
if (acs & !ads)
/* use divided clock */
return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
}
static struct clk ap_ref_clk = {
.parent = &ckih_clk,
.get_rate = clk_ap_ref_get_rate,
};
/* ap_ref_clk stuff end */
/* ap_pre_dfs_clk stuff */
static struct clk ap_pre_dfs_clk;
static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
{
u32 acsr, ascsr;
acsr = __raw_readl(MXC_CRMAP_ACSR);
ascsr = __raw_readl(MXC_CRMAP_ASCSR);
if (acsr & MXC_CRMAP_ACSR_ACS) {
u8 sel;
sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
MXC_CRMAP_ASCSR_APSEL_OFFSET;
return clk_get_rate(pll_clk(sel)) /
CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
}
return clk_get_rate(&ap_ref_clk);
}
static struct clk ap_pre_dfs_clk = {
.get_rate = clk_ap_pre_dfs_get_rate,
};
/* ap_pre_dfs_clk stuff end */
/* usb_clk stuff */
static struct clk usb_clk;
static struct clk *clk_usb_parent(struct clk *clk)
{
u32 acsr, ascsr;
acsr = __raw_readl(MXC_CRMAP_ACSR);
ascsr = __raw_readl(MXC_CRMAP_ASCSR);
if (acsr & MXC_CRMAP_ACSR_ACS) {
u8 sel;
sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
MXC_CRMAP_ASCSR_USBSEL_OFFSET;
return pll_clk(sel);
}
return &ap_ref_clk;
}
static unsigned long clk_usb_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) /
CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
}
static struct clk usb_clk = {
.enable_reg = MXC_CRMAP_ACDER2,
.enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
.get_rate = clk_usb_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
};
/* usb_clk stuff end */
static unsigned long clk_ipg_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
}
static unsigned long clk_ahb_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) /
CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
}
static struct clk ipg_clk = {
.parent = &ap_pre_dfs_clk,
.get_rate = clk_ipg_get_rate,
};
static struct clk ahb_clk = {
.parent = &ap_pre_dfs_clk,
.get_rate = clk_ahb_get_rate,
};
/* perclk_clk stuff */
static struct clk perclk_clk;
static unsigned long clk_perclk_get_rate(struct clk *clk)
{
u32 acder2;
acder2 = __raw_readl(MXC_CRMAP_ACDER2);
if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
return 2 * clk_get_rate(clk->parent);
return clk_get_rate(clk->parent);
}
static struct clk perclk_clk = {
.parent = &ckih_clk,
.get_rate = clk_perclk_get_rate,
};
/* perclk_clk stuff end */
/* uart_clk stuff */
static struct clk uart_clk[];
static unsigned long clk_uart_get_rate(struct clk *clk)
{
u32 div;
switch (clk->id) {
case 0:
case 1:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
break;
case 2:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
break;
default:
BUG();
}
return clk_get_rate(clk->parent) / div;
}
static struct clk uart_clk[] = {
{
.id = 0,
.parent = &perclk_clk,
.enable_reg = MXC_CRMAP_APRA,
.enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
.get_rate = clk_uart_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
}, {
.id = 1,
.parent = &perclk_clk,
.enable_reg = MXC_CRMAP_APRA,
.enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
.get_rate = clk_uart_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
}, {
.id = 2,
.parent = &perclk_clk,
.enable_reg = MXC_CRMAP_APRA,
.enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
.get_rate = clk_uart_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
},
};
/* uart_clk stuff end */
/* sdhc_clk stuff */
static struct clk nfc_clk;
static unsigned long clk_nfc_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) /
CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
}
static struct clk nfc_clk = {
.parent = &ahb_clk,
.enable_reg = MXC_CRMAP_ACDER2,
.enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
.get_rate = clk_nfc_get_rate,
.enable = _clk_1bit_enable,
.disable = _clk_1bit_disable,
};
/* sdhc_clk stuff end */
/* sdhc_clk stuff */
static struct clk sdhc_clk[];
static struct clk *clk_sdhc_parent(struct clk *clk)
{
u32 aprb;
u8 sel;
u32 mask;
int offset;
aprb = __raw_readl(MXC_CRMAP_APRB);
switch (clk->id) {
case 0:
mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
break;
case 1:
mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
break;
default:
BUG();
}
sel = (aprb & mask) >> offset;
switch (sel) {
case 0:
return &ckih_clk;
case 1:
return &ckih_x2_clk;
}
return &usb_clk;
}
static unsigned long clk_sdhc_get_rate(struct clk *clk)
{
u32 div;
switch (clk->id) {
case 0:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
break;
case 1:
div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
break;
default:
BUG();
}
return clk_get_rate(clk->parent) / div;
}
static int clk_sdhc_enable(struct clk *clk)
{
u32 amlpmre1, aprb;
amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
aprb = __raw_readl(MXC_CRMAP_APRB);
switch (clk->id) {
case 0:
amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
break;
case 1:
amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
break;
}
__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
__raw_writel(aprb, MXC_CRMAP_APRB);
return 0;
}
static void clk_sdhc_disable(struct clk *clk)
{
u32 amlpmre1, aprb;
amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
aprb = __raw_readl(MXC_CRMAP_APRB);
switch (clk->id) {
case 0:
amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
break;
case 1:
amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
break;
}
__raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
__raw_writel(aprb, MXC_CRMAP_APRB);
}
static struct clk sdhc_clk[] = {
{
.id = 0,
.get_rate = clk_sdhc_get_rate,
.enable = clk_sdhc_enable,
.disable = clk_sdhc_disable,
}, {
.id = 1,
.get_rate = clk_sdhc_get_rate,
.enable = clk_sdhc_enable,
.disable = clk_sdhc_disable,
},
};
/* sdhc_clk stuff end */
/* wdog_clk stuff */
static struct clk wdog_clk[] = {
{
.id = 0,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRD,
.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
}, {
.id = 1,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRD,
.enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
},
};
/* wdog_clk stuff end */
/* gpt_clk stuff */
static struct clk gpt_clk = {
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRC,
.enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
};
/* gpt_clk stuff end */
/* cspi_clk stuff */
static struct clk cspi_clk[] = {
{
.id = 0,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRE2,
.enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
}, {
.id = 1,
.parent = &ipg_clk,
.enable_reg = MXC_CRMAP_AMLPMRE1,
.enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
.enable = _clk_3bit_enable,
.disable = _clk_3bit_disable,
},
};
/* cspi_clk stuff end */
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
.con_id = n, \
.clk = &c, \
},
static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
_REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
_REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
_REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
};
int __init mxc91231_clocks_init(unsigned long fref)
{
void __iomem *gpt_base;
int i;
ckih_rate = fref;
usb_clk.parent = clk_usb_parent(&usb_clk);
sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
for (i = 0; i < ARRAY_SIZE(lookups); i++)
clkdev_add(&lookups[i]);
gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
return 0;
}
arch/arm/mach-mxc91231/crm_regs.h 0 → 100644
View file @ 590a94d9
/*
* Copyright 2006 Freescale Semiconductor, Inc.
* Copyright 2006-2007 Motorola, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
#define CKIL_CLK_FREQ 32768
#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
#define MXC_PLL_DP_CONFIG 0x04
#define MXC_PLL_DP_OP 0x08
#define MXC_PLL_DP_MFD 0x0C
#define MXC_PLL_DP_MFN 0x10
#define MXC_PLL_DP_HFS_OP 0x1C
#define MXC_PLL_DP_HFS_MFD 0x20
#define MXC_PLL_DP_HFS_MFN 0x24
/* PLL Register Bit definitions */
#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
#define MXC_PLL_DP_CTL_ADE 0x800
#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
#define MXC_PLL_DP_CTL_HFSM 0x80
#define MXC_PLL_DP_CTL_PRE 0x40
#define MXC_PLL_DP_CTL_UPEN 0x20
#define MXC_PLL_DP_CTL_RST 0x10
#define MXC_PLL_DP_CTL_RCP 0x8
#define MXC_PLL_DP_CTL_PLM 0x4
#define MXC_PLL_DP_CTL_BRM0 0x2
#define MXC_PLL_DP_CTL_LRF 0x1
#define MXC_PLL_DP_OP_MFI_OFFSET 4
#define MXC_PLL_DP_OP_MFI_MASK 0xF
#define MXC_PLL_DP_OP_PDF_OFFSET 0
#define MXC_PLL_DP_OP_PDF_MASK 0xF
#define MXC_PLL_DP_MFD_OFFSET 0
#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
#define MXC_PLL_DP_MFN_OFFSET 0
#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
/* CRM AP Register Offsets */
#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
/* CRM AP Register Bit definitions */
#define MXC_CRMAP_ASCSR_CRS 0x10000
#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
#define MXC_CRMAP_ASCSR_APISEL 0x1
#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
#define MXC_CRMAP_ACSR_ADS_OFFSET 8
#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
#define MXC_CRMAP_ACSR_ACS 0x1
#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
#define MXC_CRMAP_ADCR_ALT_PLL 0x80
#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
#define MXC_CRMAP_ADCR_DIV_BYP 0x2
#define MXC_CRMAP_ADCR_VSTAT 0x8
#define MXC_CRMAP_ADCR_TSTAT 0x10
#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
#define MXC_CRMAP_ADCR_CLK_ON 0x40
#define MXC_CRMAP_ADFMR_FC_OFFSET 16
#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
#define MXC_CRMAP_ADFMR_MF_OFFSET 1
#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
#define MXC_CRMAP_ACR_CKOHD (1 << 11)
#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
#define MXC_CRMAP_ACR_CKOD (1 << 7)
#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
/* AP Warm reset */
#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
#define NUM_GATE_CTRL 6
/* CRM COM Register Offsets */
#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
/* CRM COM Bit Definitions */
#define MXC_CRMCOM_CSCR_PPD1 0x08000000
#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
/* DSM Register Offsets */
#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
/* Bit definitions of various registers in DSM */
#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001
#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003
#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200
#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001
#define MXC_DSM_CONTROL0_RESTART 0x00000010
/* Counter Block reset */
#define MXC_DSM_CONTROL1_CB_RST 0x00000002
/* State Machine reset */
#define MXC_DSM_CONTROL1_SM_RST 0x00000004
/* Bit needed to reset counter block */
#define MXC_CONTROL1_RST_CNT32 0x00000008
#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800
#define MXC_DSM_CONTROL1_SLEEP 0x00000100
#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000
#define MXC_DSM_CTREN_CNT32 0x00000001
/* Magic Fix enable bit */
#define MXC_DSM_MGPER_EN_MGFX 0x80000000
#define MXC_DSM_MGPER_PER_MASK 0x000003FF
#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n)
/* Address offsets of the CLKCTL registers */
#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00)
#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04)
#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08)
#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
arch/arm/mach-mxc91231/devices.c 0 → 100644
View file @ 590a94d9
/*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/imx-uart.h>
static struct resource uart0[] = {
{
.start = MXC91231_UART1_BASE_ADDR,
.end = MXC91231_UART1_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_UART1_RX,
.end = MXC91231_INT_UART1_RX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART1_TX,
.end = MXC91231_INT_UART1_TX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART1_MINT,
.end = MXC91231_INT_UART1_MINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device0 = {
.name = "imx-uart",
.id = 0,
.resource = uart0,
.num_resources = ARRAY_SIZE(uart0),
};
static struct resource uart1[] = {
{
.start = MXC91231_UART2_BASE_ADDR,
.end = MXC91231_UART2_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_UART2_RX,
.end = MXC91231_INT_UART2_RX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART2_TX,
.end = MXC91231_INT_UART2_TX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART2_MINT,
.end = MXC91231_INT_UART2_MINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device1 = {
.name = "imx-uart",
.id = 1,
.resource = uart1,
.num_resources = ARRAY_SIZE(uart1),
};
static struct resource uart2[] = {
{
.start = MXC91231_UART3_BASE_ADDR,
.end = MXC91231_UART3_BASE_ADDR + 0x0B5,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_UART3_RX,
.end = MXC91231_INT_UART3_RX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART3_TX,
.end = MXC91231_INT_UART3_TX,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC91231_INT_UART3_MINT,
.end = MXC91231_INT_UART3_MINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_uart_device2 = {
.name = "imx-uart",
.id = 2,
.resource = uart2,
.num_resources = ARRAY_SIZE(uart2),
};
/* GPIO port description */
static struct mxc_gpio_port mxc_gpio_ports[] = {
[0] = {
.chip.label = "gpio-0",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
.irq = MXC91231_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_IRQ_START,
},
[1] = {
.chip.label = "gpio-1",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
.irq = MXC91231_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
},
[2] = {
.chip.label = "gpio-2",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
.irq = MXC91231_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
},
[3] = {
.chip.label = "gpio-3",
.base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
.irq = MXC91231_INT_GPIO4,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
},
};
int __init mxc_register_gpios(void)
{
return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
}
static struct resource mxc_nand_resources[] = {
{
.start = MXC91231_NFC_BASE_ADDR,
.end = MXC91231_NFC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM
}, {
.start = MXC91231_INT_NANDFC,
.end = MXC91231_INT_NANDFC,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mxc_nand_device = {
.name = "mxc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_nand_resources),
.resource = mxc_nand_resources,
};
static struct resource mxc_sdhc0_resources[] = {
{
.start = MXC91231_MMC_SDHC1_BASE_ADDR,
.end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_MMC_SDHC1,
.end = MXC91231_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxc_sdhc1_resources[] = {
{
.start = MXC91231_MMC_SDHC2_BASE_ADDR,
.end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_MMC_SDHC2,
.end = MXC91231_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_sdhc_device0 = {
.name = "mxc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
.resource = mxc_sdhc0_resources,
};
struct platform_device mxc_sdhc_device1 = {
.name = "mxc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
.resource = mxc_sdhc1_resources,
};
static struct resource mxc_cspi0_resources[] = {
{
.start = MXC91231_CSPI1_BASE_ADDR,
.end = MXC91231_CSPI1_BASE_ADDR + 0x20,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_CSPI1,
.end = MXC91231_INT_CSPI1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_cspi_device0 = {
.name = "spi_imx",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_cspi0_resources),
.resource = mxc_cspi0_resources,
};
static struct resource mxc_cspi1_resources[] = {
{
.start = MXC91231_CSPI2_BASE_ADDR,
.end = MXC91231_CSPI2_BASE_ADDR + 0x20,
.flags = IORESOURCE_MEM,
}, {
.start = MXC91231_INT_CSPI2,
.end = MXC91231_INT_CSPI2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_cspi_device1 = {
.name = "spi_imx",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_cspi1_resources),
.resource = mxc_cspi1_resources,
};
static struct resource mxc_wdog0_resources[] = {
{
.start = MXC91231_WDOG1_BASE_ADDR,
.end = MXC91231_WDOG1_BASE_ADDR + 0x10,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdog_device0 = {
.name = "mxc-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdog0_resources),
.resource = mxc_wdog0_resources,
};
arch/arm/mach-mxc91231/devices.h 0 → 100644
View file @ 590a94d9
extern struct platform_device mxc_uart_device0;
extern struct platform_device mxc_uart_device1;
extern struct platform_device mxc_uart_device2;
extern struct platform_device mxc_nand_device;
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_cspi_device0;
extern struct platform_device mxc_cspi_device1;
extern struct platform_device mxc_wdog_device0;
arch/arm/mach-mxc91231/iomux.c 0 → 100644
View file @ 590a94d9
/*
* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/iomux-mxc91231.h>
/*
* IOMUX register (base) addresses
*/
#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
static DEFINE_SPINLOCK(gpio_mux_lock);
#define NB_PORTS ((PIN_MAX + 32) / 32)
#define PIN_GLOBAL_NUM(pin) \
(((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
/*
* set the mode for a IOMUX pin.
*/
int mxc_iomux_mode(const unsigned int pin_mode)
{
u32 side, field, l, mode, ret = 0;
void __iomem *reg;
side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
switch (side) {
case MUX_SIDE_AP:
reg = IOMUXSW_AP_MUX_CTL;
break;
case MUX_SIDE_SP:
reg = IOMUXSW_SP_MUX_CTL;
break;
default:
return -EINVAL;
}
reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0xff << (field * 8));
l |= mode << (field * 8);
__raw_writel(l, reg);
spin_unlock(&gpio_mux_lock);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_mode);
/*
* This function configures the pad value for a IOMUX pin.
*/
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
{
u32 padgrp, field, l;
void __iomem *reg;
padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x, field = %d\n",
__func__, (pin + 2) / 3, field);
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
__raw_writel(l, reg);
spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_pad);
/*
* allocs a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
*/
int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
{
unsigned pad = PIN_GLOBAL_NUM(pin_mode);
if (pad >= (PIN_MAX + 1)) {
printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
pad, label ? label : "?");
return -EINVAL;
}
if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
pad, label ? label : "?");
return -EBUSY;
}
mxc_iomux_mode(pin_mode);
return 0;
}
EXPORT_SYMBOL(mxc_iomux_alloc_pin);
int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
const char *label)
{
unsigned int *p = pin_list;
int i;
int ret = -EINVAL;
for (i = 0; i < count; i++) {
ret = mxc_iomux_alloc_pin(*p, label);
if (ret)
goto setup_error;
p++;
}
return 0;
setup_error:
mxc_iomux_release_multiple_pins(pin_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
void mxc_iomux_release_pin(const unsigned int pin_mode)
{
unsigned pad = PIN_GLOBAL_NUM(pin_mode);
if (pad < (PIN_MAX + 1))
clear_bit(pad, mxc_pin_alloc_map);
}
EXPORT_SYMBOL(mxc_iomux_release_pin);
void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
{
unsigned int *p = pin_list;
int i;
for (i = 0; i < count; i++) {
mxc_iomux_release_pin(*p);
p++;
}
}
EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
arch/arm/mach-mxc91231/magx-zn5.c 0 → 100644
View file @ 590a94d9
/*
* Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
*
* This file is released under the GPLv2 or later.
*/
#include <linux/irq.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mxc91231.h>
#include <mach/mmc.h>
#include <mach/imx-uart.h>
#include "devices.h"
static struct imxuart_platform_data uart_pdata = {
};
static struct imxmmc_platform_data sdhc_pdata = {
};
static void __init zn5_init(void)
{
pm_power_off = mxc91231_power_off;
mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
mxc_register_device(&mxc_uart_device1, &uart_pdata);
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
mxc_register_device(&mxc_wdog_device0, NULL);
return;
}
static void __init zn5_timer_init(void)
{
mxc91231_clocks_init(26000000); /* 26mhz ckih */
}
struct sys_timer zn5_timer = {
.init = zn5_timer_init,
};
MACHINE_START(MAGX_ZN5, "Motorola Zn5")
.phys_io = MXC91231_AIPS1_BASE_ADDR,
.io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mxc91231_map_io,
.init_irq = mxc91231_init_irq,
.timer = &zn5_timer,
.init_machine = zn5_init,
MACHINE_END
arch/arm/mach-mxc91231/mm.c 0 → 100644
View file @ 590a94d9
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MXC specific definitions
* Copyright 2006 Motorola, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
/*
* This structure defines the MXC memory map.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MXC91231_L2CC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
.length = MXC91231_L2CC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
.length = MXC91231_X_MEMC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_ROMP_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
.length = MXC91231_ROMP_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
.length = MXC91231_AVIC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
.length = MXC91231_AIPS1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
.length = MXC91231_SPBA0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_SPBA1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
.length = MXC91231_SPBA1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
.length = MXC91231_AIPS2_SIZE,
.type = MT_DEVICE,
},
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory map for
* the IO modules.
*/
void __init mxc91231_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MXC91231);
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
void __init mxc91231_init_irq(void)
{
mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
}
arch/arm/mach-mxc91231/system.c 0 → 100644
View file @ 590a94d9
/*
* Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
*
* This file is released under the GPLv2 or later.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/proc-fns.h>
#include <mach/hardware.h>
#include "crm_regs.h"
#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
#define WDOG_WCR_OUT_ENABLE (1 << 6)
#define WDOG_WCR_ASSERT (1 << 5)
void mxc91231_power_off(void)
{
u16 wcr;
wcr = __raw_readw(WDOG_WCR);
wcr |= WDOG_WCR_OUT_ENABLE;
wcr &= ~WDOG_WCR_ASSERT;
__raw_writew(wcr, WDOG_WCR);
}
void mxc91231_arch_reset(char mode, const char *cmd)
{
u32 amcr;
/* Reset the AP using CRM */
amcr = __raw_readl(MXC_CRMAP_AMCR);
amcr &= ~MXC_CRMAP_AMCR_SW_AP;
__raw_writel(amcr, MXC_CRMAP_AMCR);
mdelay(10);
cpu_reset(0);
}
void mxc91231_prepare_idle(void)
{
u32 crm_ctl;
/* Go to WAIT mode after WFI */
crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
__raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
}
arch/arm/plat-mxc/Kconfig
View file @ 590a94d9
...@@ -9,6 +9,7 @@ choice ...@@ -9,6 +9,7 @@ choice
config ARCH_MX1 config ARCH_MX1
bool "MX1-based" bool "MX1-based"
select CPU_ARM920T select CPU_ARM920T
select COMMON_CLKDEV
help help
This enables support for systems based on the Freescale i.MX1 family This enables support for systems based on the Freescale i.MX1 family
...@@ -19,6 +20,13 @@ config ARCH_MX2 ...@@ -19,6 +20,13 @@ config ARCH_MX2
help help
This enables support for systems based on the Freescale i.MX2 family This enables support for systems based on the Freescale i.MX2 family
config ARCH_MX25
bool "MX25-based"
select CPU_ARM926T
select COMMON_CLKDEV
help
This enables support for systems based on the Freescale i.MX25 family
config ARCH_MX3 config ARCH_MX3
bool "MX3-based" bool "MX3-based"
select CPU_V6 select CPU_V6
...@@ -26,11 +34,20 @@ config ARCH_MX3 ...@@ -26,11 +34,20 @@ config ARCH_MX3
help help
This enables support for systems based on the Freescale i.MX3 family This enables support for systems based on the Freescale i.MX3 family
config ARCH_MXC91231
bool "MXC91231-based"
select CPU_V6
select COMMON_CLKDEV
help
This enables support for systems based on the Freescale MXC91231 family
endchoice endchoice
source "arch/arm/mach-mx1/Kconfig" source "arch/arm/mach-mx1/Kconfig"
source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx2/Kconfig"
source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx3/Kconfig"
source "arch/arm/mach-mx25/Kconfig"
source "arch/arm/mach-mxc91231/Kconfig"
endmenu endmenu
......
arch/arm/plat-mxc/clock.c
View file @ 590a94d9
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
#include <linux/string.h> #include <linux/string.h>
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/hardware.h>
static LIST_HEAD(clocks); static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex); static DEFINE_MUTEX(clocks_mutex);
...@@ -47,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex); ...@@ -47,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex);
* Standard clock functions defined in include/linux/clk.h * Standard clock functions defined in include/linux/clk.h
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
/*
* All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
* MXC architectures have switched to using clkdev.
*/
#ifndef CONFIG_COMMON_CLKDEV
/*
* Retrieve a clock by name.
*
* Note that we first try to use device id on the bus
* and clock name. If this fails, we try to use "<name>.<id>". If this fails,
* we try to use clock name only.
* The reference count to the clock's module owner ref count is incremented.
*/
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p, *clk = ERR_PTR(-ENOENT);
int idno;
const char *str;
if (id == NULL)
return clk;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
mutex_lock(&clocks_mutex);
list_for_each_entry(p, &clocks, node) {
if (p->id == idno &&
strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p;
goto found;
}
}
str = strrchr(id, '.');
if (str) {
int cnt = str - id;
str++;
idno = simple_strtol(str, NULL, 10);
list_for_each_entry(p, &clocks, node) {
if (p->id == idno &&
strlen(p->name) == cnt &&
strncmp(id, p->name, cnt) == 0 &&
try_module_get(p->owner)) {
clk = p;
goto found;
}
}
}
list_for_each_entry(p, &clocks, node) {
if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p;
goto found;
}
}
printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
found:
mutex_unlock(&clocks_mutex);
return clk;
}
EXPORT_SYMBOL(clk_get);
#endif
static void __clk_disable(struct clk *clk) static void __clk_disable(struct clk *clk)
{ {
if (clk == NULL || IS_ERR(clk)) if (clk == NULL || IS_ERR(clk))
...@@ -193,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk) ...@@ -193,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk)
} }
EXPORT_SYMBOL(clk_get_rate); EXPORT_SYMBOL(clk_get_rate);
#ifndef CONFIG_COMMON_CLKDEV
/* Decrement the clock's module reference count */
void clk_put(struct clk *clk)
{
if (clk && !IS_ERR(clk))
module_put(clk->owner);
}
EXPORT_SYMBOL(clk_put);
#endif
/* Round the requested clock rate to the nearest supported /* Round the requested clock rate to the nearest supported
* rate that is less than or equal to the requested rate. * rate that is less than or equal to the requested rate.
* This is dependent on the clock's current parent. * This is dependent on the clock's current parent.
...@@ -265,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk) ...@@ -265,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk)
} }
EXPORT_SYMBOL(clk_get_parent); EXPORT_SYMBOL(clk_get_parent);
#ifndef CONFIG_COMMON_CLKDEV
/*
* Add a new clock to the clock tree.
*/
int clk_register(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
mutex_lock(&clocks_mutex);
list_add(&clk->node, &clocks);
mutex_unlock(&clocks_mutex);
return 0;
}
EXPORT_SYMBOL(clk_register);
/* Remove a clock from the clock tree */
void clk_unregister(struct clk *clk)
{
if (clk == NULL || IS_ERR(clk))
return;
mutex_lock(&clocks_mutex);
list_del(&clk->node);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_unregister);
#ifdef CONFIG_PROC_FS
static int mxc_clock_read_proc(char *page, char **start, off_t off,
int count, int *eof, void *data)
{
struct clk *clkp;
char *p = page;
int len;
list_for_each_entry(clkp, &clocks, node) {
p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
clk_get_rate(clkp), clkp->usecount);
if (clkp->parent)
p += sprintf(p, ", %s-%d\n", clkp->parent->name,
clkp->parent->id);
else
p += sprintf(p, "\n");
}
len = (p - page) - off;
if (len < 0)
len = 0;
*eof = (len <= count) ? 1 : 0;
*start = page + off;
return len;
}
static int __init mxc_setup_proc_entry(void)
{
struct proc_dir_entry *res;
res = create_proc_read_entry("cpu/clocks", 0, NULL,
mxc_clock_read_proc, NULL);
if (!res) {
printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
return -ENOMEM;
}
return 0;
}
late_initcall(mxc_setup_proc_entry);
#endif /* CONFIG_PROC_FS */
#endif
/* /*
* Get the resulting clock rate from a PLL register value and the input * Get the resulting clock rate from a PLL register value and the input
* frequency. PLLs with this register layout can at least be found on * frequency. PLLs with this register layout can at least be found on
...@@ -363,12 +210,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) ...@@ -363,12 +210,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
mfn_abs = mfn; mfn_abs = mfn;
#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21 /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
if (mfn >= 0x200) { * 2's complements number
mfn |= 0xFFFFFE00; */
mfn_abs = -mfn; if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
} mfn_abs = 0x400 - mfn;
#endif
freq *= 2; freq *= 2;
freq /= pd + 1; freq /= pd + 1;
...@@ -376,8 +222,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) ...@@ -376,8 +222,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
ll = (unsigned long long)freq * mfn_abs; ll = (unsigned long long)freq * mfn_abs;
do_div(ll, mfd + 1); do_div(ll, mfd + 1);
if (mfn < 0)
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
ll = -ll; ll = -ll;
ll = (freq * mfi) + ll; ll = (freq * mfi) + ll;
return ll; return ll;
......
arch/arm/plat-mxc/gpio.c
View file @ 590a94d9
...@@ -29,6 +29,23 @@ ...@@ -29,6 +29,23 @@
static struct mxc_gpio_port *mxc_gpio_ports; static struct mxc_gpio_port *mxc_gpio_ports;
static int gpio_table_size; static int gpio_table_size;
#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
#define GPIO_INT_NONE 0x4
/* Note: This driver assumes 32 GPIOs are handled in one register */ /* Note: This driver assumes 32 GPIOs are handled in one register */
static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index) static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
...@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) ...@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
} }
} }
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
/* MX1 and MX3 has one interrupt *per* gpio port */ /* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{ {
...@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) ...@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
mxc_gpio_irq_handler(port, irq_stat); mxc_gpio_irq_handler(port, irq_stat);
} }
#endif
#ifdef CONFIG_ARCH_MX2
/* MX2 has one interrupt *for all* gpio ports */ /* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{ {
...@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) ...@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
mxc_gpio_irq_handler(&port[i], irq_stat); mxc_gpio_irq_handler(&port[i], irq_stat);
} }
} }
#endif
static struct irq_chip gpio_irq_chip = { static struct irq_chip gpio_irq_chip = {
.ack = gpio_ack_irq, .ack = gpio_ack_irq,
...@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) ...@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
/* its a serious configuration bug when it fails */ /* its a serious configuration bug when it fails */
BUG_ON( gpiochip_add(&port[i].chip) < 0 ); BUG_ON( gpiochip_add(&port[i].chip) < 0 );
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1) if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
/* setup one handler for each entry */ /* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]); set_irq_data(port[i].irq, &port[i]);
#endif }
} }
#ifdef CONFIG_ARCH_MX2 if (cpu_is_mx2()) {
/* setup one handler for all GPIO interrupts */ /* setup one handler for all GPIO interrupts */
set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
set_irq_data(port[0].irq, port); set_irq_data(port[0].irq, port);
#endif }
return 0; return 0;
} }
arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
View file @ 590a94d9
...@@ -12,11 +12,4 @@ ...@@ -12,11 +12,4 @@
#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ #ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__ #define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
#include <mach/hardware.h>
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif #endif
arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h 0 → 100644
View file @ 590a94d9
/*
* Copyright (C) 2009 Eric Benard - eric@eukrea.com
*
* Based on board-pcm038.h which is :
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
#ifndef __ASSEMBLY__
/*
* This CPU module needs a baseboard to work. After basic initializing
* its own devices, it calls baseboard's init function.
* TODO: Add your own baseboard init function and call it from
* inside eukrea_cpuimx27_init().
*
* This example here is for the development board. Refer
* eukrea_mbimx27-baseboard.c
*/
extern void eukrea_mbimx27_baseboard_init(void);
#endif
#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
arch/arm/plat-mxc/include/mach/board-mx21ads.h
View file @ 590a94d9
...@@ -14,12 +14,6 @@ ...@@ -14,12 +14,6 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ #define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
/*
* MXC UART EVB board level configurations
*/
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
/* /*
* Memory-mapped I/O on MX21ADS base board * Memory-mapped I/O on MX21ADS base board
*/ */
......
arch/arm/plat-mxc/include/mach/board-mx27ads.h
View file @ 590a94d9
...@@ -25,12 +25,6 @@ ...@@ -25,12 +25,6 @@
#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \ #define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
MXC_MAX_VIRTUAL_INTS) MXC_MAX_VIRTUAL_INTS)
/*
* MXC UART EVB board level configurations
*/
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
/* /*
* @name Memory Size parameters * @name Memory Size parameters
*/ */
......
arch/arm/plat-mxc/include/mach/board-mx27lite.h
View file @ 590a94d9
...@@ -11,9 +11,4 @@ ...@@ -11,9 +11,4 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__ #define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
arch/arm/plat-mxc/include/mach/board-mx27pdk.h
View file @ 590a94d9
...@@ -11,9 +11,4 @@ ...@@ -11,9 +11,4 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
arch/arm/plat-mxc/include/mach/board-mx31ads.h
View file @ 590a94d9
...@@ -114,9 +114,4 @@ ...@@ -114,9 +114,4 @@
#define MXC_MAX_EXP_IO_LINES 16 #define MXC_MAX_EXP_IO_LINES 16
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
arch/arm/plat-mxc/include/mach/board-mx31lilly.h
View file @ 590a94d9
...@@ -22,11 +22,6 @@ ...@@ -22,11 +22,6 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ #define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
enum mx31lilly_boards { enum mx31lilly_boards {
......
arch/arm/plat-mxc/include/mach/board-mx31lite.h
View file @ 590a94d9
...@@ -11,8 +11,5 @@ ...@@ -11,8 +11,5 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
arch/arm/plat-mxc/include/mach/board-mx31moboard.h
View file @ 590a94d9
...@@ -19,11 +19,6 @@ ...@@ -19,11 +19,6 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
enum mx31moboard_boards { enum mx31moboard_boards {
......
arch/arm/plat-mxc/include/mach/board-mx31pdk.h
View file @ 590a94d9
...@@ -11,11 +11,6 @@ ...@@ -11,11 +11,6 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
/* Definitions for components on the Debug board */ /* Definitions for components on the Debug board */
/* Base address of CPLD controller on the Debug board */ /* Base address of CPLD controller on the Debug board */
......
arch/arm/plat-mxc/include/mach/board-mx35pdk.h
View file @ 590a94d9
...@@ -19,9 +19,4 @@ ...@@ -19,9 +19,4 @@
#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__ #ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
arch/arm/plat-mxc/include/mach/board-pcm037.h
View file @ 590a94d9
...@@ -19,9 +19,4 @@ ...@@ -19,9 +19,4 @@
#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
#define __ASM_ARCH_MXC_BOARD_PCM037_H__ #define __ASM_ARCH_MXC_BOARD_PCM037_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
arch/arm/plat-mxc/include/mach/board-pcm038.h
View file @ 590a94d9
...@@ -19,11 +19,6 @@ ...@@ -19,11 +19,6 @@
#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
#define __ASM_ARCH_MXC_BOARD_PCM038_H__ #define __ASM_ARCH_MXC_BOARD_PCM038_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* /*
* This CPU module needs a baseboard to work. After basic initializing * This CPU module needs a baseboard to work. After basic initializing
......
arch/arm/plat-mxc/include/mach/board-pcm043.h
View file @ 590a94d9
...@@ -19,9 +19,4 @@ ...@@ -19,9 +19,4 @@
#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ #ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
#define __ASM_ARCH_MXC_BOARD_PCM043_H__ #define __ASM_ARCH_MXC_BOARD_PCM043_H__
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ #endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
arch/arm/plat-mxc/include/mach/board-qong.h
View file @ 590a94d9
...@@ -11,11 +11,6 @@ ...@@ -11,11 +11,6 @@
#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
#define __ASM_ARCH_MXC_BOARD_QONG_H__ #define __ASM_ARCH_MXC_BOARD_QONG_H__
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
/* NOR FLASH */ /* NOR FLASH */
#define QONG_NOR_SIZE (128*1024*1024) #define QONG_NOR_SIZE (128*1024*1024)
......
arch/arm/plat-mxc/include/mach/common.h
View file @ 590a94d9
...@@ -16,18 +16,33 @@ struct clk; ...@@ -16,18 +16,33 @@ struct clk;
extern void mx1_map_io(void); extern void mx1_map_io(void);
extern void mx21_map_io(void); extern void mx21_map_io(void);
extern void mx25_map_io(void);
extern void mx27_map_io(void); extern void mx27_map_io(void);
extern void mx31_map_io(void); extern void mx31_map_io(void);
extern void mx35_map_io(void); extern void mx35_map_io(void);
extern void mxc_init_irq(void); extern void mxc91231_map_io(void);
extern void mxc_timer_init(struct clk *timer_clk); extern void mxc_init_irq(void __iomem *);
extern void mx1_init_irq(void);
extern void mx21_init_irq(void);
extern void mx25_init_irq(void);
extern void mx27_init_irq(void);
extern void mx31_init_irq(void);
extern void mx35_init_irq(void);
extern void mxc91231_init_irq(void);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
extern int mx1_clocks_init(unsigned long fref); extern int mx1_clocks_init(unsigned long fref);
extern int mx21_clocks_init(unsigned long lref, unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
extern int mx25_clocks_init(unsigned long fref);
extern int mx27_clocks_init(unsigned long fref); extern int mx27_clocks_init(unsigned long fref);
extern int mx31_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref);
extern int mx35_clocks_init(void); extern int mx35_clocks_init(void);
extern int mxc91231_clocks_init(unsigned long fref);
extern int mxc_register_gpios(void); extern int mxc_register_gpios(void);
extern int mxc_register_device(struct platform_device *pdev, void *data); extern int mxc_register_device(struct platform_device *pdev, void *data);
extern void mxc_set_cpu_type(unsigned int type); extern void mxc_set_cpu_type(unsigned int type);
extern void mxc_arch_reset_init(void __iomem *);
extern void mxc91231_power_off(void);
extern void mxc91231_arch_reset(int, const char *);
extern void mxc91231_prepare_idle(void);
#endif #endif
arch/arm/plat-mxc/include/mach/debug-macro.S
View file @ 590a94d9
...@@ -11,52 +11,52 @@ ...@@ -11,52 +11,52 @@
* *
*/ */
#include <mach/hardware.h> #ifdef CONFIG_ARCH_MX1
#include <mach/mx1.h>
#ifdef CONFIG_MACH_MX31ADS #define UART_PADDR UART1_BASE_ADDR
#include <mach/board-mx31ads.h> #define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
#endif
#ifdef CONFIG_MACH_PCM037
#include <mach/board-pcm037.h>
#endif
#ifdef CONFIG_MACH_MX31LITE
#include <mach/board-mx31lite.h>
#endif
#ifdef CONFIG_MACH_MX27ADS
#include <mach/board-mx27ads.h>
#endif
#ifdef CONFIG_MACH_MX21ADS
#include <mach/board-mx21ads.h>
#endif #endif
#ifdef CONFIG_MACH_PCM038
#include <mach/board-pcm038.h> #ifdef CONFIG_ARCH_MX25
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif #endif
#ifdef CONFIG_MACH_MX31_3DS #include <mach/mx25.h>
#include <mach/board-mx31pdk.h> #define UART_PADDR UART1_BASE_ADDR
#define UART_VADDR MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif #endif
#ifdef CONFIG_MACH_QONG
#include <mach/board-qong.h> #ifdef CONFIG_ARCH_MX2
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif #endif
#ifdef CONFIG_MACH_PCM043 #include <mach/mx2x.h>
#include <mach/board-pcm043.h> #define UART_PADDR UART1_BASE_ADDR
#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
#endif #endif
#ifdef CONFIG_MACH_MX27_3DS
#include <mach/board-mx27pdk.h> #ifdef CONFIG_ARCH_MX3
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif #endif
#ifdef CONFIG_MACH_ARMADILLO5X0 #include <mach/mx3x.h>
#include <mach/board-armadillo5x0.h> #define UART_PADDR UART1_BASE_ADDR
#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif #endif
#ifdef CONFIG_MACH_MX35_3DS
#include <mach/board-mx35pdk.h> #ifdef CONFIG_ARCH_MXC91231
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif #endif
#ifdef CONFIG_MACH_MX27LITE #include <mach/mxc91231.h>
#include <mach/board-mx27lite.h> #define UART_PADDR MXC91231_UART2_BASE_ADDR
#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
#endif #endif
.macro addruart,rx .macro addruart,rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
ldreq \rx, =MXC_LL_UART_PADDR @ physical ldreq \rx, =UART_PADDR @ physical
ldrne \rx, =MXC_LL_UART_VADDR @ virtual ldrne \rx, =UART_VADDR @ virtual
.endm .endm
.macro senduart,rd,rx .macro senduart,rd,rx
......
arch/arm/plat-mxc/include/mach/entry-macro.S
View file @ 590a94d9
...@@ -18,7 +18,8 @@ ...@@ -18,7 +18,8 @@
.endm .endm
.macro get_irqnr_preamble, base, tmp .macro get_irqnr_preamble, base, tmp
ldr \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR) ldr \base, =avic_base
ldr \base, [\base]
#ifdef CONFIG_MXC_IRQ_PRIOR #ifdef CONFIG_MXC_IRQ_PRIOR
ldr r4, [\base, #AVIC_NIMASK] ldr r4, [\base, #AVIC_NIMASK]
#endif #endif
......
arch/arm/plat-mxc/include/mach/hardware.h
View file @ 590a94d9
...@@ -42,6 +42,14 @@ ...@@ -42,6 +42,14 @@
# include <mach/mx1.h> # include <mach/mx1.h>
#endif #endif
#ifdef CONFIG_ARCH_MX25
# include <mach/mx25.h>
#endif
#ifdef CONFIG_ARCH_MXC91231
# include <mach/mxc91231.h>
#endif
#include <mach/mxc.h> #include <mach/mxc.h>
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
arch/arm/plat-mxc/include/mach/imxfb.h
View file @ 590a94d9
...@@ -2,6 +2,8 @@ ...@@ -2,6 +2,8 @@
* This structure describes the machine which we are running on. * This structure describes the machine which we are running on.
*/ */
#include <linux/fb.h>
#define PCR_TFT (1 << 31) #define PCR_TFT (1 << 31)
#define PCR_COLOR (1 << 30) #define PCR_COLOR (1 << 30)
#define PCR_PBSIZ_1 (0 << 28) #define PCR_PBSIZ_1 (0 << 28)
...@@ -13,7 +15,8 @@ ...@@ -13,7 +15,8 @@
#define PCR_BPIX_4 (2 << 25) #define PCR_BPIX_4 (2 << 25)
#define PCR_BPIX_8 (3 << 25) #define PCR_BPIX_8 (3 << 25)
#define PCR_BPIX_12 (4 << 25) #define PCR_BPIX_12 (4 << 25)
#define PCR_BPIX_16 (4 << 25) #define PCR_BPIX_16 (5 << 25)
#define PCR_BPIX_18 (6 << 25)
#define PCR_PIXPOL (1 << 24) #define PCR_PIXPOL (1 << 24)
#define PCR_FLMPOL (1 << 23) #define PCR_FLMPOL (1 << 23)
#define PCR_LPPOL (1 << 22) #define PCR_LPPOL (1 << 22)
...@@ -46,29 +49,21 @@ ...@@ -46,29 +49,21 @@
#define DMACR_HM(x) (((x) & 0xf) << 16) #define DMACR_HM(x) (((x) & 0xf) << 16)
#define DMACR_TM(x) ((x) & 0xf) #define DMACR_TM(x) ((x) & 0xf)
struct imx_fb_platform_data { struct imx_fb_videomode {
u_long pixclock; struct fb_videomode mode;
u32 pcr;
u_short xres; unsigned char bpp;
u_short yres; };
u_int nonstd;
u_char bpp;
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len; struct imx_fb_platform_data {
u_char upper_margin; struct imx_fb_videomode *mode;
u_char lower_margin; int num_modes;
u_char sync;
u_int cmap_greyscale:1, u_int cmap_greyscale:1,
cmap_inverse:1, cmap_inverse:1,
cmap_static:1, cmap_static:1,
unused:29; unused:29;
u_int pcr;
u_int pwmr; u_int pwmr;
u_int lscr1; u_int lscr1;
u_int dmacr; u_int dmacr;
......
arch/arm/plat-mxc/include/mach/iomux-mx25.h 0 → 100644
View file @ 590a94d9
/*
* arch/arm/plat-mxc/include/mach/iomux-mx25.h
*
* Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
*
* based on arch/arm/mach-mx25/mx25_pins.h
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* and
* arch/arm/plat-mxc/include/mach/iomux-mx35.h
* Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __IOMUX_MX25_H__
#define __IOMUX_MX25_H__
#include <mach/iomux-v3.h>
#ifndef GPIO_PORTA
#error Please include mach/iomux.h
#endif
/*
*
* @brief MX25 I/O Pin List
*
* @ingroup GPIO_MX25
*/
#ifndef __ASSEMBLY__
/*
* IOMUX/PAD Bit field definitions
*/
#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL)
#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL)
#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL)
#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL)
#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL)
#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL)
#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL)
#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL)
#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL)
#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL)
#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL)
#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL)
#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL)
#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL)
#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL)
#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL)
#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL)
#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL)
#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL)
#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL)
#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL)
#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL)
#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL)
#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL)
#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL)
#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL)
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
#endif // __ASSEMBLY__
#endif // __IOMUX_MX25_H__
arch/arm/plat-mxc/include/mach/iomux-mx3.h
View file @ 590a94d9
...@@ -635,6 +635,19 @@ enum iomux_pins { ...@@ -635,6 +635,19 @@ enum iomux_pins {
#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
...@@ -669,6 +682,18 @@ enum iomux_pins { ...@@ -669,6 +682,18 @@ enum iomux_pins {
#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
* cspi1_ss1*/ * cspi1_ss1*/
......
arch/arm/plat-mxc/include/mach/iomux-mxc91231.h 0 → 100644
View file @ 590a94d9
/*
* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __MACH_IOMUX_MXC91231_H__
#define __MACH_IOMUX_MXC91231_H__
/*
* various IOMUX output functions
*/
#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
#define IOMUX_ICONFIG_FUNC 2 /* used as function */
#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
/*
* setups a single pin:
* - reserves the pin so that it is not claimed by another driver
* - setups the iomux according to the configuration
* - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
*/
int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
/*
* setups mutliple pins
* convenient way to call the above function with tables
*/
int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
const char *label);
/*
* releases a single pin:
* - make it available for a future use by another driver
* - frees the GPIO if the pin was configured as GPIO
* - DOES NOT reconfigure the IOMUX in its reset state
*/
void mxc_iomux_release_pin(const unsigned int pin_mode);
/*
* releases multiple pins
* convenvient way to call the above function with tables
*/
void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
#define MUX_SIDE_AP (0)
#define MUX_SIDE_SP (1)
#define MUX_SIDE_SHIFT (26)
#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
#define MUX_GPIO_PORT_SHIFT (23)
#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
#define MUX_GPIO_PIN_SHIFT (20)
#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
#define MUX_REG_SHIFT (15)
#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
#define MUX_FIELD_SHIFT (13)
#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
#define MUX_PADGRP_SHIFT (8)
#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
#define MUX_PIN_MASK (0xffffff << 8)
#define GPIO_PORT_MAX (3)
#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
(((side) << MUX_SIDE_SHIFT) | \
(gport << MUX_GPIO_PORT_SHIFT) | \
((gpin) << MUX_GPIO_PIN_SHIFT) | \
((ctlreg) << MUX_REG_SHIFT) | \
((ctlfield) << MUX_FIELD_SHIFT) | \
((padgrp) << MUX_PADGRP_SHIFT))
#define MUX_MODE_OUT_SHIFT (4)
#define MUX_MODE_IN_SHIFT (0)
#define MUX_MODE_SHIFT (0)
#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
#define IOMUX_MODE(pin, mode) \
(pin | (mode << MUX_MODE_SHIFT))
enum iomux_pins {
/* AP Side pins */
MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
/* Shared pins */
MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
};
#define PIN_AP_MAX (104)
#define PIN_SP_MAX (41)
#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
/*
* Convenience values for use with mxc_iomux_mode()
*
* Format here is MXC91231_PIN_(pin name)__(function)
*/
#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
#endif /* __MACH_IOMUX_MXC91231_H__ */
arch/arm/plat-mxc/include/mach/iomux-v3.h
View file @ 590a94d9
...@@ -68,28 +68,24 @@ struct pad_desc { ...@@ -68,28 +68,24 @@ struct pad_desc {
/* /*
* Use to set PAD control * Use to set PAD control
*/ */
#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0
#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1
#define PAD_CTL_NO_HYSTERESIS 0 #define PAD_CTL_DVS (1 << 13)
#define PAD_CTL_HYSTERESIS 1 #define PAD_CTL_HYS (1 << 8)
#define PAD_CTL_PULL_DISABLED 0x0 #define PAD_CTL_PKE (1 << 7)
#define PAD_CTL_PULL_KEEPER 0xa #define PAD_CTL_PUE (1 << 6)
#define PAD_CTL_PULL_DOWN_100K 0xc #define PAD_CTL_PUS_100K_DOWN (0 << 4)
#define PAD_CTL_PULL_UP_47K 0xd #define PAD_CTL_PUS_47K_UP (1 << 4)
#define PAD_CTL_PULL_UP_100K 0xe #define PAD_CTL_PUS_100K_UP (2 << 4)
#define PAD_CTL_PULL_UP_22K 0xf #define PAD_CTL_PUS_22K_UP (3 << 4)
#define PAD_CTL_OUTPUT_CMOS 0 #define PAD_CTL_ODE (1 << 3)
#define PAD_CTL_OUTPUT_OPEN_DRAIN 1
#define PAD_CTL_DRIVE_STRENGTH_NORM 0 #define PAD_CTL_DSE_STANDARD (0 << 1)
#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 #define PAD_CTL_DSE_HIGH (1 << 1)
#define PAD_CTL_DRIVE_STRENGTH_MAX 2 #define PAD_CTL_DSE_MAX (2 << 1)
#define PAD_CTL_SLEW_RATE_SLOW 0 #define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SLEW_RATE_FAST 1
/* /*
* setups a single pad: * setups a single pad:
...@@ -117,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad); ...@@ -117,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad);
*/ */
void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
/*
* Initialise the iomux controller
*/
void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
#endif /* __MACH_IOMUX_V3_H__*/ #endif /* __MACH_IOMUX_V3_H__*/
arch/arm/plat-mxc/include/mach/iomux.h
View file @ 590a94d9
...@@ -49,6 +49,9 @@ ...@@ -49,6 +49,9 @@
#ifdef CONFIG_ARCH_MX2 #ifdef CONFIG_ARCH_MX2
# define GPIO_PORT_MAX 5 # define GPIO_PORT_MAX 5
#endif #endif
#ifdef CONFIG_ARCH_MX25
# define GPIO_PORT_MAX 3
#endif
#ifndef GPIO_PORT_MAX #ifndef GPIO_PORT_MAX
# error "GPIO config port count unknown!" # error "GPIO config port count unknown!"
...@@ -107,6 +110,9 @@ ...@@ -107,6 +110,9 @@
#include <mach/iomux-mx27.h> #include <mach/iomux-mx27.h>
#endif #endif
#endif #endif
#ifdef CONFIG_ARCH_MX25
#include <mach/iomux-mx25.h>
#endif
/* decode irq number to use with IMR(x), ISR(x) and friends */ /* decode irq number to use with IMR(x), ISR(x) and friends */
......
arch/arm/plat-mxc/include/mach/irqs.h
View file @ 590a94d9
...@@ -24,6 +24,10 @@ ...@@ -24,6 +24,10 @@
#define MXC_GPIO_IRQS (32 * 6) #define MXC_GPIO_IRQS (32 * 6)
#elif defined CONFIG_ARCH_MX3 #elif defined CONFIG_ARCH_MX3
#define MXC_GPIO_IRQS (32 * 3) #define MXC_GPIO_IRQS (32 * 3)
#elif defined CONFIG_ARCH_MX25
#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MXC91231
#define MXC_GPIO_IRQS (32 * 4)
#endif #endif
/* /*
......
arch/arm/plat-mxc/include/mach/memory.h
View file @ 590a94d9
...@@ -22,6 +22,10 @@ ...@@ -22,6 +22,10 @@
#endif #endif
#elif defined CONFIG_ARCH_MX3 #elif defined CONFIG_ARCH_MX3
#define PHYS_OFFSET UL(0x80000000) #define PHYS_OFFSET UL(0x80000000)
#elif defined CONFIG_ARCH_MX25
#define PHYS_OFFSET UL(0x80000000)
#elif defined CONFIG_ARCH_MXC91231
#define PHYS_OFFSET UL(0x90000000)
#endif #endif
#if defined(CONFIG_MX1_VIDEO) #if defined(CONFIG_MX1_VIDEO)
......
arch/arm/plat-mxc/include/mach/mx1.h
View file @ 590a94d9
...@@ -12,10 +12,6 @@ ...@@ -12,10 +12,6 @@
#ifndef __ASM_ARCH_MXC_MX1_H__ #ifndef __ASM_ARCH_MXC_MX1_H__
#define __ASM_ARCH_MXC_MX1_H__ #define __ASM_ARCH_MXC_MX1_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
#include <mach/vmalloc.h> #include <mach/vmalloc.h>
/* /*
...@@ -138,20 +134,6 @@ ...@@ -138,20 +134,6 @@
#define GPIO_INT_PORTD 62 #define GPIO_INT_PORTD 62
#define WDT_INT 63 #define WDT_INT 63
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x1C
#define GPIO_GDIR 0x00
#define GPIO_PSR 0x24
#define GPIO_ICR1 0x28
#define GPIO_ICR2 0x2C
#define GPIO_IMR 0x30
#define GPIO_ISR 0x34
#define GPIO_INT_LOW_LEV 0x3
#define GPIO_INT_HIGH_LEV 0x2
#define GPIO_INT_RISE_EDGE 0x0
#define GPIO_INT_FALL_EDGE 0x1
#define GPIO_INT_NONE 0x4
/* DMA */ /* DMA */
#define DMA_REQ_UART3_T 2 #define DMA_REQ_UART3_T 2
#define DMA_REQ_UART3_R 3 #define DMA_REQ_UART3_R 3
...@@ -179,8 +161,4 @@ ...@@ -179,8 +161,4 @@
#define DMA_REQ_UART1_T 30 #define DMA_REQ_UART1_T 30
#define DMA_REQ_UART1_R 31 #define DMA_REQ_UART1_R 31
/* mandatory for CONFIG_DEBUG_LL */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_MX1_H__ */ #endif /* __ASM_ARCH_MXC_MX1_H__ */
arch/arm/plat-mxc/include/mach/mx21.h
View file @ 590a94d9
...@@ -25,11 +25,6 @@ ...@@ -25,11 +25,6 @@
#ifndef __ASM_ARCH_MXC_MX21_H__ #ifndef __ASM_ARCH_MXC_MX21_H__
#define __ASM_ARCH_MXC_MX21_H__ #define __ASM_ARCH_MXC_MX21_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
/* Memory regions and CS */ /* Memory regions and CS */
#define SDRAM_BASE_ADDR 0xC0000000 #define SDRAM_BASE_ADDR 0xC0000000
#define CSD1_BASE_ADDR 0xC4000000 #define CSD1_BASE_ADDR 0xC4000000
......
arch/arm/plat-mxc/include/mach/mx25.h 0 → 100644
View file @ 590a94d9
#ifndef __MACH_MX25_H__
#define __MACH_MX25_H__
#define MX25_AIPS1_BASE_ADDR 0x43F00000
#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000
#define MX25_AIPS1_SIZE SZ_1M
#define MX25_AIPS2_BASE_ADDR 0x53F00000
#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000
#define MX25_AIPS2_SIZE SZ_1M
#define MX25_AVIC_BASE_ADDR 0x68000000
#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000
#define MX25_AVIC_SIZE SZ_1M
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
#define MX25_AIPS1_IO_ADDRESS(x) \
(((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
#define MX25_AIPS2_IO_ADDRESS(x) \
(((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT)
#define MX25_AVIC_IO_ADDRESS(x) \
(((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
#define MX25_IO_ADDRESS(x) \
(void __force __iomem *) \
(__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
__in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \
__in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \
0xDEADBEEF)
#define UART1_BASE_ADDR 0x43f90000
#define UART2_BASE_ADDR 0x43f94000
#endif /* __MACH_MX25_H__ */
arch/arm/plat-mxc/include/mach/mx27.h
View file @ 590a94d9
...@@ -24,10 +24,6 @@ ...@@ -24,10 +24,6 @@
#ifndef __ASM_ARCH_MXC_MX27_H__ #ifndef __ASM_ARCH_MXC_MX27_H__
#define __ASM_ARCH_MXC_MX27_H__ #define __ASM_ARCH_MXC_MX27_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
/* IRAM */ /* IRAM */
#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
...@@ -120,7 +116,4 @@ extern int mx27_revision(void); ...@@ -120,7 +116,4 @@ extern int mx27_revision(void);
/* Mandatory defines used globally */ /* Mandatory defines used globally */
/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
#define ARCH_NR_GPIOS (192 + 16)
#endif /* __ASM_ARCH_MXC_MX27_H__ */ #endif /* __ASM_ARCH_MXC_MX27_H__ */
arch/arm/plat-mxc/include/mach/mx2x.h
View file @ 590a94d9
...@@ -23,10 +23,6 @@ ...@@ -23,10 +23,6 @@
#ifndef __ASM_ARCH_MXC_MX2x_H__ #ifndef __ASM_ARCH_MXC_MX2x_H__
#define __ASM_ARCH_MXC_MX2x_H__ #define __ASM_ARCH_MXC_MX2x_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
/* The following addresses are common between i.MX21 and i.MX27 */ /* The following addresses are common between i.MX21 and i.MX27 */
/* Register offests */ /* Register offests */
...@@ -154,20 +150,6 @@ ...@@ -154,20 +150,6 @@
#define MXC_INT_GPIO 8 #define MXC_INT_GPIO 8
#define MXC_INT_CSPI3 6 #define MXC_INT_CSPI3 6
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x1C
#define GPIO_GDIR 0x00
#define GPIO_PSR 0x24
#define GPIO_ICR1 0x28
#define GPIO_ICR2 0x2C
#define GPIO_IMR 0x30
#define GPIO_ISR 0x34
#define GPIO_INT_LOW_LEV 0x3
#define GPIO_INT_HIGH_LEV 0x2
#define GPIO_INT_RISE_EDGE 0x0
#define GPIO_INT_FALL_EDGE 0x1
#define GPIO_INT_NONE 0x4
/* fixed DMA request numbers */ /* fixed DMA request numbers */
#define DMA_REQ_CSI_RX 31 #define DMA_REQ_CSI_RX 31
#define DMA_REQ_CSI_STAT 30 #define DMA_REQ_CSI_STAT 30
......
arch/arm/plat-mxc/include/mach/mx31.h
View file @ 590a94d9
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
#define MX31_IRAM_SIZE SZ_16K #define MX31_IRAM_SIZE SZ_16K
#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) #define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
......
arch/arm/plat-mxc/include/mach/mx35.h
View file @ 590a94d9
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
#define MX35_IRAM_SIZE SZ_128K #define MX35_IRAM_SIZE SZ_128K
#define MXC_FEC_BASE_ADDR 0x50038000 #define MXC_FEC_BASE_ADDR 0x50038000
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_NFC_BASE_ADDR 0xBB000000 #define MX35_NFC_BASE_ADDR 0xBB000000
/* /*
......
arch/arm/plat-mxc/include/mach/mx3x.h
View file @ 590a94d9
...@@ -11,10 +11,6 @@ ...@@ -11,10 +11,6 @@
#ifndef __ASM_ARCH_MXC_MX31_H__ #ifndef __ASM_ARCH_MXC_MX31_H__
#define __ASM_ARCH_MXC_MX31_H__ #define __ASM_ARCH_MXC_MX31_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
/* /*
* MX31 memory map: * MX31 memory map:
* *
...@@ -263,25 +259,8 @@ ...@@ -263,25 +259,8 @@
#define SYSTEM_REV_MIN CHIP_REV_1_0 #define SYSTEM_REV_MIN CHIP_REV_1_0
#define SYSTEM_REV_NUM 3 #define SYSTEM_REV_NUM 3
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x00
#define GPIO_GDIR 0x04
#define GPIO_PSR 0x08
#define GPIO_ICR1 0x0C
#define GPIO_ICR2 0x10
#define GPIO_IMR 0x14
#define GPIO_ISR 0x18
#define GPIO_INT_LOW_LEV 0x0
#define GPIO_INT_HIGH_LEV 0x1
#define GPIO_INT_RISE_EDGE 0x2
#define GPIO_INT_FALL_EDGE 0x3
#define GPIO_INT_NONE 0x4
/* Mandatory defines used globally */ /* Mandatory defines used globally */
/* this CPU supports up to 96 GPIOs */
#define ARCH_NR_GPIOS 96
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern unsigned int system_rev; extern unsigned int system_rev;
......
arch/arm/plat-mxc/include/mach/mxc.h
View file @ 590a94d9
...@@ -26,9 +26,11 @@ ...@@ -26,9 +26,11 @@
#define MXC_CPU_MX1 1 #define MXC_CPU_MX1 1
#define MXC_CPU_MX21 21 #define MXC_CPU_MX21 21
#define MXC_CPU_MX25 25
#define MXC_CPU_MX27 27 #define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31 #define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35 #define MXC_CPU_MX35 35
#define MXC_CPU_MXC91231 91231
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type; extern unsigned int __mxc_cpu_type;
...@@ -58,6 +60,18 @@ extern unsigned int __mxc_cpu_type; ...@@ -58,6 +60,18 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx21() (0) # define cpu_is_mx21() (0)
#endif #endif
#ifdef CONFIG_ARCH_MX25
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX25
# endif
# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
#else
# define cpu_is_mx25() (0)
#endif
#ifdef CONFIG_MACH_MX27 #ifdef CONFIG_MACH_MX27
# ifdef mxc_cpu_type # ifdef mxc_cpu_type
# undef mxc_cpu_type # undef mxc_cpu_type
...@@ -94,13 +108,25 @@ extern unsigned int __mxc_cpu_type; ...@@ -94,13 +108,25 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx35() (0) # define cpu_is_mx35() (0)
#endif #endif
#ifdef CONFIG_ARCH_MXC91231
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MXC91231
# endif
# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231)
#else
# define cpu_is_mxc91231() (0)
#endif
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
#endif #endif
#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
#endif /* __ASM_ARCH_MXC_H__ */ #endif /* __ASM_ARCH_MXC_H__ */
arch/arm/plat-mxc/include/mach/mxc91231.h 0 → 100644
View file @ 590a94d9
/*
* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
* - Platform specific register memory map
*
* Copyright 2005-2007 Motorola, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __MACH_MXC91231_H__
#define __MACH_MXC91231_H__
/*
* L2CC
*/
#define MXC91231_L2CC_BASE_ADDR 0x30000000
#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000
#define MXC91231_L2CC_SIZE SZ_64K
/*
* AIPS 1
*/
#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000
#define MXC91231_AIPS1_SIZE SZ_1M
#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
/*
* AIPS 2
*/
#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000
#define MXC91231_AIPS2_SIZE SZ_1M
#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
/*
* SPBA global module 0
*/
#define MXC91231_SPBA0_BASE_ADDR 0x50000000
#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000
#define MXC91231_SPBA0_SIZE SZ_1M
#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
/*
* SPBA global module 1
*/
#define MXC91231_SPBA1_BASE_ADDR 0x52000000
#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000
#define MXC91231_SPBA1_SIZE SZ_1M
#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
/*!
* Defines for SPBA modules
*/
#define MXC91231_SPBA_SDHC1 0x04
#define MXC91231_SPBA_SDHC2 0x08
#define MXC91231_SPBA_UART3 0x0C
#define MXC91231_SPBA_CSPI2 0x10
#define MXC91231_SPBA_SSI2 0x14
#define MXC91231_SPBA_SIM 0x18
#define MXC91231_SPBA_IIM 0x1C
#define MXC91231_SPBA_CTI_SDMA 0x20
#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
#define MXC91231_SPBA_CSPI1 0x30
#define MXC91231_SPBA_MQSPI 0x34
#define MXC91231_SPBA_EL1T 0x38
#define MXC91231_SPBA_IOMUX 0x40
#define MXC91231_SPBA_CRM_COM 0x44
#define MXC91231_SPBA_CRM_AP 0x48
#define MXC91231_SPBA_PLL0 0x4C
#define MXC91231_SPBA_PLL1 0x50
#define MXC91231_SPBA_PLL2 0x54
#define MXC91231_SPBA_GPIO4 0x58
#define MXC91231_SPBA_SAHARA 0x5C
/*
* ROMP and AVIC
*/
#define MXC91231_ROMP_BASE_ADDR 0x60000000
#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000
#define MXC91231_ROMP_SIZE SZ_64K
#define MXC91231_AVIC_BASE_ADDR 0x68000000
#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000
#define MXC91231_AVIC_SIZE SZ_64K
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000
#define MXC91231_X_MEMC_SIZE SZ_64K
#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
/*
* Memory regions and CS
* CPLD is connected on CS4
* CS5 is TP1021 or it is not connected
* */
#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
#define MXC91231_FB_RAM_SIZE SZ_256K
#define MXC91231_CSD0_BASE_ADDR 0x80000000
#define MXC91231_CSD1_BASE_ADDR 0x90000000
#define MXC91231_CS0_BASE_ADDR 0xA0000000
#define MXC91231_CS1_BASE_ADDR 0xA8000000
#define MXC91231_CS2_BASE_ADDR 0xB0000000
#define MXC91231_CS3_BASE_ADDR 0xB2000000
#define MXC91231_CS4_BASE_ADDR 0xB4000000
#define MXC91231_CS5_BASE_ADDR 0xB6000000
/* Is given address belongs to the specified memory region? */
#define ADDRESS_IN_REGION(addr, start, size) \
(((addr) >= (start)) && ((addr) < (start)+(size)))
/* Is given address belongs to the specified named `module'? */
#define MXC91231_IS_MODULE(addr, module) \
ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
MXC91231_ ## module ## _SIZE)
/*
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF
*/
#define MXC91231_IO_ADDRESS(x) \
(void __iomem *) \
(MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
0xDEADBEEF)
/*
* define the address mapping macros: in physical address order
*/
#define MXC91231_L2CC_IO_ADDRESS(x) \
(((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
#define MXC91231_AIPS1_IO_ADDRESS(x) \
(((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
#define MXC91231_SPBA0_IO_ADDRESS(x) \
(((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
#define MXC91231_SPBA1_IO_ADDRESS(x) \
(((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
#define MXC91231_AIPS2_IO_ADDRESS(x) \
(((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
#define MXC91231_ROMP_IO_ADDRESS(x) \
(((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
#define MXC91231_AVIC_IO_ADDRESS(x) \
(((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
#define MXC91231_X_MEMC_IO_ADDRESS(x) \
(((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT)
/*
* Interrupt numbers
*/
#define MXC91231_INT_GPIO3 0
#define MXC91231_INT_EL1T_CI 1
#define MXC91231_INT_EL1T_RFCI 2
#define MXC91231_INT_EL1T_RFI 3
#define MXC91231_INT_EL1T_MCU 4
#define MXC91231_INT_EL1T_IPI 5
#define MXC91231_INT_MU_GEN 6
#define MXC91231_INT_GPIO4 7
#define MXC91231_INT_MMC_SDHC2 8
#define MXC91231_INT_MMC_SDHC1 9
#define MXC91231_INT_I2C 10
#define MXC91231_INT_SSI2 11
#define MXC91231_INT_SSI1 12
#define MXC91231_INT_CSPI2 13
#define MXC91231_INT_CSPI1 14
#define MXC91231_INT_RTIC 15
#define MXC91231_INT_SAHARA 15
#define MXC91231_INT_HAC 15
#define MXC91231_INT_UART3_RX 16
#define MXC91231_INT_UART3_TX 17
#define MXC91231_INT_UART3_MINT 18
#define MXC91231_INT_ECT 19
#define MXC91231_INT_SIM_IPB 20
#define MXC91231_INT_SIM_DATA 21
#define MXC91231_INT_RNGA 22
#define MXC91231_INT_DSM_AP 23
#define MXC91231_INT_KPP 24
#define MXC91231_INT_RTC 25
#define MXC91231_INT_PWM 26
#define MXC91231_INT_GEMK_AP 27
#define MXC91231_INT_EPIT 28
#define MXC91231_INT_GPT 29
#define MXC91231_INT_UART2_RX 30
#define MXC91231_INT_UART2_TX 31
#define MXC91231_INT_UART2_MINT 32
#define MXC91231_INT_NANDFC 33
#define MXC91231_INT_SDMA 34
#define MXC91231_INT_USB_WAKEUP 35
#define MXC91231_INT_USB_SOF 36
#define MXC91231_INT_PMU_EVTMON 37
#define MXC91231_INT_USB_FUNC 38
#define MXC91231_INT_USB_DMA 39
#define MXC91231_INT_USB_CTRL 40
#define MXC91231_INT_IPU_ERR 41
#define MXC91231_INT_IPU_SYN 42
#define MXC91231_INT_UART1_RX 43
#define MXC91231_INT_UART1_TX 44
#define MXC91231_INT_UART1_MINT 45
#define MXC91231_INT_IIM 46
#define MXC91231_INT_MU_RX_OR 47
#define MXC91231_INT_MU_TX_OR 48
#define MXC91231_INT_SCC_SCM 49
#define MXC91231_INT_SCC_SMN 50
#define MXC91231_INT_GPIO2 51
#define MXC91231_INT_GPIO1 52
#define MXC91231_INT_MQSPI1 53
#define MXC91231_INT_MQSPI2 54
#define MXC91231_INT_WDOG2 55
#define MXC91231_INT_EXT_INT7 56
#define MXC91231_INT_EXT_INT6 57
#define MXC91231_INT_EXT_INT5 58
#define MXC91231_INT_EXT_INT4 59
#define MXC91231_INT_EXT_INT3 60
#define MXC91231_INT_EXT_INT2 61
#define MXC91231_INT_EXT_INT1 62
#define MXC91231_INT_EXT_INT0 63
#define MXC91231_MAX_INT_LINES 63
#define MXC91231_MAX_EXT_LINES 8
#endif /* __MACH_MXC91231_H__ */
arch/arm/plat-mxc/include/mach/system.h
View file @ 590a94d9
...@@ -21,8 +21,18 @@ ...@@ -21,8 +21,18 @@
#ifndef __ASM_ARCH_MXC_SYSTEM_H__ #ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__
#include <mach/hardware.h>
#include <mach/common.h>
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
#ifdef CONFIG_ARCH_MXC91231
if (cpu_is_mxc91231()) {
/* Need this to set DSM low-power mode */
mxc91231_prepare_idle();
}
#endif
cpu_do_idle(); cpu_do_idle();
} }
......
arch/arm/plat-mxc/include/mach/timex.h
View file @ 590a94d9
...@@ -26,6 +26,10 @@ ...@@ -26,6 +26,10 @@
#define CLOCK_TICK_RATE 13300000 #define CLOCK_TICK_RATE 13300000
#elif defined CONFIG_ARCH_MX3 #elif defined CONFIG_ARCH_MX3
#define CLOCK_TICK_RATE 16625000 #define CLOCK_TICK_RATE 16625000
#elif defined CONFIG_ARCH_MX25
#define CLOCK_TICK_RATE 16000000
#elif defined CONFIG_ARCH_MXC91231
#define CLOCK_TICK_RATE 13000000
#endif #endif
#endif /* __ASM_ARCH_MXC_TIMEX_H__ */ #endif /* __ASM_ARCH_MXC_TIMEX_H__ */
arch/arm/plat-mxc/include/mach/uncompress.h
View file @ 590a94d9
...@@ -26,8 +26,11 @@ ...@@ -26,8 +26,11 @@
#define __MXC_BOOT_UNCOMPRESS #define __MXC_BOOT_UNCOMPRESS
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/mach-types.h>
#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) static unsigned long uart_base;
#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
#define USR2 0x98 #define USR2 0x98
#define USR2_TXFE (1<<14) #define USR2_TXFE (1<<14)
...@@ -46,19 +49,10 @@ ...@@ -46,19 +49,10 @@
static void putc(int ch) static void putc(int ch)
{ {
static unsigned long serial_port = 0; if (!uart_base)
return;
if (unlikely(serial_port == 0)) { if (!(UART(UCR1) & UCR1_UARTEN))
do {
serial_port = UART1_BASE_ADDR;
if (UART(UCR1) & UCR1_UARTEN)
break;
serial_port = UART2_BASE_ADDR;
if (UART(UCR1) & UCR1_UARTEN)
break;
return; return;
} while (0);
}
while (!(UART(USR2) & USR2_TXFE)) while (!(UART(USR2) & USR2_TXFE))
barrier(); barrier();
...@@ -68,11 +62,49 @@ static void putc(int ch) ...@@ -68,11 +62,49 @@ static void putc(int ch)
#define flush() do { } while (0) #define flush() do { } while (0)
/* #define MX1_UART1_BASE_ADDR 0x00206000
* nothing to do #define MX25_UART1_BASE_ADDR 0x43f90000
*/ #define MX2X_UART1_BASE_ADDR 0x1000a000
#define arch_decomp_setup() #define MX3X_UART1_BASE_ADDR 0x43F90000
#define MX3X_UART2_BASE_ADDR 0x43F94000
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
switch (arch_id) {
case MACH_TYPE_MX1ADS:
case MACH_TYPE_SCB9328:
uart_base = MX1_UART1_BASE_ADDR;
break;
case MACH_TYPE_MX25_3DS:
uart_base = MX25_UART1_BASE_ADDR;
break;
case MACH_TYPE_IMX27LITE:
case MACH_TYPE_MX27_3DS:
case MACH_TYPE_MX27ADS:
case MACH_TYPE_PCM038:
case MACH_TYPE_MX21ADS:
uart_base = MX2X_UART1_BASE_ADDR;
break;
case MACH_TYPE_MX31LITE:
case MACH_TYPE_ARMADILLO5X0:
case MACH_TYPE_MX31MOBOARD:
case MACH_TYPE_QONG:
case MACH_TYPE_MX31_3DS:
case MACH_TYPE_PCM037:
case MACH_TYPE_MX31ADS:
case MACH_TYPE_MX35_3DS:
case MACH_TYPE_PCM043:
uart_base = MX3X_UART1_BASE_ADDR;
break;
case MACH_TYPE_MAGX_ZN5:
uart_base = MX3X_UART2_BASE_ADDR;
break;
default:
break;
}
}
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#define arch_decomp_wdog() #define arch_decomp_wdog()
#endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */ #endif /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
arch/arm/plat-mxc/iomux-v3.c
View file @ 590a94d9
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <mach/iomux-v3.h> #include <mach/iomux-v3.h>
#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) static void __iomem *base;
static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
...@@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad) ...@@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
return -EBUSY; return -EBUSY;
if (pad->mux_ctrl_ofs) if (pad->mux_ctrl_ofs)
__raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs); __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
if (pad->select_input_ofs) if (pad->select_input_ofs)
__raw_writel(pad->select_input, __raw_writel(pad->select_input,
IOMUX_BASE + pad->select_input_ofs); base + pad->select_input_ofs);
if (!(pad->pad_ctrl & NO_PAD_CTRL)) if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
__raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs); __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
return 0; return 0;
} }
EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
...@@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count) ...@@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
} }
} }
EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
{
base = iomux_v3_base;
}
arch/arm/plat-mxc/irq.c
View file @ 590a94d9
...@@ -44,7 +44,7 @@ ...@@ -44,7 +44,7 @@
#define AVIC_FIPNDH 0x60 /* fast int pending high */ #define AVIC_FIPNDH 0x60 /* fast int pending high */
#define AVIC_FIPNDL 0x64 /* fast int pending low */ #define AVIC_FIPNDL 0x64 /* fast int pending low */
static void __iomem *avic_base; void __iomem *avic_base;
int imx_irq_set_priority(unsigned char irq, unsigned char prio) int imx_irq_set_priority(unsigned char irq, unsigned char prio)
{ {
...@@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = { ...@@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = {
* interrupts. It registers the interrupt enable and disable functions * interrupts. It registers the interrupt enable and disable functions
* to the kernel for each interrupt source. * to the kernel for each interrupt source.
*/ */
void __init mxc_init_irq(void) void __init mxc_init_irq(void __iomem *irqbase)
{ {
int i; int i;
avic_base = IO_ADDRESS(AVIC_BASE_ADDR); avic_base = irqbase;
/* put the AVIC into the reset value with /* put the AVIC into the reset value with
* all interrupts disabled * all interrupts disabled
......
arch/arm/plat-mxc/pwm.c
View file @ 590a94d9
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#define MX3_PWMPR 0x10 /* PWM Period Register */ #define MX3_PWMPR 0x10 /* PWM Period Register */
#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
#define MX3_PWMCR_EN (1 << 0) #define MX3_PWMCR_EN (1 << 0)
...@@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) ...@@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
return -EINVAL; return -EINVAL;
if (cpu_is_mx27() || cpu_is_mx3()) { if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) {
unsigned long long c; unsigned long long c;
unsigned long period_cycles, duty_cycles, prescale; unsigned long period_cycles, duty_cycles, prescale;
u32 cr;
c = clk_get_rate(pwm->clk); c = clk_get_rate(pwm->clk);
c = c * period_ns; c = c * period_ns;
do_div(c, 1000000000); do_div(c, 1000000000);
...@@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) ...@@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
writel(period_cycles, pwm->mmio_base + MX3_PWMPR); writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
writel(MX3_PWMCR_PRESCALER(prescale - 1) |
MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN, cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;
pwm->mmio_base + MX3_PWMCR);
if (cpu_is_mx25())
cr |= MX3_PWMCR_CLKSRC_IPG;
else
cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
writel(cr, pwm->mmio_base + MX3_PWMCR);
} else if (cpu_is_mx1() || cpu_is_mx21()) { } else if (cpu_is_mx1() || cpu_is_mx21()) {
/* The PWM subsystem allows for exact frequencies. However, /* The PWM subsystem allows for exact frequencies. However,
* I cannot connect a scope on my device to the PWM line and * I cannot connect a scope on my device to the PWM line and
...@@ -118,6 +127,8 @@ EXPORT_SYMBOL(pwm_enable); ...@@ -118,6 +127,8 @@ EXPORT_SYMBOL(pwm_enable);
void pwm_disable(struct pwm_device *pwm) void pwm_disable(struct pwm_device *pwm)
{ {
writel(0, pwm->mmio_base + MX3_PWMCR);
if (pwm->clk_enabled) { if (pwm->clk_enabled) {
clk_disable(pwm->clk); clk_disable(pwm->clk);
pwm->clk_enabled = 0; pwm->clk_enabled = 0;
......
arch/arm/plat-mxc/system.c
View file @ 590a94d9
...@@ -27,32 +27,38 @@ ...@@ -27,32 +27,38 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/common.h>
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
#include <asm/system.h> #include <asm/system.h>
#ifdef CONFIG_ARCH_MX1 static void __iomem *wdog_base;
#define WDOG_WCR_REG IO_ADDRESS(WDT_BASE_ADDR)
#define WDOG_WCR_ENABLE (1 << 0)
#else
#define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR)
#define WDOG_WCR_ENABLE (1 << 2)
#endif
/* /*
* Reset the system. It is called by machine_restart(). * Reset the system. It is called by machine_restart().
*/ */
void arch_reset(char mode, const char *cmd) void arch_reset(char mode, const char *cmd)
{ {
if (!cpu_is_mx1()) { unsigned int wcr_enable;
#ifdef CONFIG_ARCH_MXC91231
if (cpu_is_mxc91231()) {
mxc91231_arch_reset(mode, cmd);
return;
}
#endif
if (cpu_is_mx1()) {
wcr_enable = (1 << 0);
} else {
struct clk *clk; struct clk *clk;
clk = clk_get_sys("imx-wdt.0", NULL); clk = clk_get_sys("imx-wdt.0", NULL);
if (!IS_ERR(clk)) if (!IS_ERR(clk))
clk_enable(clk); clk_enable(clk);
wcr_enable = (1 << 2);
} }
/* Assert SRS signal */ /* Assert SRS signal */
__raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG); __raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */ /* wait for reset to assert... */
mdelay(500); mdelay(500);
...@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd) ...@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd)
/* we'll take a jump through zero as a poor second */ /* we'll take a jump through zero as a poor second */
cpu_reset(0); cpu_reset(0);
} }
void mxc_arch_reset_init(void __iomem *base)
{
wdog_base = base;
}
arch/arm/plat-mxc/time.c
View file @ 590a94d9
...@@ -47,7 +47,7 @@ ...@@ -47,7 +47,7 @@
#define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_CAPT (1 << 1)
#define MX2_TSTAT_COMP (1 << 0) #define MX2_TSTAT_COMP (1 << 0)
/* MX31, MX35 */ /* MX31, MX35, MX25, MXC91231 */
#define MX3_TCTL_WAITEN (1 << 3) #define MX3_TCTL_WAITEN (1 << 3)
#define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_CLK_IPG (1 << 6)
#define MX3_TCTL_FRR (1 << 9) #define MX3_TCTL_FRR (1 << 9)
...@@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void) ...@@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void)
{ {
unsigned int tmp; unsigned int tmp;
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
__raw_writel(0, timer_base + MX3_IR); __raw_writel(0, timer_base + MX3_IR);
else { else {
tmp = __raw_readl(timer_base + MXC_TCTL); tmp = __raw_readl(timer_base + MXC_TCTL);
...@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void) ...@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
static inline void gpt_irq_enable(void) static inline void gpt_irq_enable(void)
{ {
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
__raw_writel(1<<0, timer_base + MX3_IR); __raw_writel(1<<0, timer_base + MX3_IR);
else { else {
__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
...@@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void) ...@@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void)
__raw_writel(0, timer_base + MX1_2_TSTAT); __raw_writel(0, timer_base + MX1_2_TSTAT);
if (cpu_is_mx2()) if (cpu_is_mx2())
__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
__raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
} }
...@@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) ...@@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
{ {
unsigned int c = clk_get_rate(timer_clk); unsigned int c = clk_get_rate(timer_clk);
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.read = mx3_get_cycles;
clocksource_mxc.mult = clocksource_hz2mult(c, clocksource_mxc.mult = clocksource_hz2mult(c,
...@@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode, ...@@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
if (mode != clockevent_mode) { if (mode != clockevent_mode) {
/* Set event time into far-far future */ /* Set event time into far-far future */
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
__raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
timer_base + MX3_TCMP); timer_base + MX3_TCMP);
else else
...@@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) ...@@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
struct clock_event_device *evt = &clockevent_mxc; struct clock_event_device *evt = &clockevent_mxc;
uint32_t tstat; uint32_t tstat;
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
tstat = __raw_readl(timer_base + MX3_TSTAT); tstat = __raw_readl(timer_base + MX3_TSTAT);
else else
tstat = __raw_readl(timer_base + MX1_2_TSTAT); tstat = __raw_readl(timer_base + MX1_2_TSTAT);
...@@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) ...@@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
{ {
unsigned int c = clk_get_rate(timer_clk); unsigned int c = clk_get_rate(timer_clk);
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.set_next_event = mx3_set_next_event;
clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
...@@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) ...@@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
return 0; return 0;
} }
void __init mxc_timer_init(struct clk *timer_clk) void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
{ {
uint32_t tctl_val; uint32_t tctl_val;
int irq;
clk_enable(timer_clk); clk_enable(timer_clk);
if (cpu_is_mx1()) { timer_base = base;
#ifdef CONFIG_ARCH_MX1
timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
irq = TIM1_INT;
#endif
} else if (cpu_is_mx2()) {
#ifdef CONFIG_ARCH_MX2
timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
irq = MXC_INT_GPT1;
#endif
} else if (cpu_is_mx3()) {
#ifdef CONFIG_ARCH_MX3
timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
irq = MXC_INT_GPT;
#endif
} else
BUG();
/* /*
* Initialise to a known state (all timers off, and timing reset) * Initialise to a known state (all timers off, and timing reset)
...@@ -313,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk) ...@@ -313,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk)
__raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TCTL);
__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
if (cpu_is_mx3()) if (cpu_is_mx3() || cpu_is_mx25())
tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
else else
tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
......
drivers/serial/imx.c
View file @ 590a94d9
...@@ -67,21 +67,8 @@ ...@@ -67,21 +67,8 @@
#define UBIR 0xa4 /* BRM Incremental Register */ #define UBIR 0xa4 /* BRM Incremental Register */
#define UBMR 0xa8 /* BRM Modulator Register */ #define UBMR 0xa8 /* BRM Modulator Register */
#define UBRC 0xac /* Baud Rate Count Register */ #define UBRC 0xac /* Baud Rate Count Register */
#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 #define MX2_ONEMS 0xb0 /* One Millisecond register */
#define ONEMS 0xb0 /* One Millisecond register */ #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */
#define UTS 0xb4 /* UART Test Register */
#endif
#ifdef CONFIG_ARCH_MX1
#define BIPR1 0xb0 /* Incremental Preset Register 1 */
#define BIPR2 0xb4 /* Incremental Preset Register 2 */
#define BIPR3 0xb8 /* Incremental Preset Register 3 */
#define BIPR4 0xbc /* Incremental Preset Register 4 */
#define BMPR1 0xc0 /* BRM Modulator Register 1 */
#define BMPR2 0xc4 /* BRM Modulator Register 2 */
#define BMPR3 0xc8 /* BRM Modulator Register 3 */
#define BMPR4 0xcc /* BRM Modulator Register 4 */
#define UTS 0xd0 /* UART Test Register */
#endif
/* UART Control Register Bit Fields.*/ /* UART Control Register Bit Fields.*/
#define URXD_CHARRDY (1<<15) #define URXD_CHARRDY (1<<15)
...@@ -101,12 +88,7 @@ ...@@ -101,12 +88,7 @@
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
#define UCR1_SNDBRK (1<<4) /* Send break */ #define UCR1_SNDBRK (1<<4) /* Send break */
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
#ifdef CONFIG_ARCH_MX1 #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
#endif
#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
#define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */
#endif
#define UCR1_DOZE (1<<1) /* Doze */ #define UCR1_DOZE (1<<1) /* Doze */
#define UCR1_UARTEN (1<<0) /* UART enabled */ #define UCR1_UARTEN (1<<0) /* UART enabled */
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
...@@ -132,13 +114,9 @@ ...@@ -132,13 +114,9 @@
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
#ifdef CONFIG_ARCH_MX1 #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
#endif
#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
#define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
#endif
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
#define UCR3_BPEN (1<<0) /* Preset registers enable */ #define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
...@@ -186,12 +164,10 @@ ...@@ -186,12 +164,10 @@
#define UTS_SOFTRST (1<<0) /* Software reset */ #define UTS_SOFTRST (1<<0) /* Software reset */
/* We've been assigned a range on the "Low-density serial ports" major */ /* We've been assigned a range on the "Low-density serial ports" major */
#ifdef CONFIG_ARCH_MXC
#define SERIAL_IMX_MAJOR 207 #define SERIAL_IMX_MAJOR 207
#define MINOR_START 16 #define MINOR_START 16
#define DEV_NAME "ttymxc" #define DEV_NAME "ttymxc"
#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
#endif
/* /*
* This determines how often we check the modem status signals * This determines how often we check the modem status signals
...@@ -706,11 +682,11 @@ static int imx_startup(struct uart_port *port) ...@@ -706,11 +682,11 @@ static int imx_startup(struct uart_port *port)
} }
} }
#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3 if (!cpu_is_mx1()) {
temp = readl(sport->port.membase + UCR3); temp = readl(sport->port.membase + UCR3);
temp |= UCR3_RXDMUXSEL; temp |= MX2_UCR3_RXDMUXSEL;
writel(temp, sport->port.membase + UCR3); writel(temp, sport->port.membase + UCR3);
#endif }
if (USE_IRDA(sport)) { if (USE_IRDA(sport)) {
temp = readl(sport->port.membase + UCR4); temp = readl(sport->port.membase + UCR4);
...@@ -942,9 +918,9 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, ...@@ -942,9 +918,9 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
writel(num, sport->port.membase + UBIR); writel(num, sport->port.membase + UBIR);
writel(denom, sport->port.membase + UBMR); writel(denom, sport->port.membase + UBMR);
#ifdef ONEMS if (!cpu_is_mx1())
writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS); writel(sport->port.uartclk / div / 1000,
#endif sport->port.membase + MX2_ONEMS);
writel(old_ucr1, sport->port.membase + UCR1); writel(old_ucr1, sport->port.membase + UCR1);
...@@ -1074,17 +1050,20 @@ static void ...@@ -1074,17 +1050,20 @@ static void
imx_console_write(struct console *co, const char *s, unsigned int count) imx_console_write(struct console *co, const char *s, unsigned int count)
{ {
struct imx_port *sport = imx_ports[co->index]; struct imx_port *sport = imx_ports[co->index];
unsigned int old_ucr1, old_ucr2; unsigned int old_ucr1, old_ucr2, ucr1;
/* /*
* First, save UCR1/2 and then disable interrupts * First, save UCR1/2 and then disable interrupts
*/ */
old_ucr1 = readl(sport->port.membase + UCR1); ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
old_ucr2 = readl(sport->port.membase + UCR2); old_ucr2 = readl(sport->port.membase + UCR2);
writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) & if (cpu_is_mx1())
~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), ucr1 |= MX1_UCR1_UARTCLKEN;
sport->port.membase + UCR1); ucr1 |= UCR1_UARTEN;
ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
writel(ucr1, sport->port.membase + UCR1);
writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2); writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
......
drivers/video/imxfb.c
View file @ 590a94d9
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <linux/math64.h> #include <linux/math64.h>
#include <mach/imxfb.h> #include <mach/imxfb.h>
#include <mach/hardware.h>
/* /*
* Complain if VAR is out of range. * Complain if VAR is out of range.
...@@ -129,6 +130,10 @@ ...@@ -129,6 +130,10 @@
#define LCDISR_EOF (1<<1) #define LCDISR_EOF (1<<1)
#define LCDISR_BOF (1<<0) #define LCDISR_BOF (1<<0)
/* Used fb-mode. Can be set on kernel command line, therefore file-static. */
static const char *fb_mode;
/* /*
* These are the bitfields for each * These are the bitfields for each
* display depth that we support. * display depth that we support.
...@@ -145,10 +150,6 @@ struct imxfb_info { ...@@ -145,10 +150,6 @@ struct imxfb_info {
void __iomem *regs; void __iomem *regs;
struct clk *clk; struct clk *clk;
u_int max_bpp;
u_int max_xres;
u_int max_yres;
/* /*
* These are the addresses we mapped * These are the addresses we mapped
* the framebuffer memory region to. * the framebuffer memory region to.
...@@ -172,6 +173,9 @@ struct imxfb_info { ...@@ -172,6 +173,9 @@ struct imxfb_info {
cmap_static:1, cmap_static:1,
unused:30; unused:30;
struct imx_fb_videomode *mode;
int num_modes;
void (*lcd_power)(int); void (*lcd_power)(int);
void (*backlight_power)(int); void (*backlight_power)(int);
}; };
...@@ -298,6 +302,18 @@ static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, ...@@ -298,6 +302,18 @@ static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
return ret; return ret;
} }
static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
{
struct imx_fb_videomode *m;
int i;
for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
if (!strcmp(m->mode.name, fb_mode))
return m;
}
return NULL;
}
/* /*
* imxfb_check_var(): * imxfb_check_var():
* Round up in the following order: bits_per_pixel, xres, * Round up in the following order: bits_per_pixel, xres,
...@@ -308,35 +324,81 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ...@@ -308,35 +324,81 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{ {
struct imxfb_info *fbi = info->par; struct imxfb_info *fbi = info->par;
struct imxfb_rgb *rgb; struct imxfb_rgb *rgb;
const struct imx_fb_videomode *imxfb_mode;
unsigned long lcd_clk;
unsigned long long tmp;
u32 pcr = 0;
if (var->xres < MIN_XRES) if (var->xres < MIN_XRES)
var->xres = MIN_XRES; var->xres = MIN_XRES;
if (var->yres < MIN_YRES) if (var->yres < MIN_YRES)
var->yres = MIN_YRES; var->yres = MIN_YRES;
if (var->xres > fbi->max_xres)
var->xres = fbi->max_xres; imxfb_mode = imxfb_find_mode(fbi);
if (var->yres > fbi->max_yres) if (!imxfb_mode)
var->yres = fbi->max_yres; return -EINVAL;
var->xres = imxfb_mode->mode.xres;
var->yres = imxfb_mode->mode.yres;
var->bits_per_pixel = imxfb_mode->bpp;
var->pixclock = imxfb_mode->mode.pixclock;
var->hsync_len = imxfb_mode->mode.hsync_len;
var->left_margin = imxfb_mode->mode.left_margin;
var->right_margin = imxfb_mode->mode.right_margin;
var->vsync_len = imxfb_mode->mode.vsync_len;
var->upper_margin = imxfb_mode->mode.upper_margin;
var->lower_margin = imxfb_mode->mode.lower_margin;
var->sync = imxfb_mode->mode.sync;
var->xres_virtual = max(var->xres_virtual, var->xres); var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres_virtual = max(var->yres_virtual, var->yres); var->yres_virtual = max(var->yres_virtual, var->yres);
pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
lcd_clk = clk_get_rate(fbi->clk);
tmp = var->pixclock * (unsigned long long)lcd_clk;
do_div(tmp, 1000000);
if (do_div(tmp, 1000000) > 500000)
tmp++;
pcr = (unsigned int)tmp;
if (--pcr > 0x3F) {
pcr = 0x3F;
printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
lcd_clk / pcr);
}
switch (var->bits_per_pixel) { switch (var->bits_per_pixel) {
case 32: case 32:
pcr |= PCR_BPIX_18;
rgb = &def_rgb_18; rgb = &def_rgb_18;
break; break;
case 16: case 16:
default: default:
if (fbi->pcr & PCR_TFT) if (cpu_is_mx1())
pcr |= PCR_BPIX_12;
else
pcr |= PCR_BPIX_16;
if (imxfb_mode->pcr & PCR_TFT)
rgb = &def_rgb_16_tft; rgb = &def_rgb_16_tft;
else else
rgb = &def_rgb_16_stn; rgb = &def_rgb_16_stn;
break; break;
case 8: case 8:
pcr |= PCR_BPIX_8;
rgb = &def_rgb_8; rgb = &def_rgb_8;
break; break;
} }
/* add sync polarities */
pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25));
fbi->pcr = pcr;
/* /*
* Copy the RGB parameters for this display * Copy the RGB parameters for this display
* from the machine specific parameters. * from the machine specific parameters.
...@@ -393,10 +455,6 @@ static void imxfb_enable_controller(struct imxfb_info *fbi) ...@@ -393,10 +455,6 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
writel(fbi->screen_dma, fbi->regs + LCDC_SSA); writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
/* physical screen start address */
writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
fbi->regs + LCDC_VPW);
/* panning offset 0 (0 pixel offset) */ /* panning offset 0 (0 pixel offset) */
writel(0x00000000, fbi->regs + LCDC_POS); writel(0x00000000, fbi->regs + LCDC_POS);
...@@ -468,8 +526,6 @@ static struct fb_ops imxfb_ops = { ...@@ -468,8 +526,6 @@ static struct fb_ops imxfb_ops = {
static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info)
{ {
struct imxfb_info *fbi = info->par; struct imxfb_info *fbi = info->par;
unsigned int pcr, lcd_clk;
unsigned long long tmp;
pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
var->xres, var->hsync_len, var->xres, var->hsync_len,
...@@ -505,6 +561,10 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf ...@@ -505,6 +561,10 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
info->fix.id, var->lower_margin); info->fix.id, var->lower_margin);
#endif #endif
/* physical screen start address */
writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4),
fbi->regs + LCDC_VPW);
writel(HCR_H_WIDTH(var->hsync_len - 1) | writel(HCR_H_WIDTH(var->hsync_len - 1) |
HCR_H_WAIT_1(var->right_margin - 1) | HCR_H_WAIT_1(var->right_margin - 1) |
HCR_H_WAIT_2(var->left_margin - 3), HCR_H_WAIT_2(var->left_margin - 3),
...@@ -518,22 +578,7 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf ...@@ -518,22 +578,7 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres), writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
fbi->regs + LCDC_SIZE); fbi->regs + LCDC_SIZE);
lcd_clk = clk_get_rate(fbi->clk); writel(fbi->pcr, fbi->regs + LCDC_PCR);
tmp = var->pixclock * (unsigned long long)lcd_clk;
do_div(tmp, 1000000);
if (do_div(tmp, 1000000) > 500000)
tmp++;
pcr = (unsigned int)tmp;
if (--pcr > 0x3F) {
pcr = 0x3F;
printk(KERN_WARNING "Must limit pixel clock to %uHz\n",
lcd_clk / pcr);
}
/* add sync polarities */
pcr |= fbi->pcr & ~0x3F;
writel(pcr, fbi->regs + LCDC_PCR);
writel(fbi->pwmr, fbi->regs + LCDC_PWMR); writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
writel(fbi->dmacr, fbi->regs + LCDC_DMACR); writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
...@@ -575,6 +620,8 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev) ...@@ -575,6 +620,8 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
struct imx_fb_platform_data *pdata = pdev->dev.platform_data; struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
struct fb_info *info = dev_get_drvdata(&pdev->dev); struct fb_info *info = dev_get_drvdata(&pdev->dev);
struct imxfb_info *fbi = info->par; struct imxfb_info *fbi = info->par;
struct imx_fb_videomode *m;
int i;
pr_debug("%s\n",__func__); pr_debug("%s\n",__func__);
...@@ -603,35 +650,18 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev) ...@@ -603,35 +650,18 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
info->fbops = &imxfb_ops; info->fbops = &imxfb_ops;
info->flags = FBINFO_FLAG_DEFAULT | info->flags = FBINFO_FLAG_DEFAULT |
FBINFO_READS_FAST; FBINFO_READS_FAST;
fbi->max_xres = pdata->xres;
info->var.xres = pdata->xres;
info->var.xres_virtual = pdata->xres;
fbi->max_yres = pdata->yres;
info->var.yres = pdata->yres;
info->var.yres_virtual = pdata->yres;
fbi->max_bpp = pdata->bpp;
info->var.bits_per_pixel = pdata->bpp;
info->var.nonstd = pdata->nonstd;
info->var.pixclock = pdata->pixclock;
info->var.hsync_len = pdata->hsync_len;
info->var.left_margin = pdata->left_margin;
info->var.right_margin = pdata->right_margin;
info->var.vsync_len = pdata->vsync_len;
info->var.upper_margin = pdata->upper_margin;
info->var.lower_margin = pdata->lower_margin;
info->var.sync = pdata->sync;
info->var.grayscale = pdata->cmap_greyscale; info->var.grayscale = pdata->cmap_greyscale;
fbi->cmap_inverse = pdata->cmap_inverse; fbi->cmap_inverse = pdata->cmap_inverse;
fbi->cmap_static = pdata->cmap_static; fbi->cmap_static = pdata->cmap_static;
fbi->pcr = pdata->pcr;
fbi->lscr1 = pdata->lscr1; fbi->lscr1 = pdata->lscr1;
fbi->dmacr = pdata->dmacr; fbi->dmacr = pdata->dmacr;
fbi->pwmr = pdata->pwmr; fbi->pwmr = pdata->pwmr;
fbi->lcd_power = pdata->lcd_power; fbi->lcd_power = pdata->lcd_power;
fbi->backlight_power = pdata->backlight_power; fbi->backlight_power = pdata->backlight_power;
info->fix.smem_len = fbi->max_xres * fbi->max_yres *
fbi->max_bpp / 8; for (i = 0, m = &pdata->mode[0]; i < pdata->num_modes; i++, m++)
info->fix.smem_len = max_t(size_t, info->fix.smem_len,
m->mode.xres * m->mode.yres * m->bpp / 8);
return 0; return 0;
} }
...@@ -642,9 +672,9 @@ static int __init imxfb_probe(struct platform_device *pdev) ...@@ -642,9 +672,9 @@ static int __init imxfb_probe(struct platform_device *pdev)
struct fb_info *info; struct fb_info *info;
struct imx_fb_platform_data *pdata; struct imx_fb_platform_data *pdata;
struct resource *res; struct resource *res;
int ret; int ret, i;
printk("i.MX Framebuffer driver\n"); dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) if (!res)
...@@ -662,6 +692,9 @@ static int __init imxfb_probe(struct platform_device *pdev) ...@@ -662,6 +692,9 @@ static int __init imxfb_probe(struct platform_device *pdev)
fbi = info->par; fbi = info->par;
if (!fb_mode)
fb_mode = pdata->mode[0].mode.name;
platform_set_drvdata(pdev, info); platform_set_drvdata(pdev, info);
ret = imxfb_init_fbinfo(pdev); ret = imxfb_init_fbinfo(pdev);
...@@ -684,7 +717,7 @@ static int __init imxfb_probe(struct platform_device *pdev) ...@@ -684,7 +717,7 @@ static int __init imxfb_probe(struct platform_device *pdev)
fbi->regs = ioremap(res->start, resource_size(res)); fbi->regs = ioremap(res->start, resource_size(res));
if (fbi->regs == NULL) { if (fbi->regs == NULL) {
printk(KERN_ERR"Cannot map frame buffer registers\n"); dev_err(&pdev->dev, "Cannot map frame buffer registers\n");
goto failed_ioremap; goto failed_ioremap;
} }
...@@ -719,6 +752,13 @@ static int __init imxfb_probe(struct platform_device *pdev) ...@@ -719,6 +752,13 @@ static int __init imxfb_probe(struct platform_device *pdev)
goto failed_platform_init; goto failed_platform_init;
} }
fbi->mode = pdata->mode;
fbi->num_modes = pdata->num_modes;
INIT_LIST_HEAD(&info->modelist);
for (i = 0; i < pdata->num_modes; i++)
fb_add_videomode(&pdata->mode[i].mode, &info->modelist);
/* /*
* This makes sure that our colour bitfield * This makes sure that our colour bitfield
* descriptors are correctly initialised. * descriptors are correctly initialised.
...@@ -754,7 +794,7 @@ static int __init imxfb_probe(struct platform_device *pdev) ...@@ -754,7 +794,7 @@ static int __init imxfb_probe(struct platform_device *pdev)
failed_getclock: failed_getclock:
iounmap(fbi->regs); iounmap(fbi->regs);
failed_ioremap: failed_ioremap:
release_mem_region(res->start, res->end - res->start); release_mem_region(res->start, resource_size(res));
failed_req: failed_req:
kfree(info->pseudo_palette); kfree(info->pseudo_palette);
failed_init: failed_init:
...@@ -785,7 +825,7 @@ static int __devexit imxfb_remove(struct platform_device *pdev) ...@@ -785,7 +825,7 @@ static int __devexit imxfb_remove(struct platform_device *pdev)
framebuffer_release(info); framebuffer_release(info);
iounmap(fbi->regs); iounmap(fbi->regs);
release_mem_region(res->start, res->end - res->start + 1); release_mem_region(res->start, resource_size(res));
clk_disable(fbi->clk); clk_disable(fbi->clk);
clk_put(fbi->clk); clk_put(fbi->clk);
...@@ -811,8 +851,34 @@ static struct platform_driver imxfb_driver = { ...@@ -811,8 +851,34 @@ static struct platform_driver imxfb_driver = {
}, },
}; };
static int imxfb_setup(void)
{
#ifndef MODULE
char *opt, *options = NULL;
if (fb_get_options("imxfb", &options))
return -ENODEV;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
else
fb_mode = opt;
}
#endif
return 0;
}
int __init imxfb_init(void) int __init imxfb_init(void)
{ {
int ret = imxfb_setup();
if (ret < 0)
return ret;
return platform_driver_probe(&imxfb_driver, imxfb_probe); return platform_driver_probe(&imxfb_driver, imxfb_probe);
} }
......
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