clocksource/drivers/tegra: Fix IO endianness

Support big-endian kernel by using endian-aware register access
functions.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: ben.dooks@codethink.co.uk
Cc: hdegoede@redhat.com
Cc: laurent.pinchart+renesas@ideasonboard.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: maxime.ripard@free-electrons.com
Cc: viresh.kumar@linaro.org
Link: http://lkml.kernel.org/r/1427746633-9137-9-git-send-email-daniel.lezcano@linaro.orgSigned-off-by: Ingo Molnar <mingo@kernel.org>

drivers/clocksource/tegra20_timer.c

@@ -57,9 +57,9 @@ static u64 persistent_ms, last_persistent_ms;
 static struct delay_timer tegra_delay_timer;
 
 #define timer_writel(value, reg) \
-	__raw_writel(value, timer_reg_base + (reg))
+	writel_relaxed(value, timer_reg_base + (reg))
 #define timer_readl(reg) \
-	__raw_readl(timer_reg_base + (reg))
+	readl_relaxed(timer_reg_base + (reg))
 
 static int tegra_timer_set_next_event(unsigned long cycles,
 					 struct clock_event_device *evt)