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Commit 598f22e1 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Greg Kroah-Hartman
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USB: m66592-udc: fixes some problems 

This patch incorporates some updates from the review of the
Renesas m66592-udc driver.  Updates include:

 - Fix some locking bugs; and add a few sparse annotations
 - Don't #define __iomem !
 - Lots of whitespace fixes (most of the patch by volume)
 - Some #include file trimmage
 - Other checkpatch.pl and sparse updates
 - Alphabetized and slightly-more-informative Kconfig
 - Don't use the ID which was assigned to the amd5536udc driver.
 - Remove pointless suspend/resume methods updating obsolete field.
 - Some section fixups
 - Fix some leak bugs
 - Fix byteswapping
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: default avatarYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent d8fbba2f
Expand all Show whitespace changes
Inline Side-by-side
Showing with 450 additions and 453 deletions
drivers/usb/gadget/Kconfig
View file @ 598f22e1
...@@ -177,6 +177,24 @@ config USB_PXA2XX_SMALL ...@@ -177,6 +177,24 @@ config USB_PXA2XX_SMALL
default y if USB_ETH default y if USB_ETH
default y if USB_G_SERIAL default y if USB_G_SERIAL
config USB_GADGET_M66592
boolean "Renesas M66592 USB Peripheral Controller"
select USB_GADGET_DUALSPEED
help
M66592 is a discrete USB peripheral controller chip that
supports both full and high speed USB 2.0 data transfers.
It has seven configurable endpoints, and endpoint zero.
Say "y" to link the driver statically, or "m" to build a
dynamically linked module called "m66592_udc" and force all
gadget drivers to also be dynamically linked.
config USB_M66592
tristate
depends on USB_GADGET_M66592
default USB_GADGET
select USB_GADGET_SELECTED
config USB_GADGET_GOKU config USB_GADGET_GOKU
boolean "Toshiba TC86C001 'Goku-S'" boolean "Toshiba TC86C001 'Goku-S'"
depends on PCI depends on PCI
...@@ -282,24 +300,6 @@ config USB_AT91 ...@@ -282,24 +300,6 @@ config USB_AT91
depends on USB_GADGET_AT91 depends on USB_GADGET_AT91
default USB_GADGET default USB_GADGET
config USB_GADGET_M66592
boolean "M66592 driver"
select USB_GADGET_DUALSPEED
help
M66592 is a USB 2.0 peripheral controller.
It has seven configurable endpoints, and endpoint zero.
Say "y" to link the driver statically, or "m" to build a
dynamically linked module called "m66592_udc" and force all
gadget drivers to also be dynamically linked.
config USB_M66592
tristate
depends on USB_GADGET_M66592
default USB_GADGET
select USB_GADGET_SELECTED
config USB_GADGET_DUMMY_HCD config USB_GADGET_DUMMY_HCD
boolean "Dummy HCD (DEVELOPMENT)" boolean "Dummy HCD (DEVELOPMENT)"
depends on (USB=y || (USB=m && USB_GADGET=m)) && EXPERIMENTAL depends on (USB=y || (USB=m && USB_GADGET=m)) && EXPERIMENTAL
......
drivers/usb/gadget/gadget_chips.h
View file @ 598f22e1
...@@ -211,6 +211,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) ...@@ -211,6 +211,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
else if (gadget_is_amd5536udc(gadget)) else if (gadget_is_amd5536udc(gadget))
return 0x20; return 0x20;
else if (gadget_is_m66592(gadget)) else if (gadget_is_m66592(gadget))
return 0x20; return 0x21;
return -ENOENT; return -ENOENT;
} }
drivers/usb/gadget/m66592-udc.c
View file @ 598f22e1
This diff is collapsed.
drivers/usb/gadget/m66592-udc.h
View file @ 598f22e1
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define M66592_RCKE 0x1000 /* b12: Register clock enable */ #define M66592_RCKE 0x1000 /* b12: Register clock enable */
#define M66592_PLLC 0x0800 /* b11: PLL control */ #define M66592_PLLC 0x0800 /* b11: PLL control */
#define M66592_SCKE 0x0400 /* b10: USB clock enable */ #define M66592_SCKE 0x0400 /* b10: USB clock enable */
#define M66592_ATCKM 0x0100 /* b8: Automatic supply functional enable */ #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
#define M66592_HSE 0x0080 /* b7: Hi-speed enable */ #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
#define M66592_DCFM 0x0040 /* b6: Controller function select */ #define M66592_DCFM 0x0040 /* b6: Controller function select */
#define M66592_DMRPD 0x0020 /* b5: D- pull down control */ #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
...@@ -103,12 +103,12 @@ ...@@ -103,12 +103,12 @@
#define M66592_REW 0x4000 /* b14: Buffer rewind */ #define M66592_REW 0x4000 /* b14: Buffer rewind */
#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
#define M66592_DREQE 0x1000 /* b12: DREQ output enable */ #define M66592_DREQE 0x1000 /* b12: DREQ output enable */
#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO access */ #define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */
#define M66592_MBW_8 0x0000 /* 8bit */ #define M66592_MBW_8 0x0000 /* 8bit */
#define M66592_MBW_16 0x0400 /* 16bit */ #define M66592_MBW_16 0x0400 /* 16bit */
#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
#define M66592_DEZPM 0x0080 /* b7: Zero-length packet additional mode */ #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
#define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */ #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */
#define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */ #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
...@@ -134,7 +134,7 @@ ...@@ -134,7 +134,7 @@
#define M66592_RSME 0x4000 /* b14: Resume interrupt */ #define M66592_RSME 0x4000 /* b14: Resume interrupt */
#define M66592_SOFE 0x2000 /* b13: Frame update interrupt */ #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */
#define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */ #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */
#define M66592_CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */
#define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */ #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */
#define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */ #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */
#define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */ #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */
...@@ -142,8 +142,8 @@ ...@@ -142,8 +142,8 @@
#define M66592_SADR 0x0040 /* b6: Set address executed interrupt */ #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */
#define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */ #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */
#define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */ #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */
#define M66592_WDST 0x0008 /* b3: Control write data stage completed interrupt */ #define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */
#define M66592_RDST 0x0004 /* b2: Control read data stage completed interrupt */ #define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */
#define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */ #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */
#define M66592_SERR 0x0001 /* b0: Sequence error interrupt */ #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */
...@@ -199,8 +199,8 @@ ...@@ -199,8 +199,8 @@
#define M66592_VBINT 0x8000 /* b15: VBUS interrupt */ #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */
#define M66592_RESM 0x4000 /* b14: Resume interrupt */ #define M66592_RESM 0x4000 /* b14: Resume interrupt */
#define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */ #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */
#define M66592_DVST 0x1000 /* b12: Device state transition interrupt */ #define M66592_DVST 0x1000 /* b12: Device state transition */
#define M66592_CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ #define M66592_CTRT 0x0800 /* b11: Control stage transition */
#define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */ #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */
#define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */ #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */
#define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */ #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */
...@@ -219,7 +219,7 @@ ...@@ -219,7 +219,7 @@
#define M66592_VALID 0x0008 /* b3: Setup packet detected flag */ #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */
#define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */ #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
#define M66592_CS_SQER 0x0006 /* Sequence error */ #define M66592_CS_SQER 0x0006 /* Sequence error */
#define M66592_CS_WRND 0x0005 /* Control write nodata status stage */ #define M66592_CS_WRND 0x0005 /* Control write nodata status */
#define M66592_CS_WRSS 0x0004 /* Control write status stage */ #define M66592_CS_WRSS 0x0004 /* Control write status stage */
#define M66592_CS_WRDS 0x0003 /* Control write data stage */ #define M66592_CS_WRDS 0x0003 /* Control write data stage */
#define M66592_CS_RDSS 0x0002 /* Control read status stage */ #define M66592_CS_RDSS 0x0002 /* Control read status stage */
...@@ -265,7 +265,7 @@ ...@@ -265,7 +265,7 @@
#define M66592_SET_INTERFACE 0x0B00 #define M66592_SET_INTERFACE 0x0B00
#define M66592_SYNCH_FRAME 0x0C00 #define M66592_SYNCH_FRAME 0x0C00
#define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */ #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
#define M66592_bmRequestTypeDir 0x0080 /* b7 : Data transfer direction */ #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */
#define M66592_HOST_TO_DEVICE 0x0000 #define M66592_HOST_TO_DEVICE 0x0000
#define M66592_DEVICE_TO_HOST 0x0080 #define M66592_DEVICE_TO_HOST 0x0080
#define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */ #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
...@@ -300,7 +300,7 @@ ...@@ -300,7 +300,7 @@
#define M66592_USBINDEX 0x58 #define M66592_USBINDEX 0x58
#define M66592_wIndex 0xFFFF /* b15-0: wIndex */ #define M66592_wIndex 0xFFFF /* b15-0: wIndex */
#define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode Selectors */ #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */
#define M66592_TEST_J 0x0100 /* Test_J */ #define M66592_TEST_J 0x0100 /* Test_J */
#define M66592_TEST_K 0x0200 /* Test_K */ #define M66592_TEST_K 0x0200 /* Test_K */
#define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */ #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */
...@@ -308,7 +308,7 @@ ...@@ -308,7 +308,7 @@
#define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */ #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */
#define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */ #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */
#define M66592_TEST_Reserved 0x4000 /* Reserved */ #define M66592_TEST_Reserved 0x4000 /* Reserved */
#define M66592_TEST_VSTModes 0xC000 /* Vendor-specific test modes */ #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */
#define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */ #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */
#define M66592_EP_DIR_IN 0x0080 #define M66592_EP_DIR_IN 0x0080
#define M66592_EP_DIR_OUT 0x0000 #define M66592_EP_DIR_OUT 0x0000
...@@ -317,7 +317,7 @@ ...@@ -317,7 +317,7 @@
#define M66592_wLength 0xFFFF /* b15-0: wLength */ #define M66592_wLength 0xFFFF /* b15-0: wLength */
#define M66592_DCPCFG 0x5C #define M66592_DCPCFG 0x5C
#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */ #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
#define M66592_DIR 0x0010 /* b4: Control transfer DIR select */ #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */
#define M66592_DCPMAXP 0x5E #define M66592_DCPMAXP 0x5E
...@@ -326,7 +326,7 @@ ...@@ -326,7 +326,7 @@
#define M66592_DEVICE_1 0x4000 /* Device address 1 */ #define M66592_DEVICE_1 0x4000 /* Device address 1 */
#define M66592_DEVICE_2 0x8000 /* Device address 2 */ #define M66592_DEVICE_2 0x8000 /* Device address 2 */
#define M66592_DEVICE_3 0xC000 /* Device address 3 */ #define M66592_DEVICE_3 0xC000 /* Device address 3 */
#define M66592_MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */
#define M66592_DCPCTR 0x60 #define M66592_DCPCTR 0x60
#define M66592_BSTS 0x8000 /* b15: Buffer status */ #define M66592_BSTS 0x8000 /* b15: Buffer status */
...@@ -334,7 +334,7 @@ ...@@ -334,7 +334,7 @@
#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
#define M66592_CCPL 0x0004 /* b2: Enable control transfer complete */ #define M66592_CCPL 0x0004 /* b2: control transfer complete */
#define M66592_PID 0x0003 /* b1-0: Response PID */ #define M66592_PID 0x0003 /* b1-0: Response PID */
#define M66592_PID_STALL 0x0002 /* STALL */ #define M66592_PID_STALL 0x0002 /* STALL */
#define M66592_PID_BUF 0x0001 /* BUF */ #define M66592_PID_BUF 0x0001 /* BUF */
...@@ -356,9 +356,9 @@ ...@@ -356,9 +356,9 @@
#define M66592_ISO 0xC000 /* Isochronous */ #define M66592_ISO 0xC000 /* Isochronous */
#define M66592_INT 0x8000 /* Interrupt */ #define M66592_INT 0x8000 /* Interrupt */
#define M66592_BULK 0x4000 /* Bulk */ #define M66592_BULK 0x4000 /* Bulk */
#define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */
#define M66592_DBLB 0x0200 /* b9: Double buffer mode select */ #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */
#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */ #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
#define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */ #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */
#define M66592_DIR 0x0010 /* b4: Transfer direction select */ #define M66592_DIR 0x0010 /* b4: Transfer direction select */
#define M66592_DIR_H_OUT 0x0010 /* HOST OUT */ #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */
...@@ -391,8 +391,8 @@ ...@@ -391,8 +391,8 @@
#define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */ #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
#define M66592_PIPEPERI 0x6C #define M66592_PIPEPERI 0x6C
#define M66592_IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */
#define M66592_IITV 0x0007 /* b2-0: Isochronous interval */ #define M66592_IITV 0x0007 /* b2-0: ISO interval */
#define M66592_PIPE1CTR 0x70 #define M66592_PIPE1CTR 0x70
#define M66592_PIPE2CTR 0x72 #define M66592_PIPE2CTR 0x72
...@@ -402,7 +402,7 @@ ...@@ -402,7 +402,7 @@
#define M66592_PIPE6CTR 0x7A #define M66592_PIPE6CTR 0x7A
#define M66592_PIPE7CTR 0x7C #define M66592_PIPE7CTR 0x7C
#define M66592_BSTS 0x8000 /* b15: Buffer status */ #define M66592_BSTS 0x8000 /* b15: Buffer status */
#define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */
#define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */ #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */
#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
...@@ -412,8 +412,6 @@ ...@@ -412,8 +412,6 @@
#define M66592_INVALID_REG 0x7E #define M66592_INVALID_REG 0x7E
#define __iomem
#define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2) #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
#define M66592_MAX_SAMPLING 10 #define M66592_MAX_SAMPLING 10
...@@ -477,7 +475,7 @@ struct m66592 { ...@@ -477,7 +475,7 @@ struct m66592 {
struct m66592_ep *epaddr2ep[16]; struct m66592_ep *epaddr2ep[16];
struct usb_request *ep0_req; /* for internal request */ struct usb_request *ep0_req; /* for internal request */
u16 *ep0_buf; /* for internal request */ u16 ep0_data; /* for internal request */
struct timer_list timer; struct timer_list timer;
......
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