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Commit 5b8acdc5 authored by Hans Verkuil's avatar Hans Verkuil Committed by Mauro Carvalho Chehab
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[media] cx231xx-417: checkpatch cleanups 

Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 5aa95991
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Showing with 360 additions and 372 deletions
drivers/media/usb/cx231xx/cx231xx-417.c
View file @ 5b8acdc5
...@@ -38,7 +38,6 @@ ...@@ -38,7 +38,6 @@
#include <linux/usb.h> #include <linux/usb.h>
#include "cx231xx.h" #include "cx231xx.h"
/*#include "cx23885-ioctl.h"*/
#define CX231xx_FIRM_IMAGE_SIZE 376836 #define CX231xx_FIRM_IMAGE_SIZE 376836
#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw" #define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
...@@ -75,9 +74,11 @@ ...@@ -75,9 +74,11 @@
static unsigned int mpegbufs = 8; static unsigned int mpegbufs = 8;
module_param(mpegbufs, int, 0644); module_param(mpegbufs, int, 0644);
MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32"); MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
static unsigned int mpeglines = 128; static unsigned int mpeglines = 128;
module_param(mpeglines, int, 0644); module_param(mpeglines, int, 0644);
MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32"); MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
static unsigned int mpeglinesize = 512; static unsigned int mpeglinesize = 512;
module_param(mpeglinesize, int, 0644); module_param(mpeglinesize, int, 0644);
MODULE_PARM_DESC(mpeglinesize, MODULE_PARM_DESC(mpeglinesize,
...@@ -86,10 +87,10 @@ MODULE_PARM_DESC(mpeglinesize, ...@@ -86,10 +87,10 @@ MODULE_PARM_DESC(mpeglinesize,
static unsigned int v4l_debug = 1; static unsigned int v4l_debug = 1;
module_param(v4l_debug, int, 0644); module_param(v4l_debug, int, 0644);
MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages"); MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
struct cx231xx_dmaqueue *dma_qq;
#define dprintk(level, fmt, arg...)\ #define dprintk(level, fmt, arg...)\
do { if (v4l_debug >= level) \ do { if (v4l_debug >= level) \
printk(KERN_INFO "%s: " fmt, \ pr_info("%s: " fmt, \
(dev) ? dev->name : "cx231xx[?]", ## arg); \ (dev) ? dev->name : "cx231xx[?]", ## arg); \
} while (0) } while (0)
...@@ -131,11 +132,13 @@ static struct cx231xx_tvnorm cx231xx_tvnorms[] = { ...@@ -131,11 +132,13 @@ static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
}; };
/* ------------------------------------------------------------------ */ /* ------------------------------------------------------------------ */
enum cx231xx_capture_type { enum cx231xx_capture_type {
CX231xx_MPEG_CAPTURE, CX231xx_MPEG_CAPTURE,
CX231xx_RAW_CAPTURE, CX231xx_RAW_CAPTURE,
CX231xx_RAW_PASSTHRU_CAPTURE CX231xx_RAW_PASSTHRU_CAPTURE
}; };
enum cx231xx_capture_bits { enum cx231xx_capture_bits {
CX231xx_RAW_BITS_NONE = 0x00, CX231xx_RAW_BITS_NONE = 0x00,
CX231xx_RAW_BITS_YUV_CAPTURE = 0x01, CX231xx_RAW_BITS_YUV_CAPTURE = 0x01,
...@@ -144,33 +147,40 @@ enum cx231xx_capture_bits { ...@@ -144,33 +147,40 @@ enum cx231xx_capture_bits {
CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08, CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10 CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10
}; };
enum cx231xx_capture_end { enum cx231xx_capture_end {
CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */ CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
CX231xx_END_NOW, /* stop immediately, no irq */ CX231xx_END_NOW, /* stop immediately, no irq */
}; };
enum cx231xx_framerate { enum cx231xx_framerate {
CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */ CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */ CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */
}; };
enum cx231xx_stream_port { enum cx231xx_stream_port {
CX231xx_OUTPUT_PORT_MEMORY, CX231xx_OUTPUT_PORT_MEMORY,
CX231xx_OUTPUT_PORT_STREAMING, CX231xx_OUTPUT_PORT_STREAMING,
CX231xx_OUTPUT_PORT_SERIAL CX231xx_OUTPUT_PORT_SERIAL
}; };
enum cx231xx_data_xfer_status { enum cx231xx_data_xfer_status {
CX231xx_MORE_BUFFERS_FOLLOW, CX231xx_MORE_BUFFERS_FOLLOW,
CX231xx_LAST_BUFFER, CX231xx_LAST_BUFFER,
}; };
enum cx231xx_picture_mask { enum cx231xx_picture_mask {
CX231xx_PICTURE_MASK_NONE, CX231xx_PICTURE_MASK_NONE,
CX231xx_PICTURE_MASK_I_FRAMES, CX231xx_PICTURE_MASK_I_FRAMES,
CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3, CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7, CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
}; };
enum cx231xx_vbi_mode_bits { enum cx231xx_vbi_mode_bits {
CX231xx_VBI_BITS_SLICED, CX231xx_VBI_BITS_SLICED,
CX231xx_VBI_BITS_RAW, CX231xx_VBI_BITS_RAW,
}; };
enum cx231xx_vbi_insertion_bits { enum cx231xx_vbi_insertion_bits {
CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA, CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1, CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
...@@ -178,56 +188,69 @@ enum cx231xx_vbi_insertion_bits { ...@@ -178,56 +188,69 @@ enum cx231xx_vbi_insertion_bits {
CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1, CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1, CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
}; };
enum cx231xx_dma_unit { enum cx231xx_dma_unit {
CX231xx_DMA_BYTES, CX231xx_DMA_BYTES,
CX231xx_DMA_FRAMES, CX231xx_DMA_FRAMES,
}; };
enum cx231xx_dma_transfer_status_bits { enum cx231xx_dma_transfer_status_bits {
CX231xx_DMA_TRANSFER_BITS_DONE = 0x01, CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04, CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10, CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
}; };
enum cx231xx_pause { enum cx231xx_pause {
CX231xx_PAUSE_ENCODING, CX231xx_PAUSE_ENCODING,
CX231xx_RESUME_ENCODING, CX231xx_RESUME_ENCODING,
}; };
enum cx231xx_copyright { enum cx231xx_copyright {
CX231xx_COPYRIGHT_OFF, CX231xx_COPYRIGHT_OFF,
CX231xx_COPYRIGHT_ON, CX231xx_COPYRIGHT_ON,
}; };
enum cx231xx_notification_type { enum cx231xx_notification_type {
CX231xx_NOTIFICATION_REFRESH, CX231xx_NOTIFICATION_REFRESH,
}; };
enum cx231xx_notification_status { enum cx231xx_notification_status {
CX231xx_NOTIFICATION_OFF, CX231xx_NOTIFICATION_OFF,
CX231xx_NOTIFICATION_ON, CX231xx_NOTIFICATION_ON,
}; };
enum cx231xx_notification_mailbox { enum cx231xx_notification_mailbox {
CX231xx_NOTIFICATION_NO_MAILBOX = -1, CX231xx_NOTIFICATION_NO_MAILBOX = -1,
}; };
enum cx231xx_field1_lines { enum cx231xx_field1_lines {
CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */ CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */ CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */ CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
}; };
enum cx231xx_field2_lines { enum cx231xx_field2_lines {
CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */ CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */ CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */ CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
}; };
enum cx231xx_custom_data_type { enum cx231xx_custom_data_type {
CX231xx_CUSTOM_EXTENSION_USR_DATA, CX231xx_CUSTOM_EXTENSION_USR_DATA,
CX231xx_CUSTOM_PRIVATE_PACKET, CX231xx_CUSTOM_PRIVATE_PACKET,
}; };
enum cx231xx_mute { enum cx231xx_mute {
CX231xx_UNMUTE, CX231xx_UNMUTE,
CX231xx_MUTE, CX231xx_MUTE,
}; };
enum cx231xx_mute_video_mask { enum cx231xx_mute_video_mask {
CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00, CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000, CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000, CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
}; };
enum cx231xx_mute_video_shift { enum cx231xx_mute_video_shift {
CX231xx_MUTE_VIDEO_V_SHIFT = 8, CX231xx_MUTE_VIDEO_V_SHIFT = 8,
CX231xx_MUTE_VIDEO_U_SHIFT = 16, CX231xx_MUTE_VIDEO_U_SHIFT = 16,
...@@ -296,41 +319,43 @@ enum cx231xx_mute_video_shift { ...@@ -296,41 +319,43 @@ enum cx231xx_mute_video_shift {
#define CX23417_GPIO_MASK 0xFC0003FF #define CX23417_GPIO_MASK 0xFC0003FF
static int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
static int set_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 value)
{ {
int status = 0; int status = 0;
u32 _gpio_direction = 0; u32 _gpio_direction = 0;
_gpio_direction = _gpio_direction & CX23417_GPIO_MASK; _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
_gpio_direction = _gpio_direction|gpio_direction; _gpio_direction = _gpio_direction | gpio_direction;
status = cx231xx_send_gpio_cmd(dev, _gpio_direction, status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
(u8 *)&value, 4, 0, 0); (u8 *)&value, 4, 0, 0);
return status; return status;
} }
static int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
static int get_itvc_reg(struct cx231xx *dev, u32 gpio_direction, u32 *val_ptr)
{ {
int status = 0; int status = 0;
u32 _gpio_direction = 0; u32 _gpio_direction = 0;
_gpio_direction = _gpio_direction & CX23417_GPIO_MASK; _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
_gpio_direction = _gpio_direction|gpio_direction; _gpio_direction = _gpio_direction | gpio_direction;
status = cx231xx_send_gpio_cmd(dev, _gpio_direction, status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
(u8 *)pValue, 4, 0, 1); (u8 *)val_ptr, 4, 0, 1);
return status; return status;
} }
static int waitForMciComplete(struct cx231xx *dev) static int wait_for_mci_complete(struct cx231xx *dev)
{ {
u32 gpio; u32 gpio;
u32 gpio_driection = 0; u32 gpio_direction = 0;
u8 count = 0; u8 count = 0;
getITVCReg(dev, gpio_driection, &gpio); get_itvc_reg(dev, gpio_direction, &gpio);
while (!(gpio&0x020000)) { while (!(gpio&0x020000)) {
msleep(10); msleep(10);
getITVCReg(dev, gpio_driection, &gpio); get_itvc_reg(dev, gpio_direction, &gpio);
if (count++ > 100) { if (count++ > 100) {
dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio); dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
...@@ -345,57 +370,57 @@ static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value) ...@@ -345,57 +370,57 @@ static int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
u32 temp; u32 temp;
int status = 0; int status = 0;
temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8); temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8);
temp = temp<<10; temp = temp << 10;
status = setITVCReg(dev, ITVC_WRITE_DIR, temp); status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
if (status < 0) if (status < 0)
return status; return status;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write data byte 1;*/ /*write data byte 1;*/
temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00); temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write data byte 2;*/ /*write data byte 2;*/
temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8); temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write data byte 3;*/ /*write data byte 3;*/
temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16); temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write address byte 0;*/ /*write address byte 0;*/
temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8); temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write address byte 1;*/ /*write address byte 1;*/
temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00); temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*Write that the mode is write.*/ /*Write that the mode is write.*/
temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE; temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
return waitForMciComplete(dev); return wait_for_mci_complete(dev);
} }
static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
...@@ -407,70 +432,68 @@ static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value) ...@@ -407,70 +432,68 @@ static int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8); temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
temp = temp << 10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp | ((0x05) << 10); temp = temp | ((0x05) << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write address byte 1;*/ /*write address byte 1;*/
temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00); temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
temp = temp << 10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp | ((0x05) << 10); temp = temp | ((0x05) << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write that the mode is read;*/ /*write that the mode is read;*/
temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ; temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
temp = temp << 10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp | ((0x05) << 10); temp = temp | ((0x05) << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*wait for the MIRDY line to be asserted , /*wait for the MIRDY line to be asserted ,
signalling that the read is done;*/ signalling that the read is done;*/
ret = waitForMciComplete(dev); ret = wait_for_mci_complete(dev);
/*switch the DATA- GPIO to input mode;*/ /*switch the DATA- GPIO to input mode;*/
/*Read data byte 0;*/ /*Read data byte 0;*/
temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10; temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10); temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp & 0x03FC0000) >> 18); return_value |= ((temp & 0x03FC0000) >> 18);
setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
/* Read data byte 1;*/ /* Read data byte 1;*/
temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10; temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10); temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp & 0x03FC0000) >> 10); return_value |= ((temp & 0x03FC0000) >> 10);
setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
/*Read data byte 2;*/ /*Read data byte 2;*/
temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10; temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10); temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp & 0x03FC0000) >> 2); return_value |= ((temp & 0x03FC0000) >> 2);
setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
/*Read data byte 3;*/ /*Read data byte 3;*/
temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10; temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10); temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp & 0x03FC0000) << 6); return_value |= ((temp & 0x03FC0000) << 6);
setITVCReg(dev, ITVC_READ_DIR, (0x87 << 10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
*value = return_value; *value = return_value;
return ret; return ret;
} }
...@@ -481,59 +504,59 @@ static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value) ...@@ -481,59 +504,59 @@ static int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
u32 temp; u32 temp;
int ret = 0; int ret = 0;
temp = 0x82 | MCI_MEMORY_DATA_BYTE0|((value & 0x000000FF) << 8); temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
temp = temp << 10; temp = temp << 10;
ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
if (ret < 0) if (ret < 0)
return ret; return ret;
temp = temp | ((0x05) << 10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write data byte 1;*/ /*write data byte 1;*/
temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00); temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
temp = temp << 10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp | ((0x05) << 10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write data byte 2;*/ /*write data byte 2;*/
temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write data byte 3;*/ /*write data byte 3;*/
temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/* write address byte 2;*/ /* write address byte 2;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
((address & 0x003F0000)>>8); ((address & 0x003F0000) >> 8);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/* write address byte 1;*/ /* write address byte 1;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/* write address byte 0;*/ /* write address byte 0;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*wait for MIRDY line;*/ /*wait for MIRDY line;*/
waitForMciComplete(dev); wait_for_mci_complete(dev);
return 0; return 0;
} }
...@@ -545,68 +568,68 @@ static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value) ...@@ -545,68 +568,68 @@ static int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
int ret = 0; int ret = 0;
/*write address byte 2;*/ /*write address byte 2;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
((address & 0x003F0000)>>8); ((address & 0x003F0000) >> 8);
temp = temp<<10; temp = temp << 10;
ret = setITVCReg(dev, ITVC_WRITE_DIR, temp); ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
if (ret < 0) if (ret < 0)
return ret; return ret;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write address byte 1*/ /*write address byte 1*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*write address byte 0*/ /*write address byte 0*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8); temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
temp = temp<<10; temp = temp << 10;
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
setITVCReg(dev, ITVC_WRITE_DIR, temp); set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
/*Wait for MIRDY line*/ /*Wait for MIRDY line*/
ret = waitForMciComplete(dev); ret = wait_for_mci_complete(dev);
/*Read data byte 3;*/ /*Read data byte 3;*/
temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10; temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10); temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp&0x03FC0000)<<6); return_value |= ((temp & 0x03FC0000) << 6);
setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
/*Read data byte 2;*/ /*Read data byte 2;*/
temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10; temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10); temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp&0x03FC0000)>>2); return_value |= ((temp & 0x03FC0000) >> 2);
setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
/* Read data byte 1;*/ /* Read data byte 1;*/
temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10; temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10); temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp&0x03FC0000)>>10); return_value |= ((temp & 0x03FC0000) >> 10);
setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
/*Read data byte 0;*/ /*Read data byte 0;*/
temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10; temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10;
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10); temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10);
setITVCReg(dev, ITVC_READ_DIR, temp); set_itvc_reg(dev, ITVC_READ_DIR, temp);
getITVCReg(dev, ITVC_READ_DIR, &temp); get_itvc_reg(dev, ITVC_READ_DIR, &temp);
return_value |= ((temp&0x03FC0000)>>18); return_value |= ((temp & 0x03FC0000) >> 18);
setITVCReg(dev, ITVC_READ_DIR, (0x87<<10)); set_itvc_reg(dev, ITVC_READ_DIR, (0x87 << 10));
*value = return_value; *value = return_value;
return ret; return ret;
...@@ -703,10 +726,7 @@ static char *cmd_to_str(int cmd) ...@@ -703,10 +726,7 @@ static char *cmd_to_str(int cmd)
} }
} }
static int cx231xx_mbox_func(void *priv, static int cx231xx_mbox_func(void *priv, u32 command, int in, int out,
u32 command,
int in,
int out,
u32 data[CX2341X_MBOX_MAX_DATA]) u32 data[CX2341X_MBOX_MAX_DATA])
{ {
struct cx231xx *dev = priv; struct cx231xx *dev = priv;
...@@ -721,10 +741,8 @@ static int cx231xx_mbox_func(void *priv, ...@@ -721,10 +741,8 @@ static int cx231xx_mbox_func(void *priv,
without side effects */ without side effects */
mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value); mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
if (value != 0x12345678) { if (value != 0x12345678) {
dprintk(3, dprintk(3, "Firmware and/or mailbox pointer not initialized or corrupted, signature = 0x%x, cmd = %s\n",
"Firmware and/or mailbox pointer not initialized " value, cmd_to_str(command));
"or corrupted, signature = 0x%x, cmd = %s\n", value,
cmd_to_str(command));
return -1; return -1;
} }
...@@ -733,8 +751,8 @@ static int cx231xx_mbox_func(void *priv, ...@@ -733,8 +751,8 @@ static int cx231xx_mbox_func(void *priv,
*/ */
mc417_memory_read(dev, dev->cx23417_mailbox, &flag); mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
if (flag) { if (flag) {
dprintk(3, "ERROR: Mailbox appears to be in use " dprintk(3, "ERROR: Mailbox appears to be in use (%x), cmd = %s\n",
"(%x), cmd = %s\n", flag, cmd_to_str(command)); flag, cmd_to_str(command));
return -1; return -1;
} }
...@@ -787,11 +805,8 @@ static int cx231xx_mbox_func(void *priv, ...@@ -787,11 +805,8 @@ static int cx231xx_mbox_func(void *priv,
/* We don't need to call the API often, so using just one /* We don't need to call the API often, so using just one
* mailbox will probably suffice * mailbox will probably suffice
*/ */
static int cx231xx_api_cmd(struct cx231xx *dev, static int cx231xx_api_cmd(struct cx231xx *dev, u32 command,
u32 command, u32 inputcnt, u32 outputcnt, ...)
u32 inputcnt,
u32 outputcnt,
...)
{ {
u32 data[CX2341X_MBOX_MAX_DATA]; u32 data[CX2341X_MBOX_MAX_DATA];
va_list vargs; va_list vargs;
...@@ -834,81 +849,80 @@ static int cx231xx_find_mailbox(struct cx231xx *dev) ...@@ -834,81 +849,80 @@ static int cx231xx_find_mailbox(struct cx231xx *dev)
else else
signaturecnt = 0; signaturecnt = 0;
if (4 == signaturecnt) { if (4 == signaturecnt) {
dprintk(1, "Mailbox signature found at 0x%x\n", i+1); dprintk(1, "Mailbox signature found at 0x%x\n", i + 1);
return i+1; return i + 1;
} }
} }
dprintk(3, "Mailbox signature values not found!\n"); dprintk(3, "Mailbox signature values not found!\n");
return -1; return -1;
} }
static void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value, static void mci_write_memory_to_gpio(struct cx231xx *dev, u32 address, u32 value,
u32 *p_fw_image) u32 *p_fw_image)
{ {
u32 temp = 0; u32 temp = 0;
int i = 0; int i = 0;
temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8); temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
/*write data byte 1;*/ /*write data byte 1;*/
temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00); temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
/*write data byte 2;*/ /*write data byte 2;*/
temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8); temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
/*write data byte 3;*/ /*write data byte 3;*/
temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16); temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
/* write address byte 2;*/ /* write address byte 2;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE | temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
((address & 0x003F0000)>>8); ((address & 0x003F0000) >> 8);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
/* write address byte 1;*/ /* write address byte 1;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00); temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
/* write address byte 0;*/ /* write address byte 0;*/
temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8); temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
temp = temp<<10; temp = temp << 10;
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
temp = temp|((0x05)<<10); temp = temp | (0x05 << 10);
*p_fw_image = temp; *p_fw_image = temp;
p_fw_image++; p_fw_image++;
...@@ -971,8 +985,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev) ...@@ -971,8 +985,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev)
IVTV_REG_APU, 0); IVTV_REG_APU, 0);
if (retval != 0) { if (retval != 0) {
printk(KERN_ERR "%s: Error with mc417_register_write\n", pr_err("%s: Error with mc417_register_write\n", __func__);
__func__);
return -1; return -1;
} }
...@@ -980,25 +993,21 @@ static int cx231xx_load_firmware(struct cx231xx *dev) ...@@ -980,25 +993,21 @@ static int cx231xx_load_firmware(struct cx231xx *dev)
&dev->udev->dev); &dev->udev->dev);
if (retval != 0) { if (retval != 0) {
printk(KERN_ERR pr_err("ERROR: Hotplug firmware request failed (%s).\n",
"ERROR: Hotplug firmware request failed (%s).\n",
CX231xx_FIRM_IMAGE_NAME); CX231xx_FIRM_IMAGE_NAME);
printk(KERN_ERR "Please fix your hotplug setup, the board will " pr_err("Please fix your hotplug setup, the board will not work without firmware loaded!\n");
"not work without firmware loaded!\n");
return -1; return -1;
} }
if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) { if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
printk(KERN_ERR "ERROR: Firmware size mismatch " pr_err("ERROR: Firmware size mismatch (have %zd, expected %d)\n",
"(have %zd, expected %d)\n",
firmware->size, CX231xx_FIRM_IMAGE_SIZE); firmware->size, CX231xx_FIRM_IMAGE_SIZE);
release_firmware(firmware); release_firmware(firmware);
return -1; return -1;
} }
if (0 != memcmp(firmware->data, magic, 8)) { if (0 != memcmp(firmware->data, magic, 8)) {
printk(KERN_ERR pr_err("ERROR: Firmware magic mismatch, wrong file?\n");
"ERROR: Firmware magic mismatch, wrong file?\n");
release_firmware(firmware); release_firmware(firmware);
return -1; return -1;
} }
...@@ -1013,7 +1022,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev) ...@@ -1013,7 +1022,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev)
transfer_size += 4) { transfer_size += 4) {
fw_data = *p_fw_data; fw_data = *p_fw_data;
mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw); mci_write_memory_to_gpio(dev, address, fw_data, p_current_fw);
address = address + 1; address = address + 1;
p_current_fw += 20; p_current_fw += 20;
p_fw_data += 1; p_fw_data += 1;
...@@ -1045,7 +1054,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev) ...@@ -1045,7 +1054,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev)
retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS, retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
IVTV_CMD_HW_BLOCKS_RST); IVTV_CMD_HW_BLOCKS_RST);
if (retval < 0) { if (retval < 0) {
printk(KERN_ERR "%s: Error with mc417_register_write\n", pr_err("%s: Error with mc417_register_write\n",
__func__); __func__);
return retval; return retval;
} }
...@@ -1057,7 +1066,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev) ...@@ -1057,7 +1066,7 @@ static int cx231xx_load_firmware(struct cx231xx *dev)
retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8); retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
if (retval < 0) { if (retval < 0) {
printk(KERN_ERR "%s: Error with mc417_register_write\n", pr_err("%s: Error with mc417_register_write\n",
__func__); __func__);
return retval; return retval;
} }
...@@ -1105,27 +1114,25 @@ static int cx231xx_initialize_codec(struct cx231xx *dev) ...@@ -1105,27 +1114,25 @@ static int cx231xx_initialize_codec(struct cx231xx *dev)
dprintk(2, "%s() PING OK\n", __func__); dprintk(2, "%s() PING OK\n", __func__);
retval = cx231xx_load_firmware(dev); retval = cx231xx_load_firmware(dev);
if (retval < 0) { if (retval < 0) {
printk(KERN_ERR "%s() f/w load failed\n", __func__); pr_err("%s() f/w load failed\n", __func__);
return retval; return retval;
} }
retval = cx231xx_find_mailbox(dev); retval = cx231xx_find_mailbox(dev);
if (retval < 0) { if (retval < 0) {
printk(KERN_ERR "%s() mailbox < 0, error\n", pr_err("%s() mailbox < 0, error\n",
__func__); __func__);
return -1; return -1;
} }
dev->cx23417_mailbox = retval; dev->cx23417_mailbox = retval;
retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
if (retval < 0) { if (retval < 0) {
printk(KERN_ERR pr_err("ERROR: cx23417 firmware ping failed!\n");
"ERROR: cx23417 firmware ping failed!\n");
return -1; return -1;
} }
retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1, retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
&version); &version);
if (retval < 0) { if (retval < 0) {
printk(KERN_ERR "ERROR: cx23417 firmware get encoder :" pr_err("ERROR: cx23417 firmware get encoder: version failed!\n");
"version failed!\n");
return -1; return -1;
} }
dprintk(1, "cx23417 firmware version is 0x%08x\n", version); dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
...@@ -1134,7 +1141,7 @@ static int cx231xx_initialize_codec(struct cx231xx *dev) ...@@ -1134,7 +1141,7 @@ static int cx231xx_initialize_codec(struct cx231xx *dev)
for (i = 0; i < 1; i++) { for (i = 0; i < 1; i++) {
retval = mc417_register_read(dev, 0x20f8, &val); retval = mc417_register_read(dev, 0x20f8, &val);
dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n", dprintk(3, "***before enable656() VIM Capture Lines = %d ***\n",
val); val);
if (retval < 0) if (retval < 0)
return retval; return retval;
...@@ -1303,10 +1310,7 @@ static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *ur ...@@ -1303,10 +1310,7 @@ static void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *ur
memcpy(dma_q->p_left_data, memcpy(dma_q->p_left_data,
p_data, len - tail_data); p_data, len - tail_data);
} }
} }
return;
} }
static void buffer_filled(char *data, int len, struct urb *urb, static void buffer_filled(char *data, int len, struct urb *urb,
...@@ -1318,11 +1322,9 @@ static void buffer_filled(char *data, int len, struct urb *urb, ...@@ -1318,11 +1322,9 @@ static void buffer_filled(char *data, int len, struct urb *urb,
if (list_empty(&dma_q->active)) if (list_empty(&dma_q->active))
return; return;
buf = list_entry(dma_q->active.next, buf = list_entry(dma_q->active.next,
struct cx231xx_buffer, vb.queue); struct cx231xx_buffer, vb.queue);
/* Fill buffer */ /* Fill buffer */
vbuf = videobuf_to_vmalloc(&buf->vb); vbuf = videobuf_to_vmalloc(&buf->vb);
memcpy(vbuf, data, len); memcpy(vbuf, data, len);
...@@ -1331,10 +1333,9 @@ static void buffer_filled(char *data, int len, struct urb *urb, ...@@ -1331,10 +1333,9 @@ static void buffer_filled(char *data, int len, struct urb *urb,
v4l2_get_timestamp(&buf->vb.ts); v4l2_get_timestamp(&buf->vb.ts);
list_del(&buf->vb.queue); list_del(&buf->vb.queue);
wake_up(&buf->vb.done); wake_up(&buf->vb.done);
return;
} }
static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
static int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
{ {
struct cx231xx_dmaqueue *dma_q = urb->context; struct cx231xx_dmaqueue *dma_q = urb->context;
unsigned char *p_buffer; unsigned char *p_buffer;
...@@ -1359,11 +1360,9 @@ static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb) ...@@ -1359,11 +1360,9 @@ static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
return 0; return 0;
} }
static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
{
/*char *outp;*/ static int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
/*struct cx231xx_buffer *buf;*/ {
struct cx231xx_dmaqueue *dma_q = urb->context; struct cx231xx_dmaqueue *dma_q = urb->context;
unsigned char *p_buffer, *buffer; unsigned char *p_buffer, *buffer;
u32 buffer_size = 0; u32 buffer_size = 0;
...@@ -1394,8 +1393,6 @@ static int bb_buf_prepare(struct videobuf_queue *q, ...@@ -1394,8 +1393,6 @@ static int bb_buf_prepare(struct videobuf_queue *q,
int rc = 0, urb_init = 0; int rc = 0, urb_init = 0;
int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count; int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
dma_qq = &dev->video_mode.vidq;
if (0 != buf->vb.baddr && buf->vb.bsize < size) if (0 != buf->vb.baddr && buf->vb.bsize < size)
return -EINVAL; return -EINVAL;
buf->vb.width = fh->dev->ts1.ts_packet_size; buf->vb.width = fh->dev->ts1.ts_packet_size;
...@@ -1521,6 +1518,7 @@ static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm) ...@@ -1521,6 +1518,7 @@ static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
*norm = dev->encodernorm.id; *norm = dev->encodernorm.id;
return 0; return 0;
} }
static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id) static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
{ {
struct cx231xx_fh *fh = file->private_data; struct cx231xx_fh *fh = file->private_data;
...@@ -1552,7 +1550,8 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id) ...@@ -1552,7 +1550,8 @@ static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
dprintk(3, "exit vidioc_s_std() i=0x%x\n", i); dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
return 0; return 0;
} }
static const char *iname[] = {
static const char * const iname[] = {
[CX231XX_VMUX_COMPOSITE1] = "Composite1", [CX231XX_VMUX_COMPOSITE1] = "Composite1",
[CX231XX_VMUX_SVIDEO] = "S-Video", [CX231XX_VMUX_SVIDEO] = "S-Video",
[CX231XX_VMUX_TELEVISION] = "Television", [CX231XX_VMUX_TELEVISION] = "Television",
...@@ -1560,6 +1559,7 @@ static const char *iname[] = { ...@@ -1560,6 +1559,7 @@ static const char *iname[] = {
[CX231XX_VMUX_DVB] = "DVB", [CX231XX_VMUX_DVB] = "DVB",
[CX231XX_VMUX_DEBUG] = "for debug only", [CX231XX_VMUX_DEBUG] = "for debug only",
}; };
static int vidioc_enum_input(struct file *file, void *priv, static int vidioc_enum_input(struct file *file, void *priv,
struct v4l2_input *i) struct v4l2_input *i)
{ {
...@@ -1572,7 +1572,6 @@ static int vidioc_enum_input(struct file *file, void *priv, ...@@ -1572,7 +1572,6 @@ static int vidioc_enum_input(struct file *file, void *priv,
if (i->index >= 4) if (i->index >= 4)
return -EINVAL; return -EINVAL;
input = &cx231xx_boards[dev->model].input[i->index]; input = &cx231xx_boards[dev->model].input[i->index];
if (input->type == 0) if (input->type == 0)
...@@ -1589,8 +1588,6 @@ static int vidioc_enum_input(struct file *file, void *priv, ...@@ -1589,8 +1588,6 @@ static int vidioc_enum_input(struct file *file, void *priv,
i->type = V4L2_INPUT_TYPE_TUNER; i->type = V4L2_INPUT_TYPE_TUNER;
else else
i->type = V4L2_INPUT_TYPE_CAMERA; i->type = V4L2_INPUT_TYPE_CAMERA;
return 0; return 0;
} }
...@@ -1621,6 +1618,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, ...@@ -1621,6 +1618,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
{ {
struct cx231xx_fh *fh = file->private_data; struct cx231xx_fh *fh = file->private_data;
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
dprintk(3, "enter vidioc_s_ctrl()\n"); dprintk(3, "enter vidioc_s_ctrl()\n");
/* Update the A/V core */ /* Update the A/V core */
call_all(dev, core, s_ctrl, ctl); call_all(dev, core, s_ctrl, ctl);
...@@ -1631,7 +1629,6 @@ static int vidioc_s_ctrl(struct file *file, void *priv, ...@@ -1631,7 +1629,6 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f) struct v4l2_fmtdesc *f)
{ {
if (f->index != 0) if (f->index != 0)
return -EINVAL; return -EINVAL;
...@@ -1717,8 +1714,8 @@ static int vidioc_streamon(struct file *file, void *priv, ...@@ -1717,8 +1714,8 @@ static int vidioc_streamon(struct file *file, void *priv,
enum v4l2_buf_type i) enum v4l2_buf_type i)
{ {
struct cx231xx_fh *fh = file->private_data; struct cx231xx_fh *fh = file->private_data;
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
dprintk(3, "enter vidioc_streamon()\n"); dprintk(3, "enter vidioc_streamon()\n");
cx231xx_set_alt_setting(dev, INDEX_TS1, 0); cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
...@@ -1749,6 +1746,7 @@ static int vidioc_g_ext_ctrls(struct file *file, void *priv, ...@@ -1749,6 +1746,7 @@ static int vidioc_g_ext_ctrls(struct file *file, void *priv,
{ {
struct cx231xx_fh *fh = priv; struct cx231xx_fh *fh = priv;
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
dprintk(3, "enter vidioc_g_ext_ctrls()\n"); dprintk(3, "enter vidioc_g_ext_ctrls()\n");
if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
return -EINVAL; return -EINVAL;
...@@ -1763,6 +1761,7 @@ static int vidioc_s_ext_ctrls(struct file *file, void *priv, ...@@ -1763,6 +1761,7 @@ static int vidioc_s_ext_ctrls(struct file *file, void *priv,
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
struct cx2341x_mpeg_params p; struct cx2341x_mpeg_params p;
int err; int err;
dprintk(3, "enter vidioc_s_ext_ctrls()\n"); dprintk(3, "enter vidioc_s_ext_ctrls()\n");
if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
return -EINVAL; return -EINVAL;
...@@ -1776,9 +1775,6 @@ static int vidioc_s_ext_ctrls(struct file *file, void *priv, ...@@ -1776,9 +1775,6 @@ static int vidioc_s_ext_ctrls(struct file *file, void *priv,
} }
return err; return err;
return 0;
} }
static int vidioc_try_ext_ctrls(struct file *file, void *priv, static int vidioc_try_ext_ctrls(struct file *file, void *priv,
...@@ -1788,6 +1784,7 @@ static int vidioc_try_ext_ctrls(struct file *file, void *priv, ...@@ -1788,6 +1784,7 @@ static int vidioc_try_ext_ctrls(struct file *file, void *priv,
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
struct cx2341x_mpeg_params p; struct cx2341x_mpeg_params p;
int err; int err;
dprintk(3, "enter vidioc_try_ext_ctrls()\n"); dprintk(3, "enter vidioc_try_ext_ctrls()\n");
if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG) if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
return -EINVAL; return -EINVAL;
...@@ -1805,14 +1802,8 @@ static int vidioc_log_status(struct file *file, void *priv) ...@@ -1805,14 +1802,8 @@ static int vidioc_log_status(struct file *file, void *priv)
char name[32 + 2]; char name[32 + 2];
snprintf(name, sizeof(name), "%s/2", dev->name); snprintf(name, sizeof(name), "%s/2", dev->name);
dprintk(3,
"%s/2: ============ START LOG STATUS ============\n",
dev->name);
call_all(dev, core, log_status); call_all(dev, core, log_status);
cx2341x_log_status(&dev->mpeg_params, name); cx2341x_log_status(&dev->mpeg_params, name);
dprintk(3,
"%s/2: ============= END LOG STATUS =============\n",
dev->name);
return 0; return 0;
} }
...@@ -1821,6 +1812,7 @@ static int vidioc_querymenu(struct file *file, void *priv, ...@@ -1821,6 +1812,7 @@ static int vidioc_querymenu(struct file *file, void *priv,
{ {
struct cx231xx_fh *fh = priv; struct cx231xx_fh *fh = priv;
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
dprintk(3, "enter vidioc_querymenu()\n"); dprintk(3, "enter vidioc_querymenu()\n");
dprintk(3, "exit vidioc_querymenu()\n"); dprintk(3, "exit vidioc_querymenu()\n");
return cx231xx_querymenu(dev, a); return cx231xx_querymenu(dev, a);
...@@ -1831,6 +1823,7 @@ static int vidioc_queryctrl(struct file *file, void *priv, ...@@ -1831,6 +1823,7 @@ static int vidioc_queryctrl(struct file *file, void *priv,
{ {
struct cx231xx_fh *fh = priv; struct cx231xx_fh *fh = priv;
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
dprintk(3, "enter vidioc_queryctrl()\n"); dprintk(3, "enter vidioc_queryctrl()\n");
dprintk(3, "exit vidioc_queryctrl()\n"); dprintk(3, "exit vidioc_queryctrl()\n");
return cx231xx_queryctrl(dev, c); return cx231xx_queryctrl(dev, c);
...@@ -1881,7 +1874,6 @@ static int mpeg_open(struct file *file) ...@@ -1881,7 +1874,6 @@ static int mpeg_open(struct file *file)
fh, &dev->lock); fh, &dev->lock);
*/ */
cx231xx_set_alt_setting(dev, INDEX_VANC, 1); cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
cx231xx_set_gpio_value(dev, 2, 0); cx231xx_set_gpio_value(dev, 2, 0);
...@@ -1950,7 +1942,6 @@ static ssize_t mpeg_read(struct file *file, char __user *data, ...@@ -1950,7 +1942,6 @@ static ssize_t mpeg_read(struct file *file, char __user *data,
struct cx231xx_fh *fh = file->private_data; struct cx231xx_fh *fh = file->private_data;
struct cx231xx *dev = fh->dev; struct cx231xx *dev = fh->dev;
/* Deal w/ A/V decoder * and mpeg encoder sync issues. */ /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
/* Start mpeg encoder on first read. */ /* Start mpeg encoder on first read. */
if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) { if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
...@@ -1968,9 +1959,6 @@ static unsigned int mpeg_poll(struct file *file, ...@@ -1968,9 +1959,6 @@ static unsigned int mpeg_poll(struct file *file,
struct poll_table_struct *wait) struct poll_table_struct *wait)
{ {
struct cx231xx_fh *fh = file->private_data; struct cx231xx_fh *fh = file->private_data;
/*struct cx231xx *dev = fh->dev;*/
/*dprintk(2, "%s\n", __func__);*/
return videobuf_poll_stream(file, &fh->vidq, wait); return videobuf_poll_stream(file, &fh->vidq, wait);
} }
......
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