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Commit 602fd7c3 authored by Russell King's avatar Russell King
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Merge branch 'for-rmk' of git://git.fluff.org/bjdooks/linux into devel-stable 

Conflicts:
	arch/arm/Kconfig
parents d7931d9f 88d27041
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Showing with 5023 additions and 1476 deletions
Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt
View file @ 602fd7c3
......@@ -55,4 +55,4 @@ Maintainers
This board is maintained by Simtec Electronics.
(c) 2004 Ben Dooks, Simtec Electronics
Copyright 2004 Ben Dooks, Simtec Electronics
Documentation/arm/Samsung-S3C24XX/GPIO.txt
View file @ 602fd7c3
......@@ -134,4 +134,4 @@ Authour
Ben Dooks, 03 October 2004
(c) 2004 Ben Dooks, Simtec Electronics
Copyright 2004 Ben Dooks, Simtec Electronics
Documentation/arm/Samsung-S3C24XX/Overview.txt
View file @ 602fd7c3
......@@ -299,4 +299,4 @@ Port Contributors
Document Author
---------------
Ben Dooks, (c) 2004-2005,2006 Simtec Electronics
Ben Dooks, Copyright 2004-2006 Simtec Electronics
Documentation/arm/Samsung-S3C24XX/S3C2412.txt
View file @ 602fd7c3
......@@ -117,4 +117,4 @@ ATA
Document Author
---------------
Ben Dooks, (c) 2006 Simtec Electronics
Ben Dooks, Copyright 2006 Simtec Electronics
Documentation/arm/Samsung-S3C24XX/S3C2413.txt
View file @ 602fd7c3
......@@ -18,4 +18,4 @@ Camera Interface
Document Author
---------------
Ben Dooks, (c) 2006 Simtec Electronics
Ben Dooks, Copyright 2006 Simtec Electronics
Documentation/arm/Samsung-S3C24XX/Suspend.txt
View file @ 602fd7c3
......@@ -133,5 +133,5 @@ Configuration
Document Author
---------------
Ben Dooks, (c) 2004 Simtec Electronics
Ben Dooks, Copyright 2004 Simtec Electronics
Documentation/arm/Samsung-S3C24XX/USB-Host.txt
View file @ 602fd7c3
......@@ -90,4 +90,4 @@ Platform Data
Document Author
---------------
Ben Dooks, (c) 2005 Simtec Electronics
Ben Dooks, Copyright 2005 Simtec Electronics
arch/arm/Kconfig
View file @ 602fd7c3
......@@ -760,6 +760,7 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-dove/Kconfig"
source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
......
arch/arm/Makefile
View file @ 602fd7c3
......@@ -179,9 +179,9 @@ plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_ORION) := orion
plat-$(CONFIG_PLAT_PXA) := pxa
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung
plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung
plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
ifeq ($(CONFIG_ARCH_EBSA110),y)
......
arch/arm/mach-s3c2400/include/mach/map.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2400/include/mach/map.h
*
* Copyright 2003,2007 Simtec Electronics
* Copyright 2003-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/mach-s3c2410/Kconfig
View file @ 602fd7c3
......@@ -81,6 +81,14 @@ config ARCH_H1940
help
Say Y here if you are using the HP IPAQ H1940
config H1940BT
tristate "Control the state of H1940 bluetooth chip"
depends on ARCH_H1940
select RFKILL
help
This is a simple driver that is able to control
the state of built in bluetooth chip on h1940.
config PM_H1940
bool
help
......
arch/arm/mach-s3c2410/Makefile
View file @ 602fd7c3
......@@ -21,7 +21,8 @@ obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
# Machine support
obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
obj-$(CONFIG_ARCH_H1940) += mach-h1940.o h1940-bluetooth.o
obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
obj-$(CONFIG_H1940BT) += h1940-bluetooth.o
obj-$(CONFIG_PM_H1940) += pm-h1940.o
obj-$(CONFIG_MACH_N30) += mach-n30.o
obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
......
arch/arm/mach-s3c2410/bast-irq.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2410/bast-irq.c
*
* Copyright (c) 2003,2005 Simtec Electronics
* Copyright 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.simtec.co.uk/products/EB2410ITX/
......@@ -141,7 +141,7 @@ static __init int bast_irq_init(void)
unsigned int i;
if (machine_is_bast()) {
printk(KERN_INFO "BAST PC104 IRQ routing, (c) 2005 Simtec Electronics\n");
printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
/* zap all the IRQs */
......
arch/arm/mach-s3c2410/cpu-freq.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2410/cpu-freq.c
*
* Copyright (c) 2006,2008 Simtec Electronics
* Copyright (c) 2006-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/mach-s3c2410/h1940-bluetooth.c
View file @ 602fd7c3
......@@ -17,6 +17,7 @@
#include <linux/ctype.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/rfkill.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
......@@ -24,21 +25,10 @@
#define DRV_NAME "h1940-bt"
#ifdef CONFIG_LEDS_H1940
DEFINE_LED_TRIGGER(bt_led_trigger);
#endif
static int state;
/* Bluetooth control */
static void h1940bt_enable(int on)
{
if (on) {
#ifdef CONFIG_LEDS_H1940
/* flashing Blue */
led_trigger_event(bt_led_trigger, LED_HALF);
#endif
/* Power on the chip */
h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
/* Reset the chip */
......@@ -46,48 +36,31 @@ static void h1940bt_enable(int on)
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
state = 1;
}
else {
#ifdef CONFIG_LEDS_H1940
led_trigger_event(bt_led_trigger, 0);
#endif
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
mdelay(10);
h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
state = 0;
}
}
static ssize_t h1940bt_show(struct device *dev, struct device_attribute *attr, char *buf)
static int h1940bt_set_block(void *data, bool blocked)
{
return snprintf(buf, PAGE_SIZE, "%d\n", state);
h1940bt_enable(!blocked);
return 0;
}
static ssize_t h1940bt_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
int new_state;
char *endp;
new_state = simple_strtoul(buf, &endp, 0);
if (*endp && !isspace(*endp))
return -EINVAL;
h1940bt_enable(new_state);
return count;
}
static DEVICE_ATTR(enable, 0644,
h1940bt_show,
h1940bt_store);
static const struct rfkill_ops h1940bt_rfkill_ops = {
.set_block = h1940bt_set_block,
};
static int __init h1940bt_probe(struct platform_device *pdev)
{
struct rfkill *rfk;
int ret = 0;
/* Configures BT serial port GPIOs */
s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
......@@ -98,21 +71,44 @@ static int __init h1940bt_probe(struct platform_device *pdev)
s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
#ifdef CONFIG_LEDS_H1940
led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
#endif
/* disable BT by default */
h1940bt_enable(0);
rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
&h1940bt_rfkill_ops, NULL);
if (!rfk) {
ret = -ENOMEM;
goto err_rfk_alloc;
}
rfkill_set_led_trigger_name(rfk, "h1940-bluetooth");
ret = rfkill_register(rfk);
if (ret)
goto err_rfkill;
platform_set_drvdata(pdev, rfk);
return 0;
return device_create_file(&pdev->dev, &dev_attr_enable);
err_rfkill:
rfkill_destroy(rfk);
err_rfk_alloc:
return ret;
}
static int h1940bt_remove(struct platform_device *pdev)
{
#ifdef CONFIG_LEDS_H1940
led_trigger_unregister_simple(bt_led_trigger);
#endif
struct rfkill *rfk = platform_get_drvdata(pdev);
platform_set_drvdata(pdev, NULL);
if (rfk) {
rfkill_unregister(rfk);
rfkill_destroy(rfk);
}
rfk = NULL;
h1940bt_enable(0);
return 0;
}
......
arch/arm/mach-s3c2410/include/mach/bast-cpld.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* BAST - CPLD control constants
......
arch/arm/mach-s3c2410/include/mach/bast-irq.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine BAST - IRQ Number definitions
......
arch/arm/mach-s3c2410/include/mach/bast-map.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/bast-map.h
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine BAST - Memory map definitions
......
arch/arm/mach-s3c2410/include/mach/bast-pmu.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@simtec.co.uk>
*
......
arch/arm/mach-s3c2410/include/mach/dma.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/dma.h
*
* Copyright (C) 2003,2004,2006 Simtec Electronics
* Copyright (C) 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C24XX DMA support
......
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
*
* Copyright (c) 2003,2009 Simtec Electronics
* Copyright (c) 2003-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
......
arch/arm/mach-s3c2410/include/mach/osiris-map.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
*
* (c) 2005 Simtec Electronics
* Copyright 2005 Simtec Electronics
* http://www.simtec.co.uk/products/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/mach-s3c2410/include/mach/regs-clock.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/regs-clock.h
*
* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
*
* Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
* Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/mach-s3c2410/include/mach/regs-power.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/regs-power.h
*
* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/mach-s3c2410/include/mach/uncompress.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/uncompress.h
*
* Copyright (c) 2003, 2007 Simtec Electronics
* Copyright (c) 2003-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine VR1000 - IRQ Number definitions
......
arch/arm/mach-s3c2410/mach-bast.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2410/mach-bast.c
*
* Copyright (c) 2003-2005,2008 Simtec Electronics
* Copyright 2003-2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.simtec.co.uk/products/EB2410ITX/
......@@ -61,11 +61,12 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/audio-simtec.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
......@@ -247,7 +248,7 @@ static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };
static struct mtd_partition bast_default_nand_part[] = {
static struct mtd_partition __initdata bast_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_16K,
......@@ -273,7 +274,7 @@ static struct mtd_partition bast_default_nand_part[] = {
* socket.
*/
static struct s3c2410_nand_set bast_nand_sets[] = {
static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
[0] = {
.name = "SmartMedia",
.nr_chips = 1,
......@@ -323,7 +324,7 @@ static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
__raw_writeb(tmp, BAST_VA_CTRL2);
}
static struct s3c2410_platform_nand bast_nand_info = {
static struct s3c2410_platform_nand __initdata bast_nand_info = {
.tacls = 30,
.twrph0 = 60,
.twrph1 = 60,
......@@ -608,6 +609,11 @@ static struct s3c_cpufreq_board __initdata bast_cpufreq = {
.need_io = 1,
};
static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
.have_mic = 1,
.have_lout = 1,
};
static void __init bast_map_io(void)
{
/* initialise the clocks */
......@@ -625,7 +631,6 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_nand.dev.platform_data = &bast_nand_info;
s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
......@@ -639,6 +644,7 @@ static void __init bast_init(void)
sysdev_register(&bast_pm_sysdev);
s3c_i2c0_set_platdata(&bast_i2c_info);
s3c_nand_set_platdata(&bast_nand_info);
s3c24xx_fb_set_platdata(&bast_fb_info);
platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
......@@ -647,6 +653,7 @@ static void __init bast_init(void)
usb_simtec_init();
nor_simtec_init();
simtec_audio_add(NULL, true, &bast_audio);
s3c_cpufreq_setboard(&bast_cpufreq);
}
......
arch/arm/mach-s3c2410/mach-h1940.c
View file @ 602fd7c3
......@@ -21,6 +21,11 @@
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/pwm_backlight.h>
#include <video/platform_lcd.h>
#include <linux/mmc/host.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -32,9 +37,12 @@
#include <plat/regs-serial.h>
#include <mach/regs-lcd.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/gpio-fns.h>
#include <mach/gpio-nrs.h>
#include <mach/h1940.h>
#include <mach/h1940-latch.h>
#include <mach/fb.h>
......@@ -46,6 +54,7 @@
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/mci.h>
static struct map_desc h1940_iodesc[] __initdata = {
[0] = {
......@@ -171,16 +180,90 @@ static struct s3c2410fb_mach_info h1940_fb_info __initdata = {
.gpdup_mask= 0xffffffff,
};
static struct platform_device s3c_device_leds = {
static struct platform_device h1940_device_leds = {
.name = "h1940-leds",
.id = -1,
};
static struct platform_device s3c_device_bluetooth = {
static struct platform_device h1940_device_bluetooth = {
.name = "h1940-bt",
.id = -1,
};
static struct s3c24xx_mci_pdata h1940_mmc_cfg = {
.gpio_detect = S3C2410_GPF(5),
.gpio_wprotect = S3C2410_GPH(8),
.set_power = NULL,
.ocr_avail = MMC_VDD_32_33,
};
static int h1940_backlight_init(struct device *dev)
{
gpio_request(S3C2410_GPB(0), "Backlight");
s3c2410_gpio_setpin(S3C2410_GPB(0), 0);
s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
return 0;
}
static void h1940_backlight_exit(struct device *dev)
{
s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/);
}
static struct platform_pwm_backlight_data backlight_data = {
.pwm_id = 0,
.max_brightness = 100,
.dft_brightness = 50,
/* tcnt = 0x31 */
.pwm_period_ns = 36296,
.init = h1940_backlight_init,
.exit = h1940_backlight_exit,
};
static struct platform_device h1940_backlight = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[0].dev,
.platform_data = &backlight_data,
},
.id = -1,
};
static void h1940_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
int value;
if (!power) {
/* set to 3ec */
s3c2410_gpio_setpin(S3C2410_GPC(0), 0);
/* wait for 3ac */
do {
value = s3c2410_gpio_getpin(S3C2410_GPC(6));
} while (value);
/* set to 38c */
s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
} else {
/* Set to 3ac */
s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
/* Set to 3ad */
s3c2410_gpio_setpin(S3C2410_GPC(0), 1);
}
}
static struct plat_lcd_data h1940_lcd_power_data = {
.set_power = h1940_lcd_power_set,
};
static struct platform_device h1940_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_lcd.dev,
.dev.platform_data = &h1940_lcd_power_data,
};
static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
......@@ -188,8 +271,13 @@ static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&s3c_device_leds,
&s3c_device_bluetooth,
&h1940_device_leds,
&h1940_device_bluetooth,
&s3c_device_sdi,
&s3c_device_rtc,
&s3c_device_timer[0],
&h1940_backlight,
&h1940_lcd_powerdev,
};
static void __init h1940_map_io(void)
......@@ -219,6 +307,8 @@ static void __init h1940_init(void)
s3c24xx_udc_set_platdata(&h1940_udc_cfg);
s3c_i2c0_set_platdata(NULL);
s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg;
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
......@@ -231,6 +321,11 @@ static void __init h1940_init(void)
| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
writel(tmp, S3C2410_UPLLCON);
gpio_request(S3C2410_GPC(0), "LCD power");
gpio_request(S3C2410_GPC(5), "LCD power");
gpio_request(S3C2410_GPC(6), "LCD power");
platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
}
......
arch/arm/mach-s3c2410/mach-n30.c
View file @ 602fd7c3
......@@ -338,7 +338,7 @@ static struct platform_device *n35_devices[] __initdata = {
&n35_button_device,
};
static struct s3c2410_platform_i2c n30_i2ccfg = {
static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
.flags = 0,
.slave_addr = 0x10,
.frequency = 10*1000,
......@@ -500,8 +500,8 @@ static void __init n30_init_irq(void)
static void __init n30_init(void)
{
s3c24xx_fb_set_platdata(&n30_fb_info);
s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
s3c24xx_udc_set_platdata(&n30_udc_cfg);
s3c_i2c0_set_platdata(&n30_i2ccfg);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
......
arch/arm/mach-s3c2410/mach-qt2410.c
View file @ 602fd7c3
......@@ -258,7 +258,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
&qt2410_led,
};
static struct mtd_partition qt2410_nand_part[] = {
static struct mtd_partition __initdata qt2410_nand_part[] = {
[0] = {
.name = "U-Boot",
.size = 0x30000,
......@@ -286,7 +286,7 @@ static struct mtd_partition qt2410_nand_part[] = {
},
};
static struct s3c2410_nand_set qt2410_nand_sets[] = {
static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
[0] = {
.name = "NAND",
.nr_chips = 1,
......@@ -299,7 +299,7 @@ static struct s3c2410_nand_set qt2410_nand_sets[] = {
* chips and beyond.
*/
static struct s3c2410_platform_nand qt2410_nand_info = {
static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
.tacls = 20,
.twrph0 = 60,
.twrph1 = 20,
......@@ -331,7 +331,7 @@ static void __init qt2410_map_io(void)
static void __init qt2410_machine_init(void)
{
s3c_device_nand.dev.platform_data = &qt2410_nand_info;
s3c_nand_set_platdata(&qt2410_nand_info);
switch (tft_type) {
case 'p': /* production */
......
arch/arm/mach-s3c2410/mach-vr1000.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
*
* Copyright (c) 2003-2005,2008 Simtec Electronics
* Copyright (c) 2003-2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Machine support for Thorcom VR1000 board. Designed for Thorcom by
......@@ -49,6 +49,7 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
#include <plat/audio-simtec.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
......@@ -393,6 +394,7 @@ static void __init vr1000_init(void)
ARRAY_SIZE(vr1000_i2c_devs));
nor_simtec_init();
simtec_audio_add(NULL, true, NULL);
}
MACHINE_START(VR1000, "Thorcom-VR1000")
......
arch/arm/mach-s3c2410/pll.c
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/pll.c
*
* Copyright (c) 2006,2007 Simtec Electronics
* Copyright (c) 2006-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@arm.linux.org.uk>
......
arch/arm/mach-s3c2410/usb-simtec.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2410/usb-simtec.c
*
* Copyright (c) 2004,2005 Simtec Electronics
* Copyright 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.simtec.co.uk/products/EB2410ITX/
......@@ -108,7 +108,7 @@ int usb_simtec_init(void)
{
int ret;
printk("USB Power Control, (c) 2004 Simtec Electronics\n");
printk("USB Power Control, Copyright 2004 Simtec Electronics\n");
ret = gpio_request(S3C2410_GPB(4), "USB power control");
if (ret < 0) {
......
arch/arm/mach-s3c2412/mach-jive.c
View file @ 602fd7c3
......@@ -96,7 +96,7 @@ static struct s3c2410_uartcfg jive_uartcfgs[] = {
* 0x017d0000-0x02bd0000 : cramfs B
* 0x02bd0000-0x03fd0000 : yaffs
*/
static struct mtd_partition jive_imageA_nand_part[] = {
static struct mtd_partition __initdata jive_imageA_nand_part[] = {
#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
/* Don't allow access to the bootloader from linux */
......@@ -154,7 +154,7 @@ static struct mtd_partition jive_imageA_nand_part[] = {
},
};
static struct mtd_partition jive_imageB_nand_part[] = {
static struct mtd_partition __initdata jive_imageB_nand_part[] = {
#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
/* Don't allow access to the bootloader from linux */
......@@ -213,7 +213,7 @@ static struct mtd_partition jive_imageB_nand_part[] = {
},
};
static struct s3c2410_nand_set jive_nand_sets[] = {
static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
[0] = {
.name = "flash",
.nr_chips = 1,
......@@ -222,7 +222,7 @@ static struct s3c2410_nand_set jive_nand_sets[] = {
},
};
static struct s3c2410_platform_nand jive_nand_info = {
static struct s3c2410_platform_nand __initdata jive_nand_info = {
/* set taken from osiris nand timings, possibly still conservative */
.tacls = 30,
.twrph0 = 55,
......@@ -631,7 +631,8 @@ static void __init jive_machine_init(void)
s3c_pm_init();
s3c_device_nand.dev.platform_data = &jive_nand_info;
/** TODO - check that this is after the cmdline option! */
s3c_nand_set_platdata(&jive_nand_info);
/* initialise the spi */
......
arch/arm/mach-s3c2412/mach-vstms.c
View file @ 602fd7c3
......@@ -76,7 +76,7 @@ static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
}
};
static struct mtd_partition vstms_nand_part[] = {
static struct mtd_partition __initdata vstms_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = 0x7C000,
......@@ -99,7 +99,7 @@ static struct mtd_partition vstms_nand_part[] = {
},
};
static struct s3c2410_nand_set vstms_nand_sets[] = {
static struct s3c2410_nand_set __initdata vstms_nand_sets[] = {
[0] = {
.name = "NAND",
.nr_chips = 1,
......@@ -112,7 +112,7 @@ static struct s3c2410_nand_set vstms_nand_sets[] = {
* chips and beyond.
*/
static struct s3c2410_platform_nand vstms_nand_info = {
static struct s3c2410_platform_nand __initdata vstms_nand_info = {
.tacls = 20,
.twrph0 = 60,
.twrph1 = 20,
......@@ -143,8 +143,6 @@ static void __init vstms_fixup(struct machine_desc *desc,
static void __init vstms_map_io(void)
{
s3c_device_nand.dev.platform_data = &vstms_nand_info;
s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
......@@ -153,6 +151,8 @@ static void __init vstms_map_io(void)
static void __init vstms_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_nand_set_platdata(&vstms_nand_info);
platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
}
......
arch/arm/mach-s3c2440/Kconfig
View file @ 602fd7c3
......@@ -53,6 +53,19 @@ config MACH_OSIRIS
Say Y here if you are using the Simtec IM2440D20 module, also
known as the Osiris.
config MACH_OSIRIS_DVS
tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
depends on MACH_OSIRIS
select TPS65010
help
Say Y/M here if you want to have dynamic voltage scaling support
on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
The DVS driver alters the voltage supplied to the ARM core
depending on the frequency it is running at. The driver itself
does not do any of the frequency alteration, which is left up
to the cpufreq driver.
config MACH_RX3715
bool "HP iPAQ rx3715"
select CPU_S3C2440
......
arch/arm/mach-s3c2440/Makefile
View file @ 602fd7c3
......@@ -23,3 +23,7 @@ obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
# extra machine support
obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o
arch/arm/mach-s3c2440/irq.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2440/irq.c
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/mach-s3c2440/mach-anubis.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2440/mach-anubis.c
*
* Copyright (c) 2003-2005,2008 Simtec Electronics
* Copyright 2003-2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......@@ -53,8 +53,9 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/audio-simtec.h>
#define COPYRIGHT ", (c) 2005 Simtec Electronics"
#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
static struct map_desc anubis_iodesc[] __initdata = {
/* ISA IO areas */
......@@ -138,7 +139,7 @@ static int external_map[] = { 2 };
static int chip0_map[] = { 0 };
static int chip1_map[] = { 1 };
static struct mtd_partition anubis_default_nand_part[] = {
static struct mtd_partition __initdata anubis_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_16K,
......@@ -161,7 +162,7 @@ static struct mtd_partition anubis_default_nand_part[] = {
}
};
static struct mtd_partition anubis_default_nand_part_large[] = {
static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_128K,
......@@ -191,7 +192,7 @@ static struct mtd_partition anubis_default_nand_part_large[] = {
* socket.
*/
static struct s3c2410_nand_set anubis_nand_sets[] = {
static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
[1] = {
.name = "External",
.nr_chips = 1,
......@@ -233,7 +234,7 @@ static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
__raw_writeb(tmp, ANUBIS_VA_CTRL1);
}
static struct s3c2410_platform_nand anubis_nand_info = {
static struct s3c2410_platform_nand __initdata anubis_nand_info = {
.tacls = 25,
.twrph0 = 55,
.twrph1 = 40,
......@@ -437,6 +438,17 @@ static struct i2c_board_info anubis_i2c_devs[] __initdata = {
}
};
/* Audio setup */
static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
.have_mic = 1,
.have_lout = 1,
.output_cdclk = 1,
.use_mpllin = 1,
.amp_gpio = S3C2410_GPB(2),
.amp_gain[0] = S3C2410_GPD(10),
.amp_gain[1] = S3C2410_GPD(11),
};
static void __init anubis_map_io(void)
{
/* initialise the clocks */
......@@ -454,8 +466,6 @@ static void __init anubis_map_io(void)
s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
s3c_device_nand.dev.platform_data = &anubis_nand_info;
s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
s3c24xx_init_clocks(0);
s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
......@@ -476,6 +486,9 @@ static void __init anubis_map_io(void)
static void __init anubis_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_nand_set_platdata(&anubis_nand_info);
simtec_audio_add(NULL, false, &anubis_audio);
platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
i2c_register_board_info(0, anubis_i2c_devs,
......
arch/arm/mach-s3c2440/mach-at2440evb.c
View file @ 602fd7c3
......@@ -96,7 +96,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
/* NAND Flash on AT2440EVB board */
static struct mtd_partition at2440evb_default_nand_part[] = {
static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_256K,
......@@ -114,7 +114,7 @@ static struct mtd_partition at2440evb_default_nand_part[] = {
},
};
static struct s3c2410_nand_set at2440evb_nand_sets[] = {
static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
[0] = {
.name = "nand",
.nr_chips = 1,
......@@ -123,7 +123,7 @@ static struct s3c2410_nand_set at2440evb_nand_sets[] = {
},
};
static struct s3c2410_platform_nand at2440evb_nand_info = {
static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
.tacls = 25,
.twrph0 = 55,
.twrph1 = 40,
......@@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = {
static void __init at2440evb_map_io(void)
{
s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata;
s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
......@@ -228,6 +226,7 @@ static void __init at2440evb_map_io(void)
static void __init at2440evb_init(void)
{
s3c24xx_fb_set_platdata(&at2440evb_fb_info);
s3c_nand_set_platdata(&at2440evb_nand_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
......
arch/arm/mach-s3c2440/mach-mini2440.c
View file @ 602fd7c3
......@@ -532,7 +532,6 @@ static void __init mini2440_map_io(void)
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
s3c_device_nand.dev.platform_data = &mini2440_nand_info;
s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg;
}
......@@ -677,8 +676,11 @@ static void __init mini2440_init(void)
printk("\n");
s3c24xx_fb_set_platdata(&mini2440_fb_info);
}
s3c24xx_udc_set_platdata(&mini2440_udc_cfg);
s3c_nand_set_platdata(&mini2440_nand_info);
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, mini2440_i2c_devs,
ARRAY_SIZE(mini2440_i2c_devs));
......
arch/arm/mach-s3c2440/mach-osiris-dvs.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2440/mach-osiris-dvs.c
*
* Copyright (c) 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Simtec Osiris Dynamic Voltage Scaling support.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/cpufreq.h>
#include <linux/gpio.h>
#include <linux/i2c/tps65010.h>
#include <plat/cpu-freq.h>
#define OSIRIS_GPIO_DVS S3C2410_GPB(5)
static bool dvs_en;
static void osiris_dvs_tps_setdvs(bool on)
{
unsigned vregs1 = 0, vdcdc2 = 0;
if (!on) {
vdcdc2 = TPS_VCORE_DISCH | TPS_LP_COREOFF;
vregs1 = TPS_LDO1_OFF; /* turn off in low-power mode */
}
dvs_en = on;
vdcdc2 |= TPS_VCORE_1_3V | TPS_VCORE_LP_1_0V;
vregs1 |= TPS_LDO2_ENABLE | TPS_LDO1_ENABLE;
tps65010_config_vregs1(vregs1);
tps65010_config_vdcdc2(vdcdc2);
}
static bool is_dvs(struct s3c_freq *f)
{
/* at the moment, we assume ARMCLK = HCLK => DVS */
return f->armclk == f->hclk;
}
/* keep track of current state */
static bool cur_dvs = false;
static int osiris_dvs_notify(struct notifier_block *nb,
unsigned long val, void *data)
{
struct cpufreq_freqs *cf = data;
struct s3c_cpufreq_freqs *freqs = to_s3c_cpufreq(cf);
bool old_dvs = is_dvs(&freqs->old);
bool new_dvs = is_dvs(&freqs->new);
int ret = 0;
if (!dvs_en)
return 0;
printk(KERN_DEBUG "%s: old %ld,%ld new %ld,%ld\n", __func__,
freqs->old.armclk, freqs->old.hclk,
freqs->new.armclk, freqs->new.hclk);
switch (val) {
case CPUFREQ_PRECHANGE:
if (old_dvs & !new_dvs ||
cur_dvs & !new_dvs) {
pr_debug("%s: exiting dvs\n", __func__);
cur_dvs = false;
gpio_set_value(OSIRIS_GPIO_DVS, 1);
}
break;
case CPUFREQ_POSTCHANGE:
if (!old_dvs & new_dvs ||
!cur_dvs & new_dvs) {
pr_debug("entering dvs\n");
cur_dvs = true;
gpio_set_value(OSIRIS_GPIO_DVS, 0);
}
break;
}
return ret;
}
static struct notifier_block osiris_dvs_nb = {
.notifier_call = osiris_dvs_notify,
};
static int __devinit osiris_dvs_probe(struct platform_device *pdev)
{
int ret;
dev_info(&pdev->dev, "initialising\n");
ret = gpio_request(OSIRIS_GPIO_DVS, "osiris-dvs");
if (ret) {
dev_err(&pdev->dev, "cannot claim gpio\n");
goto err_nogpio;
}
/* start with dvs disabled */
gpio_direction_output(OSIRIS_GPIO_DVS, 1);
ret = cpufreq_register_notifier(&osiris_dvs_nb,
CPUFREQ_TRANSITION_NOTIFIER);
if (ret) {
dev_err(&pdev->dev, "failed to register with cpufreq\n");
goto err_nofreq;
}
osiris_dvs_tps_setdvs(true);
return 0;
err_nofreq:
gpio_free(OSIRIS_GPIO_DVS);
err_nogpio:
return ret;
}
static int __devexit osiris_dvs_remove(struct platform_device *pdev)
{
dev_info(&pdev->dev, "exiting\n");
/* disable any current dvs */
gpio_set_value(OSIRIS_GPIO_DVS, 1);
osiris_dvs_tps_setdvs(false);
cpufreq_unregister_notifier(&osiris_dvs_nb,
CPUFREQ_TRANSITION_NOTIFIER);
gpio_free(OSIRIS_GPIO_DVS);
return 0;
}
/* the CONFIG_PM block is so small, it isn't worth actaully compiling it
* out if the configuration isn't set. */
static int osiris_dvs_suspend(struct device *dev)
{
gpio_set_value(OSIRIS_GPIO_DVS, 1);
osiris_dvs_tps_setdvs(false);
cur_dvs = false;
return 0;
}
static int osiris_dvs_resume(struct device *dev)
{
osiris_dvs_tps_setdvs(true);
return 0;
}
static const struct dev_pm_ops osiris_dvs_pm = {
.suspend = osiris_dvs_suspend,
.resume = osiris_dvs_resume,
};
static struct platform_driver osiris_dvs_driver = {
.probe = osiris_dvs_probe,
.remove = __devexit_p(osiris_dvs_remove),
.driver = {
.name = "osiris-dvs",
.owner = THIS_MODULE,
.pm = &osiris_dvs_pm,
},
};
static int __init osiris_dvs_init(void)
{
return platform_driver_register(&osiris_dvs_driver);
}
static void __exit osiris_dvs_exit(void)
{
platform_driver_unregister(&osiris_dvs_driver);
}
module_init(osiris_dvs_init);
module_exit(osiris_dvs_exit);
MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:osiris-dvs");
arch/arm/mach-s3c2440/mach-osiris.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2440/mach-osiris.c
*
* Copyright (c) 2005,2008 Simtec Electronics
* Copyright (c) 2005-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......@@ -23,6 +23,8 @@
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/i2c/tps65010.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
......@@ -148,7 +150,7 @@ static int external_map[] = { 2 };
static int chip0_map[] = { 0 };
static int chip1_map[] = { 1 };
static struct mtd_partition osiris_default_nand_part[] = {
static struct mtd_partition __initdata osiris_default_nand_part[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_16K,
......@@ -171,7 +173,7 @@ static struct mtd_partition osiris_default_nand_part[] = {
}
};
static struct mtd_partition osiris_default_nand_part_large[] = {
static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
[0] = {
.name = "Boot Agent",
.size = SZ_128K,
......@@ -201,7 +203,7 @@ static struct mtd_partition osiris_default_nand_part_large[] = {
* socket.
*/
static struct s3c2410_nand_set osiris_nand_sets[] = {
static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
[1] = {
.name = "External",
.nr_chips = 1,
......@@ -243,7 +245,7 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}
static struct s3c2410_platform_nand osiris_nand_info = {
static struct s3c2410_platform_nand __initdata osiris_nand_info = {
.tacls = 25,
.twrph0 = 60,
.twrph1 = 60,
......@@ -326,12 +328,44 @@ static struct sys_device osiris_pm_sysdev = {
.cls = &osiris_pm_sysclass,
};
/* Link for DVS driver to TPS65011 */
static void osiris_tps_release(struct device *dev)
{
/* static device, do not need to release anything */
}
static struct platform_device osiris_tps_device = {
.name = "osiris-dvs",
.id = -1,
.dev.release = osiris_tps_release,
};
static int osiris_tps_setup(struct i2c_client *client, void *context)
{
osiris_tps_device.dev.parent = &client->dev;
return platform_device_register(&osiris_tps_device);
}
static int osiris_tps_remove(struct i2c_client *client, void *context)
{
platform_device_unregister(&osiris_tps_device);
return 0;
}
static struct tps65010_board osiris_tps_board = {
.base = -1, /* GPIO can go anywhere at the moment */
.setup = osiris_tps_setup,
.teardown = osiris_tps_remove,
};
/* I2C devices fitted. */
static struct i2c_board_info osiris_i2c_devs[] __initdata = {
{
I2C_BOARD_INFO("tps65011", 0x48),
.irq = IRQ_EINT20,
.platform_data = &osiris_tps_board,
},
};
......@@ -377,8 +411,6 @@ static void __init osiris_map_io(void)
s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
s3c_device_nand.dev.platform_data = &osiris_nand_info;
s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
s3c24xx_init_clocks(0);
s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
......@@ -408,6 +440,7 @@ static void __init osiris_init(void)
sysdev_register(&osiris_pm_sysdev);
s3c_i2c0_set_platdata(NULL);
s3c_nand_set_platdata(&osiris_nand_info);
s3c_cpufreq_setboard(&osiris_cpufreq);
......
arch/arm/mach-s3c2440/mach-rx3715.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2440/mach-rx3715.c
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.handhelds.org/projects/rx3715.html
......@@ -149,7 +149,7 @@ static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
.gpdup_mask = 0xffffffff,
};
static struct mtd_partition rx3715_nand_part[] = {
static struct mtd_partition __initdata rx3715_nand_part[] = {
[0] = {
.name = "Whole Flash",
.offset = 0,
......@@ -158,7 +158,7 @@ static struct mtd_partition rx3715_nand_part[] = {
}
};
static struct s3c2410_nand_set rx3715_nand_sets[] = {
static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
[0] = {
.name = "Internal",
.nr_chips = 1,
......@@ -167,7 +167,7 @@ static struct s3c2410_nand_set rx3715_nand_sets[] = {
},
};
static struct s3c2410_platform_nand rx3715_nand_info = {
static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
.tacls = 25,
.twrph0 = 50,
.twrph1 = 15,
......@@ -186,8 +186,6 @@ static struct platform_device *rx3715_devices[] __initdata = {
static void __init rx3715_map_io(void)
{
s3c_device_nand.dev.platform_data = &rx3715_nand_info;
s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
s3c24xx_init_clocks(16934000);
s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
......@@ -205,6 +203,7 @@ static void __init rx3715_init_machine(void)
#endif
s3c_pm_init();
s3c_nand_set_platdata(&rx3715_nand_info);
s3c24xx_fb_set_platdata(&rx3715_fb_info);
platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
}
......
arch/arm/mach-s3c2440/mach-smdk2440.c
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c2440/mach-smdk2440.c
*
* Copyright (c) 2004,2005 Simtec Electronics
* Copyright (c) 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://www.fluff.org/ben/smdk2440/
......
arch/arm/mach-s3c2442/mach-gta02.c
View file @ 602fd7c3
......@@ -423,7 +423,7 @@ static struct i2c_board_info gta02_i2c_devs[] __initdata = {
},
};
static struct s3c2410_nand_set gta02_nand_sets[] = {
static struct s3c2410_nand_set __initdata gta02_nand_sets[] = {
[0] = {
/*
* This name is also hard-coded in the boot loaders, so
......@@ -442,7 +442,7 @@ static struct s3c2410_nand_set gta02_nand_sets[] = {
* data sheet (K5D2G13ACM-D075 MCP Memory).
*/
static struct s3c2410_platform_nand gta02_nand_info = {
static struct s3c2410_platform_nand __initdata gta02_nand_info = {
.tacls = 0,
.twrph0 = 25,
.twrph1 = 15,
......@@ -621,9 +621,9 @@ static void __init gta02_machine_init(void)
#endif
s3c_device_usb.dev.platform_data = &gta02_usb_info;
s3c_device_nand.dev.platform_data = &gta02_nand_info;
s3c24xx_udc_set_platdata(&gta02_udc_cfg);
s3c_nand_set_platdata(&gta02_nand_info);
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
......
arch/arm/mach-s3c24a0/include/mach/map.h
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
*
* Copyright 2003,2007 Simtec Electronics
* Copyright 2003-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/mach-s3c24a0/include/mach/regs-clock.h
View file @ 602fd7c3
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
*
* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/mach-s3c6400/include/mach/map.h
View file @ 602fd7c3
......@@ -64,6 +64,9 @@
#define S3C64XX_PA_USBHOST (0x74300000)
#define S3C64XX_PA_USB_HSPHY (0x7C100000)
#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
/* place VICs close together */
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
......@@ -79,5 +82,6 @@
#define S3C_PA_FB S3C64XX_PA_FB
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
#endif /* __ASM_ARCH_6400_MAP_H */
arch/arm/mach-s3c6400/include/mach/regs-fb.h
View file @ 602fd7c3
/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
*
/*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - new-style framebuffer register definitions
* Copyright 2009 Samsung Electronics Co.
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards and specifically the S3C64XX series
* S3C6400 and S3C6410.
* Pawel Osciak <p.osciak@samsung.com>
* Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
*
* The file contains the cpu specific items which change between whichever
* architecture is selected. See <plat/regs-fb.h> for the core definitions
* that are the same.
* Framebuffer register definitions for Samsung S3C64xx.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* include the core definitions here, in case we really do need to
* override them at a later date.
*/
#include <plat/regs-fb.h>
#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
/* Window position controls */
#define WINCON(_win) (0x20 + ((_win) * 4))
/* OSD1 and OSD4 do not have register D */
#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDINTCON0 (0x130)
#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
/* WINCONx */
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
#define WINCONx_ENLOCAL (1 << 22)
#define WINCONx_BUFSTATUS (1 << 21)
#define WINCONx_BUFSEL (1 << 20)
#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_YCbCr (1 << 13)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_BLD_PIX (1 << 6)
#define WINCON2_ALPHA_SEL (1 << 1)
#define WINCON2_BPPMODE_MASK (0xf << 2)
#define WINCON2_BPPMODE_SHIFT (2)
#define WINCON2_BPPMODE_1BPP (0x0 << 2)
#define WINCON2_BPPMODE_2BPP (0x1 << 2)
#define WINCON2_BPPMODE_4BPP (0x2 << 2)
#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
#define WINCON3_BLD_PIX (1 << 6)
#define WINCON3_ALPHA_SEL (1 << 1)
#define WINCON3_BPPMODE_MASK (0xf << 2)
#define WINCON3_BPPMODE_SHIFT (2)
#define WINCON3_BPPMODE_1BPP (0x0 << 2)
#define WINCON3_BPPMODE_2BPP (0x1 << 2)
#define WINCON3_BPPMODE_4BPP (0x2 << 2)
#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define DITHMODE (0x170)
#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define DITHMODE_R_POS_MASK (0x3 << 5)
#define DITHMODE_R_POS_SHIFT (5)
#define DITHMODE_R_POS_8BIT (0x0 << 5)
#define DITHMODE_R_POS_6BIT (0x1 << 5)
#define DITHMODE_R_POS_5BIT (0x2 << 5)
#define DITHMODE_G_POS_MASK (0x3 << 3)
#define DITHMODE_G_POS_SHIFT (3)
#define DITHMODE_G_POS_8BIT (0x0 << 3)
#define DITHMODE_G_POS_6BIT (0x1 << 3)
#define DITHMODE_G_POS_5BIT (0x2 << 3)
#define DITHMODE_B_POS_MASK (0x3 << 1)
#define DITHMODE_B_POS_SHIFT (1)
#define DITHMODE_B_POS_8BIT (0x0 << 1)
#define DITHMODE_B_POS_6BIT (0x1 << 1)
#define DITHMODE_B_POS_5BIT (0x2 << 1)
#ifndef __ASM_ARCH_MACH_REGS_FB_H
#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
#define DITHMODE_DITH_EN (1 << 0)
#define WPALCON (0x1A0)
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
#include <plat/regs-fb-v4.h>
/* Palette registers */
#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
/* system specific implementation code for palette sizes, and other
* information that changes depending on which architecture is being
* compiled.
*/
/* return true if window _win has OSD register D */
#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
{
if (win < 2)
return 256;
if (win < 4)
return 16;
if (win == 4)
return 4;
BUG(); /* shouldn't get here */
}
static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
{
/* all windows can do 1/2 bpp */
if ((bpp == 25 || bpp == 19) && win == 0)
return 0; /* win 0 does not have 19 or 25bpp modes */
if (bpp == 4 && win == 4)
return 0;
if (bpp == 8 && (win >= 3))
return 0; /* win 3/4 cannot do 8bpp in any mode */
return 1;
}
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
......@@ -203,57 +38,4 @@ static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
BUG();
}
static inline int s3c_fb_pal_is16(unsigned int window)
{
return window > 1;
}
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
struct fb_bitfield b;
struct fb_bitfield a;
};
static inline void s3c_fb_init_palette(unsigned int window,
struct s3c_fb_palette *palette)
{
if (window < 2) {
/* Windows 0/1 are 8/8/8 or A/8/8/8 */
palette->r.offset = 16;
palette->r.length = 8;
palette->g.offset = 8;
palette->g.length = 8;
palette->b.offset = 0;
palette->b.length = 8;
} else {
/* currently we assume RGB 5/6/5 */
palette->r.offset = 11;
palette->r.length = 5;
palette->g.offset = 5;
palette->g.length = 6;
palette->b.offset = 0;
palette->b.length = 5;
}
}
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
* 0010 4(P) 4(P) 4(P) 4(P) -none-
* 0011 8(P) 8(P) -none- -none- -none-
* 0100 -none- 8(A232) 8(A232) -none- -none-
* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
* 1110 -none- -none- -none- -none- -none-
* 1111 -none- -none- -none- -none- -none-
*/
#endif /* __ASM_ARCH_MACH_REGS_FB_H */
arch/arm/mach-s3c6400/s3c6400.c
View file @ 602fd7c3
......@@ -45,6 +45,7 @@ void __init s3c6400_map_io(void)
s3c6400_default_sdhci0();
s3c6400_default_sdhci1();
s3c6400_default_sdhci2();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
......
arch/arm/mach-s3c6410/cpu.c
View file @ 602fd7c3
......@@ -58,6 +58,7 @@ void __init s3c6410_map_io(void)
/* initialise device information early */
s3c6410_default_sdhci0();
s3c6410_default_sdhci1();
s3c6410_default_sdhci2();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
......
arch/arm/mach-s3c6410/mach-hmt.c
View file @ 602fd7c3
......@@ -250,7 +250,7 @@ static void __init hmt_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_fb_set_platdata(&hmt_lcd_pdata);
s3c_device_nand.dev.platform_data = &hmt_nand_info;
s3c_nand_set_platdata(&hmt_nand_info);
gpio_request(S3C64XX_GPC(7), "usb power");
gpio_direction_output(S3C64XX_GPC(7), 0);
......
arch/arm/mach-s3c6410/mach-smdk6410.c
View file @ 602fd7c3
......@@ -25,6 +25,7 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/smsc911x.h>
#include <linux/regulator/fixed.h>
#ifdef CONFIG_SMDK6410_WM1190_EV1
#include <linux/mfd/wm8350/core.h>
......@@ -184,6 +185,43 @@ static struct platform_device smdk6410_smsc911x = {
},
};
#ifdef CONFIG_REGULATOR
static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
{
/* WM8580 */
.supply = "PVDD",
.dev_name = "0-001b",
},
{
/* WM8580 */
.supply = "AVDD",
.dev_name = "0-001b",
},
};
static struct regulator_init_data smdk6410_b_pwr_5v_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
.consumer_supplies = smdk6410_b_pwr_5v_consumers,
};
static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
.supply_name = "B_PWR_5V",
.microvolts = 5000000,
.init_data = &smdk6410_b_pwr_5v_data,
};
static struct platform_device smdk6410_b_pwr_5v = {
.name = "reg-fixed-voltage",
.id = -1,
.dev = {
.platform_data = &smdk6410_b_pwr_5v_pdata,
},
};
#endif
static struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
......@@ -198,6 +236,10 @@ static struct platform_device *smdk6410_devices[] __initdata = {
&s3c_device_fb,
&s3c_device_usb,
&s3c_device_usb_hsotg,
#ifdef CONFIG_REGULATOR
&smdk6410_b_pwr_5v,
#endif
&smdk6410_lcd_powerdev,
&smdk6410_smsc911x,
......@@ -232,6 +274,14 @@ static struct regulator_init_data wm8350_dcdc3_data = {
};
/* USB, EXT, PCM, ADC/DAC, USB, MMC */
static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
{
/* WM8580 */
.supply = "DVDD",
.dev_name = "0-001b",
},
};
static struct regulator_init_data wm8350_dcdc4_data = {
.constraints = {
.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
......@@ -239,6 +289,8 @@ static struct regulator_init_data wm8350_dcdc4_data = {
.max_uV = 3000000,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
.consumer_supplies = wm8350_dcdc4_consumers,
};
/* ARM core */
......
arch/arm/mach-s5pc100/Kconfig
View file @ 602fd7c3
......@@ -14,9 +14,23 @@ config CPU_S5PC100
help
Enable S5PC100 CPU support
config S5PC100_SETUP_SDHCI
bool
select S5PC1XX_SETUP_SDHCI_GPIO
help
Internal helper functions for S5PC100 based SDHCI systems
config MACH_SMDKC100
bool "SMDKC100"
select CPU_S5PC100
select S3C_DEV_FB
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S5PC1XX_SETUP_I2C0
select S5PC1XX_SETUP_I2C1
select S5PC1XX_SETUP_FB_24BPP
select S5PC100_SETUP_SDHCI
help
Machine support for the Samsung SMDKC100
arch/arm/mach-s5pc100/Makefile
View file @ 602fd7c3
......@@ -13,5 +13,9 @@ obj- :=
obj-$(CONFIG_CPU_S5PC100) += cpu.o
# Helper and device support
obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
# machine support
obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
arch/arm/mach-s5pc100/cpu.c
View file @ 602fd7c3
......@@ -22,6 +22,8 @@
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <asm/proc-fns.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
......@@ -32,6 +34,7 @@
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/regs-power.h>
#include <plat/cpu.h>
#include <plat/devs.h>
......@@ -45,6 +48,23 @@
static struct map_desc s5pc100_iodesc[] __initdata = {
};
static void s5pc100_idle(void)
{
unsigned long tmp;
tmp = __raw_readl(S5PC100_PWR_CFG);
tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
__raw_writel(tmp, S5PC100_PWR_CFG);
tmp = __raw_readl(S5PC100_OTHERS);
tmp |= S5PC100_PMU_INT_DISABLE;
__raw_writel(tmp, S5PC100_OTHERS);
cpu_do_idle();
}
/* s5pc100_map_io
*
* register the standard cpu IO areas
......@@ -55,6 +75,13 @@ void __init s5pc100_map_io(void)
iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
/* initialise device information early */
s5pc100_default_sdhci0();
s5pc100_default_sdhci1();
s5pc100_default_sdhci2();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
}
void __init s5pc100_init_clocks(int xtal)
......@@ -93,5 +120,7 @@ int __init s5pc100_init(void)
{
printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
s5pc1xx_idle = s5pc100_idle;
return sysdev_register(&s5pc100_sysdev);
}
arch/arm/mach-s5pc100/include/mach/gpio.h
View file @ 602fd7c3
......@@ -18,40 +18,45 @@
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S5PC1XX_GPIO_A0_NR (8)
#define S5PC1XX_GPIO_A1_NR (5)
#define S5PC1XX_GPIO_B_NR (8)
#define S5PC1XX_GPIO_C_NR (5)
#define S5PC1XX_GPIO_D_NR (7)
#define S5PC1XX_GPIO_E0_NR (8)
#define S5PC1XX_GPIO_E1_NR (6)
#define S5PC1XX_GPIO_F0_NR (8)
#define S5PC1XX_GPIO_F1_NR (8)
#define S5PC1XX_GPIO_F2_NR (8)
#define S5PC1XX_GPIO_F3_NR (4)
#define S5PC1XX_GPIO_G0_NR (8)
#define S5PC1XX_GPIO_G1_NR (3)
#define S5PC1XX_GPIO_G2_NR (7)
#define S5PC1XX_GPIO_G3_NR (7)
#define S5PC1XX_GPIO_H0_NR (8)
#define S5PC1XX_GPIO_H1_NR (8)
#define S5PC1XX_GPIO_H2_NR (8)
#define S5PC1XX_GPIO_H3_NR (8)
#define S5PC1XX_GPIO_I_NR (8)
#define S5PC1XX_GPIO_J0_NR (8)
#define S5PC1XX_GPIO_J1_NR (5)
#define S5PC1XX_GPIO_J2_NR (8)
#define S5PC1XX_GPIO_J3_NR (8)
#define S5PC1XX_GPIO_J4_NR (4)
#define S5PC1XX_GPIO_K0_NR (8)
#define S5PC1XX_GPIO_K1_NR (6)
#define S5PC1XX_GPIO_K2_NR (8)
#define S5PC1XX_GPIO_K3_NR (8)
#define S5PC1XX_GPIO_MP00_NR (8)
#define S5PC1XX_GPIO_MP01_NR (8)
#define S5PC1XX_GPIO_MP02_NR (8)
#define S5PC1XX_GPIO_MP03_NR (8)
#define S5PC1XX_GPIO_MP04_NR (5)
#define S5PC100_GPIO_A0_NR (8)
#define S5PC100_GPIO_A1_NR (5)
#define S5PC100_GPIO_B_NR (8)
#define S5PC100_GPIO_C_NR (5)
#define S5PC100_GPIO_D_NR (7)
#define S5PC100_GPIO_E0_NR (8)
#define S5PC100_GPIO_E1_NR (6)
#define S5PC100_GPIO_F0_NR (8)
#define S5PC100_GPIO_F1_NR (8)
#define S5PC100_GPIO_F2_NR (8)
#define S5PC100_GPIO_F3_NR (4)
#define S5PC100_GPIO_G0_NR (8)
#define S5PC100_GPIO_G1_NR (3)
#define S5PC100_GPIO_G2_NR (7)
#define S5PC100_GPIO_G3_NR (7)
#define S5PC100_GPIO_H0_NR (8)
#define S5PC100_GPIO_H1_NR (8)
#define S5PC100_GPIO_H2_NR (8)
#define S5PC100_GPIO_H3_NR (8)
#define S5PC100_GPIO_I_NR (8)
#define S5PC100_GPIO_J0_NR (8)
#define S5PC100_GPIO_J1_NR (5)
#define S5PC100_GPIO_J2_NR (8)
#define S5PC100_GPIO_J3_NR (8)
#define S5PC100_GPIO_J4_NR (4)
#define S5PC100_GPIO_K0_NR (8)
#define S5PC100_GPIO_K1_NR (6)
#define S5PC100_GPIO_K2_NR (8)
#define S5PC100_GPIO_K3_NR (8)
#define S5PC100_GPIO_L0_NR (8)
#define S5PC100_GPIO_L1_NR (8)
#define S5PC100_GPIO_L2_NR (8)
#define S5PC100_GPIO_L3_NR (8)
#define S5PC100_GPIO_L4_NR (8)
#define S5PC100_GPIO_MP00_NR (8)
#define S5PC100_GPIO_MP01_NR (8)
#define S5PC100_GPIO_MP02_NR (8)
#define S5PC100_GPIO_MP03_NR (8)
#define S5PC100_GPIO_MP04_NR (5)
/* GPIO bank numbes */
......@@ -64,83 +69,94 @@
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number {
S5PC1XX_GPIO_A0_START = 0,
S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
S5PC100_GPIO_A0_START = 0,
S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
};
/* S5PC1XX GPIO number definitions. */
#define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr))
#define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr))
#define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr))
#define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr))
#define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr))
#define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr))
#define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr))
#define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr))
#define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr))
#define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr))
#define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr))
#define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr))
#define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr))
#define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr))
#define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr))
#define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr))
#define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr))
#define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr))
#define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr))
#define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr))
#define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr))
#define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr))
#define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr))
#define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr))
#define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr))
#define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr))
#define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr))
#define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr))
#define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr))
#define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr))
#define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr))
#define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr))
#define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr))
#define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr))
/* S5PC100 GPIO number definitions. */
#define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr))
#define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr))
#define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr))
#define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr))
#define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr))
#define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr))
#define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr))
#define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr))
#define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr))
#define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr))
#define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr))
#define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr))
#define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr))
#define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr))
#define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr))
#define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr))
#define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr))
#define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr))
#define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr))
#define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr))
#define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr))
#define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr))
#define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr))
#define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr))
#define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr))
#define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr))
#define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr))
#define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr))
#define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr))
#define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr))
#define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr))
#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr))
#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr))
#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr))
#define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr))
#define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr))
#define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr))
#define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr))
#define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr))
#define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr))
/* the end of the S5PC1XX specific gpios */
#define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
#define S3C_GPIO_END S5PC1XX_GPIO_END
/* It used the end of the S5PC1XX gpios */
#define S3C_GPIO_END S5PC100_GPIO_END
/* define the number of gpios we need to the one after the MP04() range */
#define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
#include <asm-generic/gpio.h>
arch/arm/mach-s5pc100/include/mach/irqs.h
View file @ 602fd7c3
......@@ -11,4 +11,9 @@
#include <plat/irqs.h>
/* LCD */
#define IRQ_LCD_FIFO IRQ_LCD0
#define IRQ_LCD_VSYNC IRQ_LCD1
#define IRQ_LCD_SYSTEM IRQ_LCD2
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s5pc100/include/mach/map.h
View file @ 602fd7c3
......@@ -17,6 +17,19 @@
#include <plat/map-base.h>
/*
* map-base.h has already defined virtual memory address
* S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
* S3C_VA_SYS S3C_ADDR(0x00100000) system control
* S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
* S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
* S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
* S3C_VA_UART S3C_ADDR(0x01000000) UART
*
* S5PC100 specific virtual memory address can be defined here
* S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
*
*/
/* Chip ID */
#define S5PC100_PA_CHIPID (0xE0000000)
......@@ -24,13 +37,20 @@
#define S5PC1XX_VA_CHIPID S3C_VA_SYS
/* System */
#define S5PC100_PA_SYS (0xE0100000)
#define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0)
#define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000)
#define S5PC100_PA_CLK (0xE0100000)
#define S5PC100_PA_CLK_OTHER (0xE0200000)
#define S5PC100_PA_PWR (0xE0108000)
#define S5PC1XX_PA_CLK S5PC100_PA_CLK
#define S5PC1XX_PA_PWR S5PC100_PA_PWR
#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER
#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000)
/* GPIO */
#define S5PC100_PA_GPIO (0xE0300000)
#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO
#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
/* Interrupt */
#define S5PC100_PA_VIC (0xE4000000)
......@@ -40,23 +60,64 @@
#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
/* DMA */
#define S5PC100_PA_MDMA (0xE8100000)
#define S5PC100_PA_PDMA0 (0xE9000000)
#define S5PC100_PA_PDMA1 (0xE9200000)
/* Timer */
#define S5PC100_PA_TIMER (0xEA000000)
#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER
#define S5PC1XX_VA_TIMER S3C_VA_TIMER
/* RTC */
#define S5PC100_PA_RTC (0xEA300000)
/* UART */
#define S5PC100_PA_UART (0xEC000000)
#define S5PC1XX_PA_UART S5PC100_PA_UART
#define S5PC1XX_VA_UART S3C_VA_UART
/* IIC */
#define S5PC100_PA_IIC (0xEC100000)
/* I2C */
#define S5PC100_PA_I2C (0xEC100000)
#define S5PC100_PA_I2C1 (0xEC200000)
/* USB HS OTG */
#define S5PC100_PA_USB_HSOTG (0xED200000)
#define S5PC100_PA_USB_HSPHY (0xED300000)
/* SD/MMC */
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0)
#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1)
#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2)
/* LCD */
#define S5PC100_PA_FB (0xEE000000)
/* Multimedia */
#define S5PC100_PA_G2D (0xEE800000)
#define S5PC100_PA_JPEG (0xEE500000)
#define S5PC100_PA_ROTATOR (0xEE100000)
#define S5PC100_PA_G3D (0xEF000000)
/* I2S */
#define S5PC100_PA_I2S0 (0xF2000000)
#define S5PC100_PA_I2S1 (0xF2100000)
#define S5PC100_PA_I2S2 (0xF2200000)
/* KEYPAD */
#define S5PC100_PA_KEYPAD (0xF3100000)
/* ADC & TouchScreen */
#define S5PC100_PA_TSADC (0xF3000000)
/* ETC */
#define S5PC100_PA_SDRAM (0x20000000)
#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM
/* compatibility defines. */
#define S3C_PA_RTC S5PC100_PA_RTC
#define S3C_PA_UART S5PC100_PA_UART
#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0)
#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400)
......@@ -67,9 +128,23 @@
#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
#define S3C_UART_OFFSET 0x400
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S3C_PA_FB S5PC100_PA_FB
#define S3C_PA_G2D S5PC100_PA_G2D
#define S3C_PA_G3D S5PC100_PA_G3D
#define S3C_PA_JPEG S5PC100_PA_JPEG
#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0)
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000)
#define S3C_PA_IIC S5PC100_PA_IIC
#define S3C_PA_IIC S5PC100_PA_I2C
#define S3C_PA_IIC1 S5PC100_PA_I2C1
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_TSADC S5PC100_PA_TSADC
#endif /* __ASM_ARCH_C100_MAP_H */
arch/arm/mach-s5pc100/include/mach/regs-fb.h 0 → 100644
View file @ 602fd7c3
/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
*
* Copyright 2009 Samsung Electronics Co.
* Pawel Osciak <p.osciak@samsung.com>
*
* Framebuffer register definitions for Samsung S5PC100.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_FB_H
#define __ASM_ARCH_REGS_FB_H __FILE__
#include <plat/regs-fb-v4.h>
/* VP1 interface timing control */
#define VP1CON0 (0x118)
#define VP1_RATECON_EN (1 << 31)
#define VP1_CLKRATE_MASK (0xff)
#define VP1CON1 (0x11c)
#define VP1_VTREGCON_EN (1 << 31)
#define VP1_VBPD_MASK (0xfff)
#define VP1_VBPD_SHIFT (16)
#define WPALCON_H (0x19c)
#define WPALCON_L (0x1a0)
/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
* different for WPAL2-4
*/
/* In WPALCON_L (aka WPALCON) */
#define WPALCON_W1PAL_32BPP_A888 (0x7 << 3)
#define WPALCON_W0PAL_32BPP_A888 (0x7 << 0)
/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
* e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
*/
#define WPALCON_L_WxPAL_L_MASK (0x1)
#define WPALCON_L_W2PAL_L_SHIFT (6)
#define WPALCON_L_W3PAL_L_SHIFT (7)
#define WPALCON_L_W4PAL_L_SHIFT (8)
#define WPALCON_L_WxPAL_H_MASK (0x3)
#define WPALCON_H_W2PAL_H_SHIFT (9)
#define WPALCON_H_W3PAL_H_SHIFT (13)
#define WPALCON_H_W4PAL_H_SHIFT (17)
/* Per-window alpha value registers */
/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
* for windows 1-4 alpha values consist of two parts, the 4 low bits are
* taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
* e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
*/
#define VIDWxALPHA0(_win) (0x200 + (_win * 8))
#define VIDWxALPHA1(_win) (0x204 + (_win * 8))
/* Only for window 0 in VIDW0ALPHAx. */
#define VIDW0ALPHAx_R(_x) ((_x) << 16)
#define VIDW0ALPHAx_R_MASK (0xff << 16)
#define VIDW0ALPHAx_R_SHIFT (16)
#define VIDW0ALPHAx_G(_x) ((_x) << 8)
#define VIDW0ALPHAx_G_MASK (0xff << 8)
#define VIDW0ALPHAx_G_SHIFT (8)
#define VIDW0ALPHAx_B(_x) ((_x) << 0)
#define VIDW0ALPHAx_B_MASK (0xff << 0)
#define VIDW0ALPHAx_B_SHIFT (0)
/* Low 4 bits of alpha0-1 for windows 1-4 */
#define VIDW14ALPHAx_R_L(_x) ((_x) << 16)
#define VIDW14ALPHAx_R_L_MASK (0xf << 16)
#define VIDW14ALPHAx_R_L_SHIFT (16)
#define VIDW14ALPHAx_G_L(_x) ((_x) << 8)
#define VIDW14ALPHAx_G_L_MASK (0xf << 8)
#define VIDW14ALPHAx_G_L_SHIFT (8)
#define VIDW14ALPHAx_B_L(_x) ((_x) << 0)
#define VIDW14ALPHAx_B_L_MASK (0xf << 0)
#define VIDW14ALPHAx_B_L_SHIFT (0)
/* Per-window blending equation control registers */
#define BLENDEQx(_win) (0x244 + ((_win) * 4))
#define BLENDEQ1 (0x244)
#define BLENDEQ2 (0x248)
#define BLENDEQ3 (0x24c)
#define BLENDEQ4 (0x250)
#define BLENDEQx_Q_FUNC(_x) ((_x) << 18)
#define BLENDEQx_Q_FUNC_MASK (0xf << 18)
#define BLENDEQx_P_FUNC(_x) ((_x) << 12)
#define BLENDEQx_P_FUNC_MASK (0xf << 12)
#define BLENDEQx_B_FUNC(_x) ((_x) << 6)
#define BLENDEQx_B_FUNC_MASK (0xf << 6)
#define BLENDEQx_A_FUNC(_x) ((_x) << 0)
#define BLENDEQx_A_FUNC_MASK (0xf << 0)
#define BLENDCON (0x260)
#define BLENDCON_8BIT_ALPHA (1 << 0)
/* Per-window palette base addresses (start of palette memory).
* Each window palette area consists of 256 32-bit entries.
* START is the first address (entry 0th), END is the address of 255th entry.
*/
#define WIN0_PAL_BASE (0x2400)
#define WIN0_PAL_END (0x27fc)
#define WIN1_PAL_BASE (0x2800)
#define WIN1_PAL_END (0x2bfc)
#define WIN2_PAL_BASE (0x2c00)
#define WIN2_PAL_END (0x2ffc)
#define WIN3_PAL_BASE (0x3000)
#define WIN3_PAL_END (0x33fc)
#define WIN4_PAL_BASE (0x3400)
#define WIN4_PAL_END (0x37fc)
#define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4))
#define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4))
#define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4))
#define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4))
#define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4))
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
case 0: return WIN0_PAL(reg);
case 1: return WIN1_PAL(reg);
case 2: return WIN2_PAL(reg);
case 3: return WIN3_PAL(reg);
case 4: return WIN4_PAL(reg);
}
BUG();
}
#endif /* __ASM_ARCH_REGS_FB_H */
arch/arm/mach-s5pc100/include/mach/system.h
View file @ 602fd7c3
......@@ -11,14 +11,21 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
#include <linux/io.h>
#include <mach/map.h>
#include <plat/regs-clock.h>
void (*s5pc1xx_idle)(void);
static void arch_idle(void)
{
/* nothing here yet */
if (s5pc1xx_idle)
s5pc1xx_idle();
}
static void arch_reset(char mode, const char *cmd)
{
/* nothing here yet */
__raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
return;
}
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s5pc100/mach-smdkc100.c
View file @ 602fd7c3
......@@ -27,16 +27,22 @@
#include <asm/mach/map.h>
#include <mach/map.h>
#include <mach/regs-fb.h>
#include <video/platform_lcd.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-gpio.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/s5pc100.h>
#include <plat/fb.h>
#include <plat/iic.h>
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
......@@ -73,9 +79,78 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
},
};
/* I2C0 */
static struct i2c_board_info i2c_devs0[] __initdata = {
};
/* I2C1 */
static struct i2c_board_info i2c_devs1[] __initdata = {
};
/* LCD power controller */
static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
/* backlight */
gpio_direction_output(S5PC100_GPD(0), power);
if (power) {
/* module reset */
gpio_direction_output(S5PC100_GPH0(6), 1);
mdelay(100);
gpio_direction_output(S5PC100_GPH0(6), 0);
mdelay(10);
gpio_direction_output(S5PC100_GPH0(6), 1);
mdelay(10);
}
}
static struct plat_lcd_data smdkc100_lcd_power_data = {
.set_power = smdkc100_lcd_power_set,
};
static struct platform_device smdkc100_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdkc100_lcd_power_data,
};
/* Frame Buffer */
static struct s3c_fb_pd_win smdkc100_fb_win0 = {
/* this is to ensure we use win0 */
.win_mode = {
.refresh = 70,
.pixclock = (8+13+3+800)*(7+5+1+480),
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
};
static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
.win[0] = &smdkc100_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
.setup_gpio = s5pc100_fb_gpio_setup_24bpp,
};
static struct map_desc smdkc100_iodesc[] = {};
static struct platform_device *smdkc100_devices[] __initdata = {
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&smdkc100_lcd_powerdev,
};
static void __init smdkc100_map_io(void)
......@@ -87,12 +162,24 @@ static void __init smdkc100_map_io(void)
static void __init smdkc100_machine_init(void)
{
/* I2C */
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
s3c_fb_set_platdata(&smdkc100_lcd_pdata);
/* LCD init */
gpio_request(S5PC100_GPD(0), "GPD");
gpio_request(S5PC100_GPH0(6), "GPH0");
smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
}
MACHINE_START(SMDKC100, "SMDKC100")
/* Maintainer: Byungho Min <bhmin@samsung.com> */
.phys_io = S5PC1XX_PA_UART & 0xfff00000,
.phys_io = S5PC100_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S5PC100_PA_SDRAM + 0x100,
......
arch/arm/mach-s5pc100/setup-sdhci.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
*
* Copyright 2008 Samsung Electronics
*
* S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* Based on mach-s3c6410/setup-sdhci.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s5pc100_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
/* [2] = "mmc_bus", not yet succesfuuly used yet */
/* [3] = "48m", - note not succesfully used yet */
};
void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything acording to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
arch/arm/plat-s3c/Kconfig
View file @ 602fd7c3
......@@ -159,6 +159,12 @@ config S3C_GPIO_CFG_S3C64XX
Internal configuration to enable S3C64XX style GPIO configuration
functions.
config S5P_GPIO_CFG_S5PC1XX
bool
help
Internal configuration to enable S5PC1XX style GPIO configuration
functions.
# DMA
config S3C_DMA
......@@ -178,6 +184,11 @@ config S3C_DEV_HSMMC1
help
Compile in platform device definitions for HSMMC channel 1
config S3C_DEV_HSMMC2
bool
help
Compile in platform device definitions for HSMMC channel 2
config S3C_DEV_I2C1
bool
help
......
arch/arm/plat-s3c/Makefile
View file @ 602fd7c3
......@@ -36,6 +36,7 @@ obj-$(CONFIG_HAVE_PWM) += pwm.o
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
......
arch/arm/plat-s3c/clock.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/clock.c
*
* Copyright (c) 2004-2005 Simtec Electronics
* Copyright 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Core clock control support
......@@ -337,7 +337,7 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
int __init s3c24xx_register_baseclocks(unsigned long xtal)
{
printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
clk_xtal.rate = xtal;
......
arch/arm/plat-s3c/dev-hsmmc2.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c/dev-hsmmc2.c
*
* Copyright (c) 2009 Samsung Electronics
* Copyright (c) 2009 Maurus Cuelenaere
*
* Based on arch/arm/plat-s3c/dev-hsmmc1.c
* original file Copyright (c) 2008 Simtec Electronics
*
* S3C series device definition for hsmmc device 2
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc2_resource[] = {
[0] = {
.start = S3C_PA_HSMMC2,
.end = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC2,
.end = IRQ_HSMMC2,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc2 = {
.name = "s3c-sdhci",
.id = 2,
.num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
.resource = s3c_hsmmc2_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc2_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc2_def_platdata,
},
};
void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}
arch/arm/plat-s3c/dev-i2c0.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c/dev-i2c0.c
*
* Copyright 2008,2009 Simtec Electronics
* Copyright 2008-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
......
arch/arm/plat-s3c/dev-i2c1.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c/dev-i2c1.c
*
* Copyright 2008,2009 Simtec Electronics
* Copyright 2008-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
......
arch/arm/plat-s3c/dev-nand.c
View file @ 602fd7c3
......@@ -9,8 +9,12 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <mach/map.h>
#include <plat/devs.h>
#include <plat/nand.h>
static struct resource s3c_nand_resource[] = {
[0] = {
......@@ -28,3 +32,96 @@ struct platform_device s3c_device_nand = {
};
EXPORT_SYMBOL(s3c_device_nand);
/**
* s3c_nand_copy_set() - copy nand set data
* @set: The new structure, directly copied from the old.
*
* Copy all the fields from the NAND set field from what is probably __initdata
* to new kernel memory. The code returns 0 if the copy happened correctly or
* an error code for the calling function to display.
*
* Note, we currently do not try and look to see if we've already copied the
* data in a previous set.
*/
static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
{
void *ptr;
int size;
size = sizeof(struct mtd_partition) * set->nr_partitions;
if (size) {
ptr = kmemdup(set->partitions, size, GFP_KERNEL);
set->partitions = ptr;
if (!ptr)
return -ENOMEM;
}
size = sizeof(int) * set->nr_chips;
if (size) {
ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
set->nr_map = ptr;
if (!ptr)
return -ENOMEM;
}
if (set->ecc_layout) {
ptr = kmemdup(set->ecc_layout,
sizeof(struct nand_ecclayout), GFP_KERNEL);
set->ecc_layout = ptr;
if (!ptr)
return -ENOMEM;
}
return 0;
}
void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
{
struct s3c2410_platform_nand *npd;
int size;
int ret;
/* note, if we get a failure in allocation, we simply drop out of the
* function. If there is so little memory available at initialisation
* time then there is little chance the system is going to run.
*/
npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL);
if (!npd) {
printk(KERN_ERR "%s: failed copying platform data\n", __func__);
return;
}
/* now see if we need to copy any of the nand set data */
size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
if (size) {
struct s3c2410_nand_set *from = npd->sets;
struct s3c2410_nand_set *to;
int i;
to = kmemdup(from, size, GFP_KERNEL);
npd->sets = to; /* set, even if we failed */
if (!to) {
printk(KERN_ERR "%s: no memory for sets\n", __func__);
return;
}
for (i = 0; i < npd->nr_sets; i++) {
ret = s3c_nand_copy_set(to);
if (!ret) {
printk(KERN_ERR "%s: failed to copy set %d\n",
__func__, i);
return;
}
to++;
}
}
}
EXPORT_SYMBOL_GPL(s3c_nand_set_platdata);
arch/arm/plat-s3c/dma.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c/dma.c
*
* Copyright (c) 2003-2005,2006,2009 Simtec Electronics
* Copyright (c) 2003-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
......
arch/arm/plat-s3c/include/plat/audio-simtec.h
View file @ 602fd7c3
......@@ -33,5 +33,5 @@ struct s3c24xx_audio_simtec_pdata {
void (*startup)(void);
};
extern int simtec_audio_add(const char *codec_name,
extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
struct s3c24xx_audio_simtec_pdata *pdata);
arch/arm/plat-s3c/include/plat/cpu-freq.h
View file @ 602fd7c3
/* arch/arm/plat-s3c/include/plat/cpu-freq.h
*
* Copyright (c) 2006,2007 Simtec Electronics
* Copyright (c) 2006-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c/include/plat/cpu.h
View file @ 602fd7c3
......@@ -12,6 +12,9 @@
/* todo - fix when rmk changes iodescs to use `void __iomem *` */
#ifndef __SAMSUNG_PLAT_CPU_H
#define __SAMSUNG_PLAT_CPU_H
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
#ifndef MHZ
......@@ -73,3 +76,6 @@ extern struct sysdev_class s3c2443_sysclass;
extern struct sysdev_class s3c6410_sysclass;
extern struct sysdev_class s3c64xx_sysclass;
extern void (*s5pc1xx_idle)(void);
#endif
arch/arm/plat-s3c/include/plat/dma.h
View file @ 602fd7c3
/* arch/arm/plat-s3c/include/plat/dma.h
*
* Copyright (C) 2003,2004,2006 Simtec Electronics
* Copyright (C) 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C DMA support
......
arch/arm/plat-s3c/include/plat/fb.h
View file @ 602fd7c3
......@@ -70,4 +70,11 @@ extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
*/
extern void s3c64xx_fb_gpio_setup_24bpp(void);
/**
* s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
*/
extern void s5pc100_fb_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */
arch/arm/plat-s3c/include/plat/iic.h
View file @ 602fd7c3
/* arch/arm/plat-s3c/include/plat/iic.h
*
* Copyright 2004,2009 Simtec Electronics
* Copyright 2004-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller platform_device info
......
arch/arm/plat-s3c/include/plat/nand.h
View file @ 602fd7c3
......@@ -55,3 +55,11 @@ struct s3c2410_platform_nand {
int chip);
};
/**
* s3c_nand_set_platdata() - register NAND platform data.
* @nand: The NAND platform data to register with s3c_device_nand.
*
* This function copies the given NAND platform data, @nand and registers
* it with the s3c_device_nand. This allows @nand to be __initdata.
*/
extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
arch/arm/plat-s3c/include/plat/regs-fb-v4.h 0 → 100644
View file @ 602fd7c3
/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards and specifically the S3C64XX series
* S3C6400 and S3C6410.
*
* The file contains the cpu specific items which change between whichever
* architecture is selected. See <plat/regs-fb.h> for the core definitions
* that are the same.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* include the core definitions here, in case we really do need to
* override them at a later date.
*/
#include <plat/regs-fb.h>
#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
/* Window position controls */
#define WINCON(_win) (0x20 + ((_win) * 4))
/* OSD1 and OSD4 do not have register D */
#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
#define VIDINTCON0 (0x130)
#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
/* WINCONx */
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
#define WINCONx_ENLOCAL (1 << 22)
#define WINCONx_BUFSTATUS (1 << 21)
#define WINCONx_BUFSEL (1 << 20)
#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_YCbCr (1 << 13)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_BLD_PIX (1 << 6)
#define WINCON2_ALPHA_SEL (1 << 1)
#define WINCON2_BPPMODE_MASK (0xf << 2)
#define WINCON2_BPPMODE_SHIFT (2)
#define WINCON2_BPPMODE_1BPP (0x0 << 2)
#define WINCON2_BPPMODE_2BPP (0x1 << 2)
#define WINCON2_BPPMODE_4BPP (0x2 << 2)
#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
#define WINCON3_BLD_PIX (1 << 6)
#define WINCON3_ALPHA_SEL (1 << 1)
#define WINCON3_BPPMODE_MASK (0xf << 2)
#define WINCON3_BPPMODE_SHIFT (2)
#define WINCON3_BPPMODE_1BPP (0x0 << 2)
#define WINCON3_BPPMODE_2BPP (0x1 << 2)
#define WINCON3_BPPMODE_4BPP (0x2 << 2)
#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define DITHMODE (0x170)
#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define DITHMODE_R_POS_MASK (0x3 << 5)
#define DITHMODE_R_POS_SHIFT (5)
#define DITHMODE_R_POS_8BIT (0x0 << 5)
#define DITHMODE_R_POS_6BIT (0x1 << 5)
#define DITHMODE_R_POS_5BIT (0x2 << 5)
#define DITHMODE_G_POS_MASK (0x3 << 3)
#define DITHMODE_G_POS_SHIFT (3)
#define DITHMODE_G_POS_8BIT (0x0 << 3)
#define DITHMODE_G_POS_6BIT (0x1 << 3)
#define DITHMODE_G_POS_5BIT (0x2 << 3)
#define DITHMODE_B_POS_MASK (0x3 << 1)
#define DITHMODE_B_POS_SHIFT (1)
#define DITHMODE_B_POS_8BIT (0x0 << 1)
#define DITHMODE_B_POS_6BIT (0x1 << 1)
#define DITHMODE_B_POS_5BIT (0x2 << 1)
#define DITHMODE_DITH_EN (1 << 0)
#define WPALCON (0x1A0)
/* Palette control */
/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
* but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
/* system specific implementation code for palette sizes, and other
* information that changes depending on which architecture is being
* compiled.
*/
/* return true if window _win has OSD register D */
#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
{
if (win < 2)
return 256;
if (win < 4)
return 16;
if (win == 4)
return 4;
BUG(); /* shouldn't get here */
}
static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
{
/* all windows can do 1/2 bpp */
if ((bpp == 25 || bpp == 19) && win == 0)
return 0; /* win 0 does not have 19 or 25bpp modes */
if (bpp == 4 && win == 4)
return 0;
if (bpp == 8 && (win >= 3))
return 0; /* win 3/4 cannot do 8bpp in any mode */
return 1;
}
static inline int s3c_fb_pal_is16(unsigned int window)
{
return window > 1;
}
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
struct fb_bitfield b;
struct fb_bitfield a;
};
static inline void s3c_fb_init_palette(unsigned int window,
struct s3c_fb_palette *palette)
{
if (window < 2) {
/* Windows 0/1 are 8/8/8 or A/8/8/8 */
palette->r.offset = 16;
palette->r.length = 8;
palette->g.offset = 8;
palette->g.length = 8;
palette->b.offset = 0;
palette->b.length = 8;
} else {
/* currently we assume RGB 5/6/5 */
palette->r.offset = 11;
palette->r.length = 5;
palette->g.offset = 5;
palette->g.length = 6;
palette->b.offset = 0;
palette->b.length = 5;
}
}
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
* 0010 4(P) 4(P) 4(P) 4(P) -none-
* 0011 8(P) 8(P) -none- -none- -none-
* 0100 -none- 8(A232) 8(A232) -none- -none-
* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
* 1110 -none- -none- -none- -none- -none-
* 1111 -none- -none- -none- -none- -none-
*/
arch/arm/plat-s3c/include/plat/regs-nand.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
*
* Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
* Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/plat-s3c/include/plat/regs-serial.h
View file @ 602fd7c3
......@@ -6,7 +6,7 @@
*
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
*
* Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
* Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
*
* Adapted from:
*
......
arch/arm/plat-s3c/include/plat/sdhci.h
View file @ 602fd7c3
......@@ -57,6 +57,7 @@ struct s3c_sdhci_platdata {
*/
extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
/* Default platform data, exported so that per-cpu initialisation can
* set the correct one when there are more than one cpu type selected.
......@@ -64,11 +65,16 @@ extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
/* Helper function availablity */
extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
/* S3C6400 SDHCI setup */
......@@ -103,6 +109,17 @@ static inline void s3c6400_default_sdhci1(void)
static inline void s3c6400_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#ifdef CONFIG_S3C_DEV_HSMMC2
static inline void s3c6400_default_sdhci2(void)
{
s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
}
#else
static inline void s3c6400_default_sdhci2(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC2 */
#else
static inline void s3c6400_default_sdhci0(void) { }
static inline void s3c6400_default_sdhci1(void) { }
......@@ -140,9 +157,70 @@ static inline void s3c6410_default_sdhci1(void)
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#ifdef CONFIG_S3C_DEV_HSMMC2
static inline void s3c6410_default_sdhci2(void)
{
s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci2(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC2 */
#else
static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C6410_SETUP_SDHCI */
/* S5PC100 SDHCI setup */
#ifdef CONFIG_S5PC100_SETUP_SDHCI
extern char *s5pc100_hsmmc_clksrcs[4];
extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
#ifdef CONFIG_S3C_DEV_HSMMC
static inline void s5pc100_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
}
#else
static inline void s5pc100_default_sdhci0(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s5pc100_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
}
#else
static inline void s5pc100_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#ifdef CONFIG_S3C_DEV_HSMMC2
static inline void s5pc100_default_sdhci2(void)
{
s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
}
#else
static inline void s5pc100_default_sdhci2(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#else
static inline void s5pc100_default_sdhci0(void) { }
static inline void s5pc100_default_sdhci1(void) { }
static inline void s5pc100_default_sdhci2(void) { }
#endif /* CONFIG_S5PC100_SETUP_SDHCI */
#endif /* __PLAT_S3C_SDHCI_H */
arch/arm/plat-s3c/pm-check.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c/pm-check.c
* originally in linux/arch/arm/plat-s3c24xx/pm.c
*
* Copyright (c) 2004,2006,2008 Simtec Electronics
* Copyright (c) 2004-2008 Simtec Electronics
* http://armlinux.simtec.co.uk
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c/pm.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c/pm.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2004,2006,2008 Simtec Electronics
* Copyright 2004-2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
......
arch/arm/plat-s3c24xx/Kconfig
View file @ 602fd7c3
......@@ -178,4 +178,11 @@ config MACH_SMDK
help
Common machine code for SMDK2410 and SMDK2440
config S3C24XX_SIMTEC_AUDIO
bool
depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
default y
help
Add audio devices for common Simtec S3C24XX boards
endif
arch/arm/plat-s3c24xx/Makefile
View file @ 602fd7c3
......@@ -55,3 +55,4 @@ obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10) += spi-bus1-gpd8_9_10.o
# machine common support
obj-$(CONFIG_MACH_SMDK) += common-smdk.o
obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o
arch/arm/plat-s3c24xx/clock-dclk.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
*
* Copyright (c) 2004,2008 Simtec Electronics
* Copyright (c) 2004-2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
......
arch/arm/plat-s3c24xx/common-smdk.c
View file @ 602fd7c3
......@@ -198,7 +198,7 @@ void __init smdk_machine_init(void)
if (machine_is_smdk2443())
smdk_nand_info.twrph0 = 50;
s3c_device_nand.dev.platform_data = &smdk_nand_info;
s3c_nand_set_platdata(&smdk_nand_info);
platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
......
arch/arm/plat-s3c24xx/cpu-freq.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
*
* Copyright (c) 2006,2007,2008 Simtec Electronics
* Copyright (c) 2006-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c24xx/dma.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/dma.c
*
* Copyright (c) 2003-2005,2006 Simtec Electronics
* Copyright 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 DMA core
......@@ -1310,7 +1310,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
int channel;
int ret;
printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
dma_channels = channels;
......
arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
View file @ 602fd7c3
/* arch/arm/plat-s3c/include/plat/cpu-freq.h
*
* Copyright (c) 2006,2007,2009 Simtec Electronics
* Copyright (c) 2006-2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c24xx/include/plat/mci.h
View file @ 602fd7c3
#ifndef _ARCH_MCI_H
#define _ARCH_MCI_H
/**
* struct s3c24xx_mci_pdata - sd/mmc controller platform data
* @no_wprotect: Set this to indicate there is no write-protect switch.
* @no_detect: Set this if there is no detect switch.
* @wprotect_invert: Invert the default sense of the write protect switch.
* @detect_invert: Invert the default sense of the write protect switch.
* @use_dma: Set to allow the use of DMA.
* @gpio_detect: GPIO number for the card detect line.
* @gpio_wprotect: GPIO number for the write protect line.
* @ocr_avail: The mask of the available power states, non-zero to use.
* @set_power: Callback to control the power mode.
*
* The @gpio_detect is used for card detection when @no_wprotect is unset,
* and the default sense is that 0 returned from gpio_get_value() means
* that a card is inserted. If @detect_invert is set, then the value from
* gpio_get_value() is inverted, which makes 1 mean card inserted.
*
* The driver will use @gpio_wprotect to signal whether the card is write
* protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
* means the card is read/write, and 1 means read-only. The @wprotect_invert
* will invert the value returned from gpio_get_value().
*
* Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
* to a non-zero value, otherwise the default of 3.2-3.4V is used.
*/
struct s3c24xx_mci_pdata {
unsigned int no_wprotect : 1;
unsigned int no_detect : 1;
......
arch/arm/plat-s3c24xx/include/plat/regs-dma.h
View file @ 602fd7c3
/* arch/arm/mach-s3c2410/include/mach/dma.h
*
* Copyright (C) 2003,2004,2006 Simtec Electronics
* Copyright (C) 2003-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C24XX DMA support
......
arch/arm/plat-s3c24xx/irq-pm.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/irq-om.c
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
......
arch/arm/plat-s3c24xx/irq.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/irq.c
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/plat-s3c24xx/pm-simtec.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/pm-simtec.c
*
* Copyright (c) 2004 Simtec Electronics
* Copyright 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://armlinux.simtec.co.uk/
......@@ -35,7 +35,7 @@
#include <plat/pm.h>
#define COPYRIGHT ", (c) 2005 Simtec Electronics"
#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
/* pm_simtec_init
*
......
arch/arm/plat-s3c24xx/pm.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/pm.c
*
* Copyright (c) 2004,2006 Simtec Electronics
* Copyright (c) 2004-2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Power Manager (Suspend-To-RAM) support
......
arch/arm/plat-s3c24xx/s3c2410-iotiming.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
*
* Copyright (c) 2006,2008,2009 Simtec Electronics
* Copyright (c) 2006-2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c24xx/s3c2412-iotiming.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
*
* Copyright (c) 2006,2008 Simtec Electronics
* Copyright (c) 2006-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
*
* Copyright (c) 2006,2008,2009 Simtec Electronics
* Copyright (c) 2006-2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@simtec.co.uk>
......
arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
View file @ 602fd7c3
/* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
*
* Copyright (c) 2006,2007 Simtec Electronics
* Copyright (c) 2006-2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
* Vincent Sanders <vince@arm.linux.org.uk>
......
arch/arm/plat-s3c24xx/s3c244x-clock.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
*
* Copyright (c) 2004-2005,2008 Simtec Electronics
* Copyright (c) 2004-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
......
arch/arm/plat-s3c24xx/s3c244x-irq.c
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
*
* Copyright (c) 2003,2004 Simtec Electronics
* Copyright (c) 2003-2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
......
arch/arm/plat-s3c24xx/simtec-audio.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s3c24xx/simtec-audio.c
*
* Copyright (c) 2009 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Audio setup for various Simtec S3C24XX implementations
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/io.h>
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
#include <plat/audio-simtec.h>
#include <plat/devs.h>
/* platform ops for audio */
static void simtec_audio_startup_lrroute(void)
{
unsigned int tmp;
unsigned long flags;
local_irq_save(flags);
tmp = __raw_readb(BAST_VA_CTRL1);
tmp &= ~BAST_CPLD_CTRL1_LRMASK;
tmp |= BAST_CPLD_CTRL1_LRCDAC;
__raw_writeb(tmp, BAST_VA_CTRL1);
local_irq_restore(flags);
}
static struct s3c24xx_audio_simtec_pdata simtec_audio_platdata;
static char our_name[32];
static struct platform_device simtec_audio_dev = {
.name = our_name,
.id = -1,
.dev = {
.parent = &s3c_device_iis.dev,
.platform_data = &simtec_audio_platdata,
},
};
int __init simtec_audio_add(const char *name, bool has_lr_routing,
struct s3c24xx_audio_simtec_pdata *spd)
{
if (!name)
name = "tlv320aic23";
snprintf(our_name, sizeof(our_name)-1, "s3c24xx-simtec-%s", name);
/* copy platform data so the source can be __initdata */
if (spd)
simtec_audio_platdata = *spd;
if (has_lr_routing)
simtec_audio_platdata.startup = simtec_audio_startup_lrroute;
platform_device_register(&s3c_device_iis);
platform_device_register(&simtec_audio_dev);
return 0;
}
arch/arm/plat-s3c64xx/cpu.c
View file @ 602fd7c3
......@@ -107,6 +107,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_USB_HSPHY,
.pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
.length = SZ_1K,
.type = MT_DEVICE,
},
};
......
arch/arm/plat-s3c64xx/cpufreq.c
View file @ 602fd7c3
......@@ -19,6 +19,7 @@
static struct clk *armclk;
static struct regulator *vddarm;
static unsigned long regulator_latency;
#ifdef CONFIG_CPU_S3C6410
struct s3c64xx_dvfs {
......@@ -27,11 +28,10 @@ struct s3c64xx_dvfs {
};
static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
[0] = { 1000000, 1000000 },
[1] = { 1000000, 1050000 },
[2] = { 1050000, 1100000 },
[3] = { 1050000, 1150000 },
[4] = { 1250000, 1350000 },
[0] = { 1000000, 1150000 },
[1] = { 1050000, 1150000 },
[2] = { 1100000, 1150000 },
[3] = { 1200000, 1350000 },
};
static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
......@@ -41,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
{ 1, 266000 },
{ 2, 333000 },
{ 2, 400000 },
{ 3, 532000 },
{ 3, 533000 },
{ 4, 667000 },
{ 2, 532000 },
{ 2, 533000 },
{ 3, 667000 },
{ 0, CPUFREQ_TABLE_END },
};
#endif
......@@ -141,7 +141,7 @@ static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
}
#ifdef CONFIG_REGULATOR
static void __init s3c64xx_cpufreq_constrain_voltages(void)
static void __init s3c64xx_cpufreq_config_regulator(void)
{
int count, v, i, found;
struct cpufreq_frequency_table *freq;
......@@ -150,11 +150,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
count = regulator_count_voltages(vddarm);
if (count < 0) {
pr_err("cpufreq: Unable to check supported voltages\n");
return;
}
freq = s3c64xx_freq_table;
while (freq->frequency != CPUFREQ_TABLE_END) {
while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
if (freq->frequency == CPUFREQ_ENTRY_INVALID)
continue;
......@@ -175,6 +174,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
freq++;
}
/* Guess based on having to do an I2C/SPI write; in future we
* will be able to query the regulator performance here. */
regulator_latency = 1 * 1000 * 1000;
}
#endif
......@@ -206,7 +209,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
pr_err("cpufreq: Only frequency scaling available\n");
vddarm = NULL;
} else {
s3c64xx_cpufreq_constrain_voltages();
s3c64xx_cpufreq_config_regulator();
}
#endif
......@@ -217,8 +220,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
/* Check for frequencies we can generate */
r = clk_round_rate(armclk, freq->frequency * 1000);
r /= 1000;
if (r != freq->frequency)
if (r != freq->frequency) {
pr_debug("cpufreq: %dkHz unsupported by clock\n",
freq->frequency);
freq->frequency = CPUFREQ_ENTRY_INVALID;
}
/* If we have no regulator then assume startup
* frequency is the maximum we can support. */
......@@ -230,9 +236,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
policy->cur = clk_get_rate(armclk) / 1000;
/* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
* write plus clock reprogramming. */
policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
/* Datasheet says PLL stabalisation time (if we were to use
* the PLLs, which we don't currently) is ~300us worst case,
* but add some fudge.
*/
policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
if (ret != 0) {
......
arch/arm/plat-s3c64xx/gpiolib.c
View file @ 602fd7c3
......@@ -213,6 +213,11 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
.get_pull = s3c_gpio_getpull_updown,
};
int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
{
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
}
static struct s3c_gpio_chip gpio_4bit[] = {
{
.base = S3C64XX_GPA_BASE,
......@@ -269,10 +274,16 @@ static struct s3c_gpio_chip gpio_4bit[] = {
.base = S3C64XX_GPM(0),
.ngpio = S3C64XX_GPIO_M_NR,
.label = "GPM",
.to_irq = s3c64xx_gpio2int_gpm,
},
},
};
int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
{
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}
static struct s3c_gpio_chip gpio_4bit2[] = {
{
.base = S3C64XX_GPH_BASE + 0x4,
......@@ -297,6 +308,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
.base = S3C64XX_GPL(0),
.ngpio = S3C64XX_GPIO_L_NR,
.label = "GPL",
.to_irq = s3c64xx_gpio2int_gpl,
},
},
};
......
arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
View file @ 602fd7c3
......@@ -36,18 +36,18 @@
#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16)
#define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16)
#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20)
#define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20)
#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28)
#define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28)
#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
arch/arm/plat-s3c64xx/irq-eint.c
View file @ 602fd7c3
......@@ -65,7 +65,7 @@ static void s3c_irq_eint_maskack(unsigned int irq)
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int pin;
int pin, pin_val;
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
......@@ -109,7 +109,10 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
return -1;
}
if (offs <= 15)
shift = (offs / 2) * 4;
else
shift = ((offs - 16) / 2) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(reg);
......@@ -119,12 +122,18 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
/* set the GPIO pin appropriately */
if (offs < 23)
if (offs < 16) {
pin = S3C64XX_GPN(offs);
else
pin_val = S3C_GPIO_SFN(2);
} else if (offs < 23) {
pin = S3C64XX_GPL(offs + 8 - 16);
pin_val = S3C_GPIO_SFN(3);
} else {
pin = S3C64XX_GPM(offs - 23);
pin_val = S3C_GPIO_SFN(3);
}
s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(pin, pin_val);
return 0;
}
......
arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
View file @ 602fd7c3
......@@ -53,3 +53,23 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
}
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPH(6 + width);
/* Set all the necessary GPH pins to special-function 1 */
for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
/* Set all the necessary GPC pins to special-function 1 */
for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
arch/arm/plat-s5pc1xx/Kconfig
View file @ 602fd7c3
......@@ -15,6 +15,9 @@ config PLAT_S5PC1XX
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
select S5P_GPIO_CFG_S5PC1XX
help
Base platform code for any Samsung S5PC1XX device
......@@ -34,7 +37,12 @@ config CPU_S5PC100_CLOCK
# platform specific device setup
config S5PC100_SETUP_I2C0
config S5PC1XX_SETUP_FB_24BPP
bool
help
Common setup code for S5PC1XX with an 24bpp RGB display helper.
config S5PC1XX_SETUP_I2C0
bool
default y
help
......@@ -43,8 +51,14 @@ config S5PC100_SETUP_I2C0
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S5PC100_SETUP_I2C1
config S5PC1XX_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S5PC1XX_SETUP_SDHCI_GPIO
bool
help
Common setup code for SDHCI gpio.
endif
arch/arm/plat-s5pc1xx/Makefile
View file @ 602fd7c3
......@@ -13,7 +13,9 @@ obj- :=
obj-y += dev-uart.o
obj-y += cpu.o
obj-y += irq.o
obj-y += irq.o irq-gpio.o irq-eint.o
obj-y += clock.o
obj-y += gpiolib.o
# CPU support
......@@ -22,5 +24,8 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
# Device setup
obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
arch/arm/plat-s5pc1xx/clock.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s5pc1xx/clock.c
*
* Copyright 2009 Samsung Electronics Co.
*
* S5PC1XX Base clock support
*
* Based on plat-s3c64xx/clock.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/regs-clock.h>
#include <plat/devs.h>
#include <plat/clock.h>
struct clk clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S5PC100_CLKSRC1);
if (enable)
val |= S5PC100_CLKSRC1_CLK48M_MASK;
else
val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
__raw_writel(val, S5PC100_CLKSRC1);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
struct clk clk_54m = {
.name = "clk_54m",
.id = -1,
.rate = 54000000,
};
static int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 0;
}
static int clk_dummy_enable(struct clk *clk, int enable)
{
return 0;
}
struct clk clk_hd0 = {
.name = "hclkd0",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
.enable = clk_dummy_enable,
};
struct clk clk_pd0 = {
.name = "pclkd0",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
.enable = clk_dummy_enable,
};
static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
}
static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
}
static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
}
static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
}
static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
}
static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
}
static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
}
static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
}
static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
}
static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
}
int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
}
int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
}
static struct clk s5pc100_init_clocks_disable[] = {
{
.name = "dsi",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_DSI,
}, {
.name = "csi",
.id = -1,
.parent = &clk_h,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_CSI,
}, {
.name = "ccan",
.id = 0,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
}, {
.name = "ccan",
.id = 1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
}, {
.name = "keypad",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
}, {
.name = "hclkd2",
.id = -1,
.parent = NULL,
.enable = s5pc100_clk_d20_ctrl,
.ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
}, {
.name = "iis-d2",
.id = -1,
.parent = NULL,
.enable = s5pc100_clk_d20_ctrl,
.ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
},
};
static struct clk s5pc100_init_clocks[] = {
/* System1 (D0_0) devices */
{
.name = "intc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_INTC,
}, {
.name = "tzic",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_TZIC,
}, {
.name = "cf-ata",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_CFCON,
}, {
.name = "mdma",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_MDMA,
}, {
.name = "g2d",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_G2D,
}, {
.name = "secss",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_SECSS,
}, {
.name = "cssys",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
},
/* Memory (D0_1) devices */
{
.name = "dmc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_DMC,
}, {
.name = "sromc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_SROMC,
}, {
.name = "onenand",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
}, {
.name = "nand",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_NFCON,
}, {
.name = "intmem",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
}, {
.name = "ebi",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_EBI,
},
/* System2 (D0_2) devices */
{
.name = "seckey",
.id = -1,
.parent = &clk_pd0,
.enable = s5pc100_clk_d02_ctrl,
.ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
}, {
.name = "sdm",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc100_clk_d02_ctrl,
.ctrlbit = S5PC100_CLKGATE_D02_SDM,
},
/* File (D1_0) devices */
{
.name = "pdma",
.id = 0,
.parent = &clk_h,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
}, {
.name = "pdma",
.id = 1,
.parent = &clk_h,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
}, {
.name = "otg",
.id = -1,
.parent = &clk_h,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
}, {
.name = "modem",
.id = -1,
.parent = &clk_h,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_48m,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_48m,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_48m,
.enable = s5pc100_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
},
/* Multimedia1 (D1_1) devices */
{
.name = "lcd",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_LCD,
}, {
.name = "rotator",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
}, {
.name = "fimc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
}, {
.name = "fimc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
}, {
.name = "fimc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
}, {
.name = "jpeg",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_JPEG,
}, {
.name = "g3d",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_G3D,
},
/* Multimedia2 (D1_2) devices */
{
.name = "tv",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_TV,
}, {
.name = "vp",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_VP,
}, {
.name = "mixer",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_MIXER,
}, {
.name = "hdmi",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_HDMI,
}, {
.name = "mfc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_MFC,
},
/* System (D1_3) devices */
{
.name = "chipid",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_GPIO,
}, {
.name = "apc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_APC,
}, {
.name = "iec",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_IEC,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_PWM,
}, {
.name = "systimer",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_WDT,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_RTC,
},
/* Connectivity (D1_4) devices */
{
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART3,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_IIC,
}, {
.name = "hdmi-i2c",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI1,
}, {
.name = "spi",
.id = 2,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI2,
}, {
.name = "irda",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_IRDA,
}, {
.name = "hsitx",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HSITX,
}, {
.name = "hsirx",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
},
/* Audio (D1_5) devices */
{
.name = "iis",
.id = 0,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS0,
}, {
.name = "iis",
.id = 1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS1,
}, {
.name = "iis",
.id = 2,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS2,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_AC97,
}, {
.name = "pcm",
.id = 0,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_PCM0,
}, {
.name = "pcm",
.id = 1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_PCM1,
}, {
.name = "spdif",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_TSADC,
}, {
.name = "cg",
.id = -1,
.parent = &clk_p,
.enable = s5pc100_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_CG,
},
/* Audio (D2_0) devices: all disabled */
/* Special Clocks 0 */
{
.name = "sclk_hpm",
.id = -1,
.parent = NULL,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
}, {
.name = "sclk_onenand",
.id = -1,
.parent = NULL,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
}, {
.name = "spi_48",
.id = 0,
.parent = &clk_48m,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
}, {
.name = "spi_48",
.id = 1,
.parent = &clk_48m,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
}, {
.name = "spi_48",
.id = 2,
.parent = &clk_48m,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
}, {
.name = "mmc_48",
.id = 0,
.parent = &clk_48m,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
}, {
.name = "mmc_48",
.id = 1,
.parent = &clk_48m,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
}, {
.name = "mmc_48",
.id = 2,
.parent = &clk_48m,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
},
/* Special Clocks 1 */
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
&clk_54m,
};
void __init s5pc1xx_register_clocks(void)
{
struct clk *clkp;
int ret;
int ptr;
int size;
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
clkp = s5pc100_init_clocks;
size = ARRAY_SIZE(s5pc100_init_clocks);
for (ptr = 0; ptr < size; ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clkp = s5pc100_init_clocks_disable;
size = ARRAY_SIZE(s5pc100_init_clocks_disable);
for (ptr = 0; ptr < size; ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}
arch/arm/plat-s5pc1xx/cpu.c
View file @ 602fd7c3
......@@ -55,6 +55,16 @@ static struct cpu_table cpu_ids[] __initdata = {
static struct map_desc s5pc1xx_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER,
.pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_GPIO,
.pfn = __phys_to_pfn(S5PC100_PA_GPIO),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5PC1XX_VA_CHIPID,
.pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID),
.length = SZ_16,
......
arch/arm/plat-s5pc1xx/gpio-config.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s5pc1xx/gpio-config.c
*
* Copyright 2009 Samsung Electronics
*
* S5PC1XX GPIO Configuration.
*
* Based on plat-s3c64xx/gpio-config.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg-s5pc1xx.h>
s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
void __iomem *reg;
int shift = off * 2;
u32 drvstr;
if (!chip)
return -EINVAL;
reg = chip->base + 0x0C;
drvstr = __raw_readl(reg);
drvstr = 0xffff & (0x3 << shift);
drvstr = drvstr >> shift;
return (__force s5p_gpio_drvstr_t)drvstr;
}
EXPORT_SYMBOL(s5p_gpio_get_drvstr);
int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
s5p_gpio_drvstr_t drvstr)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
void __iomem *reg;
int shift = off * 2;
u32 tmp;
if (!chip)
return -EINVAL;
reg = chip->base + 0x0C;
tmp = __raw_readl(reg);
tmp |= drvstr << shift;
__raw_writel(tmp, reg);
return 0;
}
EXPORT_SYMBOL(s5p_gpio_set_drvstr);
arch/arm/plat-s5pc1xx/gpiolib.c 0 → 100644
View file @ 602fd7c3
/*
* arch/arm/plat-s5pc1xx/gpiolib.c
*
* Copyright 2009 Samsung Electronics Co
* Kyungmin Park <kyungmin.park@samsung.com>
*
* S5PC1XX - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/map.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <plat/regs-gpio.h>
/* S5PC100 GPIO bank summary:
*
* Bank GPIOs Style INT Type
* A0 8 4Bit GPIO_INT0
* A1 5 4Bit GPIO_INT1
* B 8 4Bit GPIO_INT2
* C 5 4Bit GPIO_INT3
* D 7 4Bit GPIO_INT4
* E0 8 4Bit GPIO_INT5
* E1 6 4Bit GPIO_INT6
* F0 8 4Bit GPIO_INT7
* F1 8 4Bit GPIO_INT8
* F2 8 4Bit GPIO_INT9
* F3 4 4Bit GPIO_INT10
* G0 8 4Bit GPIO_INT11
* G1 3 4Bit GPIO_INT12
* G2 7 4Bit GPIO_INT13
* G3 7 4Bit GPIO_INT14
* H0 8 4Bit WKUP_INT
* H1 8 4Bit WKUP_INT
* H2 8 4Bit WKUP_INT
* H3 8 4Bit WKUP_INT
* I 8 4Bit GPIO_INT15
* J0 8 4Bit GPIO_INT16
* J1 5 4Bit GPIO_INT17
* J2 8 4Bit GPIO_INT18
* J3 8 4Bit GPIO_INT19
* J4 4 4Bit GPIO_INT20
* K0 8 4Bit None
* K1 6 4Bit None
* K2 8 4Bit None
* K3 8 4Bit None
* L0 8 4Bit None
* L1 8 4Bit None
* L2 8 4Bit None
* L3 8 4Bit None
*/
#define OFF_GPCON (0x00)
#define OFF_GPDAT (0x04)
#define con_4bit_shift(__off) ((__off) * 4)
#if 1
#define gpio_dbg(x...) do { } while (0)
#else
#define gpio_dbg(x...) printk(KERN_DEBUG x)
#endif
/* The s5pc1xx_gpiolib routines are to control the gpio banks where
* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
* following example:
*
* base + 0x00: Control register, 4 bits per gpio
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*
* Note, since the data register is one bit per gpio and is at base + 0x4
* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
* the output.
*/
static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, base + OFF_GPCON);
gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
return 0;
}
static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
unsigned long dat;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, base + OFF_GPCON);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
{
return S3C_IRQ_GPIO(chip->base + offset);
}
static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
{
int base;
base = chip->base - S5PC100_GPH0(0);
if (base == 0)
return IRQ_EINT(offset);
base = chip->base - S5PC100_GPH1(0);
if (base == 0)
return IRQ_EINT(8 + offset);
base = chip->base - S5PC100_GPH2(0);
if (base == 0)
return IRQ_EINT(16 + offset);
base = chip->base - S5PC100_GPH3(0);
if (base == 0)
return IRQ_EINT(24 + offset);
return -EINVAL;
}
static struct s3c_gpio_cfg gpio_cfg = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_cfg_eint = {
.cfg_eint = 0xf,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
{
.base = S5PC100_GPA0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPA0(0),
.ngpio = S5PC100_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.base = S5PC100_GPA1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPA1(0),
.ngpio = S5PC100_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.base = S5PC100_GPB_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPB(0),
.ngpio = S5PC100_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S5PC100_GPC_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPC(0),
.ngpio = S5PC100_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S5PC100_GPD_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPD(0),
.ngpio = S5PC100_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S5PC100_GPE0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPE0(0),
.ngpio = S5PC100_GPIO_E0_NR,
.label = "GPE0",
},
}, {
.base = S5PC100_GPE1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPE1(0),
.ngpio = S5PC100_GPIO_E1_NR,
.label = "GPE1",
},
}, {
.base = S5PC100_GPF0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF0(0),
.ngpio = S5PC100_GPIO_F0_NR,
.label = "GPF0",
},
}, {
.base = S5PC100_GPF1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF1(0),
.ngpio = S5PC100_GPIO_F1_NR,
.label = "GPF1",
},
}, {
.base = S5PC100_GPF2_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF2(0),
.ngpio = S5PC100_GPIO_F2_NR,
.label = "GPF2",
},
}, {
.base = S5PC100_GPF3_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPF3(0),
.ngpio = S5PC100_GPIO_F3_NR,
.label = "GPF3",
},
}, {
.base = S5PC100_GPG0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG0(0),
.ngpio = S5PC100_GPIO_G0_NR,
.label = "GPG0",
},
}, {
.base = S5PC100_GPG1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG1(0),
.ngpio = S5PC100_GPIO_G1_NR,
.label = "GPG1",
},
}, {
.base = S5PC100_GPG2_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG2(0),
.ngpio = S5PC100_GPIO_G2_NR,
.label = "GPG2",
},
}, {
.base = S5PC100_GPG3_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPG3(0),
.ngpio = S5PC100_GPIO_G3_NR,
.label = "GPG3",
},
}, {
.base = S5PC100_GPH0_BASE,
.config = &gpio_cfg_eint,
.chip = {
.base = S5PC100_GPH0(0),
.ngpio = S5PC100_GPIO_H0_NR,
.label = "GPH0",
},
}, {
.base = S5PC100_GPH1_BASE,
.config = &gpio_cfg_eint,
.chip = {
.base = S5PC100_GPH1(0),
.ngpio = S5PC100_GPIO_H1_NR,
.label = "GPH1",
},
}, {
.base = S5PC100_GPH2_BASE,
.config = &gpio_cfg_eint,
.chip = {
.base = S5PC100_GPH2(0),
.ngpio = S5PC100_GPIO_H2_NR,
.label = "GPH2",
},
}, {
.base = S5PC100_GPH3_BASE,
.config = &gpio_cfg_eint,
.chip = {
.base = S5PC100_GPH3(0),
.ngpio = S5PC100_GPIO_H3_NR,
.label = "GPH3",
},
}, {
.base = S5PC100_GPI_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPI(0),
.ngpio = S5PC100_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S5PC100_GPJ0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ0(0),
.ngpio = S5PC100_GPIO_J0_NR,
.label = "GPJ0",
},
}, {
.base = S5PC100_GPJ1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ1(0),
.ngpio = S5PC100_GPIO_J1_NR,
.label = "GPJ1",
},
}, {
.base = S5PC100_GPJ2_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ2(0),
.ngpio = S5PC100_GPIO_J2_NR,
.label = "GPJ2",
},
}, {
.base = S5PC100_GPJ3_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ3(0),
.ngpio = S5PC100_GPIO_J3_NR,
.label = "GPJ3",
},
}, {
.base = S5PC100_GPJ4_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC100_GPJ4(0),
.ngpio = S5PC100_GPIO_J4_NR,
.label = "GPJ4",
},
}, {
.base = S5PC100_GPK0_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK0(0),
.ngpio = S5PC100_GPIO_K0_NR,
.label = "GPK0",
},
}, {
.base = S5PC100_GPK1_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK1(0),
.ngpio = S5PC100_GPIO_K1_NR,
.label = "GPK1",
},
}, {
.base = S5PC100_GPK2_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK2(0),
.ngpio = S5PC100_GPIO_K2_NR,
.label = "GPK2",
},
}, {
.base = S5PC100_GPK3_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPK3(0),
.ngpio = S5PC100_GPIO_K3_NR,
.label = "GPK3",
},
}, {
.base = S5PC100_GPL0_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL0(0),
.ngpio = S5PC100_GPIO_L0_NR,
.label = "GPL0",
},
}, {
.base = S5PC100_GPL1_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL1(0),
.ngpio = S5PC100_GPIO_L1_NR,
.label = "GPL1",
},
}, {
.base = S5PC100_GPL2_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL2(0),
.ngpio = S5PC100_GPIO_L2_NR,
.label = "GPL2",
},
}, {
.base = S5PC100_GPL3_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL3(0),
.ngpio = S5PC100_GPIO_L3_NR,
.label = "GPL3",
},
}, {
.base = S5PC100_GPL4_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC100_GPL4(0),
.ngpio = S5PC100_GPIO_L4_NR,
.label = "GPL4",
},
},
};
/* FIXME move from irq-gpio.c */
extern struct irq_chip s5pc1xx_gpioint;
extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
{
chip->chip.direction_input = s5pc1xx_gpiolib_input;
chip->chip.direction_output = s5pc1xx_gpiolib_output;
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
/* Interrupt */
if (chip->config == &gpio_cfg) {
int i, irq;
chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
for (i = 0; i < chip->chip.ngpio; i++) {
irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
set_irq_chip(irq, &s5pc1xx_gpioint);
set_irq_data(irq, &chip->chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
} else if (chip->config == &gpio_cfg_eint)
chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
}
static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
int nr_chips,
void (*fn)(struct s3c_gpio_chip *))
{
for (; nr_chips > 0; nr_chips--, chips++) {
if (fn)
(fn)(chips);
s3c_gpiolib_add(chips);
}
}
static __init int s5pc1xx_gpiolib_init(void)
{
struct s3c_gpio_chip *chips;
int nr_chips;
chips = s5pc100_gpio_chips;
nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
/* Interrupt */
set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
return 0;
}
core_initcall(s5pc1xx_gpiolib_init);
arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h
*
* Copyright 2009 Samsung Electronic
*
* S5PC1XX Platform - GPIO pin configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This file contains the necessary definitions to get the basic gpio
* pin configuration done such as setting a pin to input or output or
* changing the pull-{up,down} configurations.
*/
#ifndef __GPIO_CFG_S5PC1XX_H
#define __GPIO_CFG_S5PC1XX_H __FILE__
typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
#define S5P_GPIO_DRVSTR_LV1 0x00
#define S5P_GPIO_DRVSTR_LV2 0x01
#define S5P_GPIO_DRVSTR_LV3 0x10
#define S5P_GPIO_DRVSTR_LV4 0x11
extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off);
extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
s5p_gpio_drvstr_t drvstr);
#endif /* __GPIO_CFG_S5PC1XX_H */
arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
*
* Copyright 2009 Samsung Electronics Co.
*
* External Interrupt (GPH0 ~ GPH3) control register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0)
#define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4)
#define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8)
#define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC)
#define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
#define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80)
#define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84)
#define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88)
#define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C)
#define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90)
#define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94)
#define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98)
#define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C)
#define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
#define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100)
#define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104)
#define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108)
#define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C)
#define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
#define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140)
#define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144)
#define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148)
#define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C)
#define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
#define S5PC1XX_WKUP_INT_LOWLEV (0x00)
#define S5PC1XX_WKUP_INT_HILEV (0x01)
#define S5PC1XX_WKUP_INT_FALLEDGE (0x02)
#define S5PC1XX_WKUP_INT_RISEEDGE (0x03)
#define S5PC1XX_WKUP_INT_BOTHEDGE (0x04)
arch/arm/plat-s5pc1xx/include/plat/irqs.h
View file @ 602fd7c3
......@@ -171,12 +171,21 @@
#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
/* External interrupt */
#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1)
#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
#define IRQ_EINT(x) S3C_EINT(x)
#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16))
#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
#define NR_IRQS (IRQ_EINT(31)+1)
/* GPIO interrupt */
#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
/*
* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
*/
#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
View file @ 602fd7c3
......@@ -13,68 +13,69 @@
#ifndef __PLAT_REGS_CLOCK_H
#define __PLAT_REGS_CLOCK_H __FILE__
#define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x))
#define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00)
#define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04)
#define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08)
#define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C)
#define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100)
#define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104)
#define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108)
#define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C)
#define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200)
#define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204)
#define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208)
#define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C)
#define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300)
#define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304)
#define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308)
#define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C)
#define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310)
#define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400)
#define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500)
#define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504)
#define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508)
#define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520)
#define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524)
#define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528)
#define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C)
#define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530)
#define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534)
#define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540)
#define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560)
#define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564)
#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200)
#define S5PC1XX_EPLL_EN (1<<31)
#define S5PC1XX_EPLL_MASK 0xffffffff
#define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
/* s5pc100 register for clock */
#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
#define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
/* EPLL_CON */
#define S5PC100_EPLL_EN (1<<31)
#define S5PC100_EPLL_MASK 0xffffffff
#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
/* CLKSRC0 */
#define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0)
#define S5PC1XX_CLKSRC0_APLL_SHIFT (0)
#define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4)
#define S5PC1XX_CLKSRC0_MPLL_SHIFT (4)
#define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8)
#define S5PC1XX_CLKSRC0_EPLL_SHIFT (8)
#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0)
#define S5PC100_CLKSRC0_APLL_SHIFT (0)
#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4)
#define S5PC100_CLKSRC0_MPLL_SHIFT (4)
#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8)
#define S5PC100_CLKSRC0_EPLL_SHIFT (8)
#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
#define S5PC100_CLKSRC0_HPLL_SHIFT (12)
#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
#define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
#define S5PC100_CLKSRC0_HREF_SHIFT (20)
#define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24)
#define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24)
#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24)
#define S5PC100_CLKSRC0_ONENAND_SHIFT (24)
/* CLKSRC1 */
......@@ -127,10 +128,9 @@
#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
#define S5PC100_CLKSRC3_SPDIF_SHIFT (24)
/* CLKDIV0 */
#define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0)
#define S5PC1XX_CLKDIV0_APLL_SHIFT (0)
#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
#define S5PC100_CLKDIV0_APLL_SHIFT (0)
#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
#define S5PC100_CLKDIV0_ARM_SHIFT (4)
#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
......@@ -141,8 +141,8 @@
#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
/* CLKDIV1 */
#define S5PC100_CLKDIV1_AM_MASK (0x7<<0)
#define S5PC100_CLKDIV1_AM_SHIFT (0)
#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
......@@ -202,7 +202,6 @@
#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
#define S5PC100_CLKGATE_D00_INTC (1<<0)
#define S5PC100_CLKGATE_D00_TZIC (1<<1)
......@@ -295,8 +294,8 @@
#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
/* Special Clock Gate 0 Registers */
#define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0)
#define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1)
#define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
#define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
......@@ -329,85 +328,24 @@
#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
/* register for power management */
#define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000)
#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004)
#define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010)
#define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014)
#define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018)
#define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C)
#define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100)
#define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104)
#define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108)
#define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110)
#define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114)
#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200)
#define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300)
#define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304)
#define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308)
#define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400)
#define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404)
#define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408)
#define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C)
#define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410)
#define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414)
#define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418)
#define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C)
#define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500)
#define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504)
#define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508)
#define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C)
#define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510)
#define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514)
#define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518)
#define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C)
#define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520)
#define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600)
#define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604)
#define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608)
#define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C)
#define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610)
#define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614)
#define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618)
#define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C)
#define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620)
#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700)
#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704)
#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708)
#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C)
#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710)
#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714)
#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718)
#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C)
#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724)
#define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000)
#define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008)
#define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100)
#define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104)
#define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200)
#define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300)
#define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304)
#define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308)
#define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400)
#define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414)
#define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420)
#define S5PC100_CFG_WFI_CLEAN (~(3<<5))
#define S5PC100_CFG_WFI_IDLE (1<<5)
#define S5PC100_CFG_WFI_STOP (2<<5)
#define S5PC100_CFG_WFI_SLEEP (3<<5)
#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
#define S5PC100_SWRESET_RESETVAL 0xc100
#define S5PC100_OTHER_SYS_INT 24
#define S5PC100_OTHER_STA_TYPE 23
#define STA_TYPE_EXPON 0
#define STA_TYPE_SFR 1
#define S5PC100_PWR_STA_EXP_SCALE 0
#define S5PC100_PWR_STA_CNT 4
#define S5PC100_PWR_STABLE_COUNT 85500
#define S5PC100_SLEEP_CFG_OSC_EN 0
/* OTHERS Resgister */
......
arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX - GPIO register definitions
*/
#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
#include <mach/map.h>
/* S5PC100 */
#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO
#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68)
#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80)
/* PDNEN */
#define S5PC100_PDNEN_CFG_PDNEN (1 << 1)
#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
#define S5PC100_PDNEN_POWERDOWN (1 << 0)
#define S5PC100_PDNEN_NORMAL (0 << 0)
/* Common part */
/* External interrupt base is same at both s5pc100 and s5pc110 */
#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE)
#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
arch/arm/plat-s5pc1xx/include/plat/regs-power.h 0 → 100644
View file @ 602fd7c3
/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
*
* Copyright 2009 Samsung Electronics Co.
* Jongse Won <jongse.won@samsung.com>
*
* S5PC1XX clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_REGS_PWR
#define __ASM_ARM_REGS_PWR __FILE__
#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x))
/* s5pc100 (0xE0108000) register for power management */
#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0)
#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4)
#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10)
#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14)
#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18)
#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C)
#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100)
#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104)
#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108)
#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110)
#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114)
#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200)
#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300)
#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304)
#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308)
#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400)
#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404)
#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408)
#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C)
#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410)
#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414)
#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418)
#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C)
#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500)
#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504)
#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508)
#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C)
#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510)
#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514)
#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518)
#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C)
#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520)
#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600)
#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604)
#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608)
#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C)
#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610)
#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614)
#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618)
#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C)
#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620)
#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700)
#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704)
#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708)
#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C)
#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710)
#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714)
#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718)
#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C)
#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724)
/* PWR_CFG */
#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31)
#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5)
#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5)
#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5)
#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5)
#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5)
/* SLEEP_CFG */
#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0)
/* OTHERS */
#define S5PC100_PMU_INT_DISABLE (1 << 24)
#endif /* __ASM_ARM_REGS_PWR */
arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
View file @ 602fd7c3
......@@ -35,10 +35,9 @@ extern struct clk clk_hpll;
extern struct clk clk_hd0;
extern struct clk clk_pd0;
extern struct clk clk_54m;
extern struct clk clk_dout_mpll2;
extern void s5pc1xx_register_clocks(void);
extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable);
extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable);
extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
......
arch/arm/plat-s5pc1xx/irq-eint.c 0 → 100644
View file @ 602fd7c3
/*
* linux/arch/arm/plat-s5pc1xx/irq-eint.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
* Kyungin Park <kyungmin.park@samsung.com>
*
* Based on plat-s3c64xx/irq-eint.c
*
* S5PC1XX - Interrupt handling for IRQ_EINT(x)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/pm.h>
#include <linux/gpio.h>
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-ext.h>
#include <plat/pm.h>
#include <plat/regs-gpio.h>
#include <plat/regs-irqtype.h>
/*
* bank is a group of external interrupt
* bank0 means EINT0 ... EINT7
* bank1 means EINT8 ... EINT15
* bank2 means EINT16 ... EINT23
* bank3 means EINT24 ... EINT31
*/
static inline int s3c_get_eint(unsigned int irq)
{
int real;
if (irq < IRQ_EINT16_31)
real = (irq - IRQ_EINT0);
else
real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
return real;
}
static inline int s3c_get_bank(unsigned int irq)
{
return s3c_get_eint(irq) >> 3;
}
static inline int s3c_eint_to_bit(unsigned int irq)
{
int real, bit;
real = s3c_get_eint(irq);
bit = 1 << (real & (8 - 1));
return bit;
}
static inline void s3c_irq_eint_mask(unsigned int irq)
{
u32 mask;
u32 bank = s3c_get_bank(irq);
mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
mask |= s3c_eint_to_bit(irq);
__raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
}
static void s3c_irq_eint_unmask(unsigned int irq)
{
u32 mask;
u32 bank = s3c_get_bank(irq);
mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
mask &= ~(s3c_eint_to_bit(irq));
__raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
}
static inline void s3c_irq_eint_ack(unsigned int irq)
{
u32 bank = s3c_get_bank(irq);
__raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
}
static void s3c_irq_eint_maskack(unsigned int irq)
{
/* compiler should in-line these */
s3c_irq_eint_mask(irq);
s3c_irq_eint_ack(irq);
}
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
u32 bank = s3c_get_bank(irq);
int real = s3c_get_eint(irq);
int gpio, shift, sfn;
u32 ctrl, con = 0;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
con = S5PC1XX_WKUP_INT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
con = S5PC1XX_WKUP_INT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
con = S5PC1XX_WKUP_INT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
con = S5PC1XX_WKUP_INT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
con = S5PC1XX_WKUP_INT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -EINVAL;
}
gpio = real & (8 - 1);
shift = gpio << 2;
ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
ctrl &= ~(0x7 << shift);
ctrl |= con << shift;
__raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
switch (real) {
case 0 ... 7:
gpio = S5PC100_GPH0(gpio);
break;
case 8 ... 15:
gpio = S5PC100_GPH1(gpio);
break;
case 16 ... 23:
gpio = S5PC100_GPH2(gpio);
break;
case 24 ... 31:
gpio = S5PC100_GPH3(gpio);
break;
default:
return -EINVAL;
}
sfn = S3C_GPIO_SFN(0x2);
s3c_gpio_cfgpin(gpio, sfn);
return 0;
}
static struct irq_chip s3c_irq_eint = {
.name = "EINT",
.mask = s3c_irq_eint_mask,
.unmask = s3c_irq_eint_unmask,
.mask_ack = s3c_irq_eint_maskack,
.ack = s3c_irq_eint_ack,
.set_type = s3c_irq_eint_set_type,
.set_wake = s3c_irqext_wake,
};
/* s3c_irq_demux_eint
*
* This function demuxes the IRQ from external interrupts,
* from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
* the specific handlers s3c_irq_demux_eintX_Y.
*/
static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
{
u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
unsigned int irq;
status &= ~mask;
status &= (1 << (end - start + 1)) - 1;
for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
if (status & 1)
generic_handle_irq(irq);
status >>= 1;
}
}
static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
s3c_irq_demux_eint(16, 23);
s3c_irq_demux_eint(24, 31);
}
/*
* Handle EINT0 ... EINT15 at VIC directly
*/
static void s3c_irq_vic_eint_mask(unsigned int irq)
{
void __iomem *base = get_irq_chip_data(irq);
unsigned int real;
s3c_irq_eint_mask(irq);
real = s3c_get_eint(irq);
writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
}
static void s3c_irq_vic_eint_unmask(unsigned int irq)
{
void __iomem *base = get_irq_chip_data(irq);
unsigned int real;
s3c_irq_eint_unmask(irq);
real = s3c_get_eint(irq);
writel(1 << real, base + VIC_INT_ENABLE);
}
static inline void s3c_irq_vic_eint_ack(unsigned int irq)
{
u32 bit;
u32 bank = s3c_get_bank(irq);
bit = s3c_eint_to_bit(irq);
__raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
}
static void s3c_irq_vic_eint_maskack(unsigned int irq)
{
/* compiler should in-line these */
s3c_irq_vic_eint_mask(irq);
s3c_irq_vic_eint_ack(irq);
}
static struct irq_chip s3c_irq_vic_eint = {
.name = "EINT",
.mask = s3c_irq_vic_eint_mask,
.unmask = s3c_irq_vic_eint_unmask,
.mask_ack = s3c_irq_vic_eint_maskack,
.ack = s3c_irq_vic_eint_ack,
.set_type = s3c_irq_eint_set_type,
.set_wake = s3c_irqext_wake,
};
static int __init s5pc1xx_init_irq_eint(void)
{
int irq;
for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
set_irq_chip(irq, &s3c_irq_vic_eint);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
set_irq_chip(irq, &s3c_irq_eint);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
return 0;
}
arch_initcall(s5pc1xx_init_irq_eint);
arch/arm/plat-s5pc1xx/irq-gpio.c 0 → 100644
View file @ 602fd7c3
/*
* arch/arm/plat-s5pc1xx/irq-gpio.c
*
* Copyright (C) 2009 Samsung Electronics
*
* S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/map.h>
#include <plat/gpio-cfg.h>
#define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x))
#define CON_OFFSET 0x700
#define MASK_OFFSET 0x900
#define PEND_OFFSET 0xA00
#define CON_OFFSET_2 0xE00
#define MASK_OFFSET_2 0xF00
#define PEND_OFFSET_2 0xF40
#define GPIOINT_LEVEL_LOW 0x0
#define GPIOINT_LEVEL_HIGH 0x1
#define GPIOINT_EDGE_FALLING 0x2
#define GPIOINT_EDGE_RISING 0x3
#define GPIOINT_EDGE_BOTH 0x4
static int group_to_con_offset(int group)
{
return group << 2;
}
static int group_to_mask_offset(int group)
{
return group << 2;
}
static int group_to_pend_offset(int group)
{
return group << 2;
}
static int s5pc1xx_get_start(unsigned int group)
{
switch (group) {
case 0: return S5PC100_GPIO_A0_START;
case 1: return S5PC100_GPIO_A1_START;
case 2: return S5PC100_GPIO_B_START;
case 3: return S5PC100_GPIO_C_START;
case 4: return S5PC100_GPIO_D_START;
case 5: return S5PC100_GPIO_E0_START;
case 6: return S5PC100_GPIO_E1_START;
case 7: return S5PC100_GPIO_F0_START;
case 8: return S5PC100_GPIO_F1_START;
case 9: return S5PC100_GPIO_F2_START;
case 10: return S5PC100_GPIO_F3_START;
case 11: return S5PC100_GPIO_G0_START;
case 12: return S5PC100_GPIO_G1_START;
case 13: return S5PC100_GPIO_G2_START;
case 14: return S5PC100_GPIO_G3_START;
case 15: return S5PC100_GPIO_I_START;
case 16: return S5PC100_GPIO_J0_START;
case 17: return S5PC100_GPIO_J1_START;
case 18: return S5PC100_GPIO_J2_START;
case 19: return S5PC100_GPIO_J3_START;
case 20: return S5PC100_GPIO_J4_START;
default:
BUG();
}
return -EINVAL;
}
static int s5pc1xx_get_group(unsigned int irq)
{
irq -= S3C_IRQ_GPIO(0);
switch (irq) {
case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
return 0;
case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
return 1;
case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
return 2;
case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
return 3;
case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
return 4;
case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
return 5;
case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
return 6;
case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
return 7;
case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
return 8;
case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
return 9;
case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
return 10;
case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
return 11;
case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
return 12;
case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
return 13;
case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
return 14;
case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
return 15;
case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
return 16;
case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
return 17;
case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
return 18;
case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
return 19;
case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
return 20;
default:
BUG();
}
return -EINVAL;
}
static int s5pc1xx_get_offset(unsigned int irq)
{
struct gpio_chip *chip = get_irq_data(irq);
return irq - S3C_IRQ_GPIO(chip->base);
}
static void s5pc1xx_gpioint_ack(unsigned int irq)
{
int group, offset, pend_offset;
unsigned int value;
group = s5pc1xx_get_group(irq);
offset = s5pc1xx_get_offset(irq);
pend_offset = group_to_pend_offset(group);
value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
value |= 1 << offset;
__raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
}
static void s5pc1xx_gpioint_mask(unsigned int irq)
{
int group, offset, mask_offset;
unsigned int value;
group = s5pc1xx_get_group(irq);
offset = s5pc1xx_get_offset(irq);
mask_offset = group_to_mask_offset(group);
value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
value |= 1 << offset;
__raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
}
static void s5pc1xx_gpioint_unmask(unsigned int irq)
{
int group, offset, mask_offset;
unsigned int value;
group = s5pc1xx_get_group(irq);
offset = s5pc1xx_get_offset(irq);
mask_offset = group_to_mask_offset(group);
value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
value &= ~(1 << offset);
__raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
}
static void s5pc1xx_gpioint_mask_ack(unsigned int irq)
{
s5pc1xx_gpioint_mask(irq);
s5pc1xx_gpioint_ack(irq);
}
static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
{
int group, offset, con_offset;
unsigned int value;
group = s5pc1xx_get_group(irq);
offset = s5pc1xx_get_offset(irq);
con_offset = group_to_con_offset(group);
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No irq type\n");
return -EINVAL;
case IRQ_TYPE_EDGE_RISING:
type = GPIOINT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
type = GPIOINT_EDGE_FALLING;
break;
case IRQ_TYPE_EDGE_BOTH:
type = GPIOINT_EDGE_BOTH;
break;
case IRQ_TYPE_LEVEL_HIGH:
type = GPIOINT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
type = GPIOINT_LEVEL_LOW;
break;
default:
BUG();
}
value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
value &= ~(0xf << (offset * 0x4));
value |= (type << (offset * 0x4));
__raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
return 0;
}
struct irq_chip s5pc1xx_gpioint = {
.name = "GPIO",
.ack = s5pc1xx_gpioint_ack,
.mask = s5pc1xx_gpioint_mask,
.mask_ack = s5pc1xx_gpioint_mask_ack,
.unmask = s5pc1xx_gpioint_unmask,
.set_type = s5pc1xx_gpioint_set_type,
};
void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
{
int group, offset, pend_offset, mask_offset;
int real_irq, group_end;
unsigned int pend, mask;
group_end = 21;
for (group = 0; group < group_end; group++) {
pend_offset = group_to_pend_offset(group);
pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
if (!pend)
continue;
mask_offset = group_to_mask_offset(group);
mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
pend &= ~mask;
for (offset = 0; offset < 8; offset++) {
if (pend & (1 << offset)) {
real_irq = s5pc1xx_get_start(group) + offset;
generic_handle_irq(S3C_IRQ_GPIO(real_irq));
}
}
}
}
arch/arm/plat-s5pc1xx/irq.c
View file @ 602fd7c3
......@@ -79,7 +79,7 @@ static void s3c_irq_timer_ack(unsigned int irq)
{
u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
reg &= 0x1f;
reg &= 0x1f; /* mask out pending interrupts */
reg |= (1 << 5) << (irq - IRQ_TIMER0);
__raw_writel(reg, S3C64XX_TINT_CSTAT);
}
......
arch/arm/plat-s5pc1xx/s5pc100-clock.c
View file @ 602fd7c3
......@@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = {
#define clk_fin_hpll clk_ext_xtal_mux
#define clk_fout_mpll clk_mpll
#define clk_vclk_54m clk_54m
struct clk_sources {
unsigned int nr_sources;
......@@ -67,851 +68,398 @@ struct clksrc_clk {
void __iomem *reg_source;
};
static int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 1;
}
struct clk clk_27m = {
.name = "clk_27m",
/* APLL */
static struct clk clk_fout_apll = {
.name = "fout_apll",
.id = -1,
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S5PC1XX_CLK_SRC1);
if (enable)
val |= S5PC100_CLKSRC1_CLK48M_MASK;
else
val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
__raw_writel(val, S5PC1XX_CLK_SRC1);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
[1] = &clk_fout_apll,
};
struct clk clk_54m = {
.name = "clk_54m",
.id = -1,
.rate = 54000000,
static struct clk_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
struct clk clk_hpll = {
.name = "hpll",
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
.id = -1,
},
.shift = S5PC100_CLKSRC0_APLL_SHIFT,
.mask = S5PC100_CLKSRC0_APLL_MASK,
.sources = &clk_src_apll,
.reg_source = S5PC100_CLKSRC0,
};
struct clk clk_hd0 = {
.name = "hclkd0",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
return rate / (ratio + 1);
}
struct clk clk_pd0 = {
.name = "pclkd0",
static struct clk clk_dout_apll = {
.name = "dout_apll",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
.parent = &clk_mout_apll.clk,
.get_rate = s5pc100_clk_dout_apll_get_rate,
};
static int s5pc1xx_clk_gate(void __iomem *reg,
struct clk *clk,
int enable)
static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
__raw_writel(con, reg);
return 0;
return rate / (ratio + 1);
}
static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable)
static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
unsigned long rate)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
}
unsigned long parent = clk_get_rate(clk->parent);
u32 div;
static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
}
if (parent < rate)
return rate;
static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
}
div = (parent / rate) - 1;
if (div > S5PC100_CLKDIV0_ARM_MASK)
div = S5PC100_CLKDIV0_ARM_MASK;
static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
return parent / (div + 1);
}
static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable)
static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
}
unsigned long parent = clk_get_rate(clk->parent);
u32 div;
u32 val;
static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
}
if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
return -EINVAL;
static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
}
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
}
val = __raw_readl(S5PC100_CLKDIV0);
val &= S5PC100_CLKDIV0_ARM_MASK;
val |= (div - 1);
__raw_writel(val, S5PC100_CLKDIV0);
static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
return 0;
}
static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
}
static struct clk clk_arm = {
.name = "armclk",
.id = -1,
.parent = &clk_dout_apll,
.get_rate = s5pc100_clk_arm_get_rate,
.set_rate = s5pc100_clk_arm_set_rate,
.round_rate = s5pc100_clk_arm_round_rate,
};
int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable)
static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
{
return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
}
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable)
{
return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
return rate / (ratio + 1);
}
static struct clk init_clocks_disable[] = {
{
.name = "dsi",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_DSI,
}, {
.name = "csi",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_CSI,
}, {
.name = "ccan0",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
}, {
.name = "ccan1",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
}, {
.name = "keypad",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
}, {
.name = "hclkd2",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_clk_d20_ctrl,
.ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
}, {
.name = "iis-d2",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_clk_d20_ctrl,
.ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
}, {
.name = "otg",
static struct clk clk_dout_d0_bus = {
.name = "dout_d0_bus",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
},
.parent = &clk_arm,
.get_rate = s5pc100_clk_dout_d0_bus_get_rate,
};
static struct clk init_clocks[] = {
/* System1 (D0_0) devices */
{
.name = "intc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_INTC,
}, {
.name = "tzic",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_TZIC,
}, {
.name = "cf-ata",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_CFCON,
}, {
.name = "mdma",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_MDMA,
}, {
.name = "g2d",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_G2D,
}, {
.name = "secss",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_SECSS,
}, {
.name = "cssys",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d00_ctrl,
.ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
},
static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
/* Memory (D0_1) devices */
{
.name = "dmc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_DMC,
}, {
.name = "sromc",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_SROMC,
}, {
.name = "onenand",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
}, {
.name = "nand",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_NFCON,
}, {
.name = "intmem",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
}, {
.name = "ebi",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d01_ctrl,
.ctrlbit = S5PC100_CLKGATE_D01_EBI,
},
ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
/* System2 (D0_2) devices */
{
.name = "seckey",
.id = -1,
.parent = &clk_pd0,
.enable = s5pc1xx_clk_d02_ctrl,
.ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
}, {
.name = "sdm",
.id = -1,
.parent = &clk_hd0,
.enable = s5pc1xx_clk_d02_ctrl,
.ctrlbit = S5PC100_CLKGATE_D02_SDM,
},
return rate / (ratio + 1);
}
/* File (D1_0) devices */
{
.name = "pdma0",
static struct clk clk_dout_pclkd0 = {
.name = "dout_pclkd0",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
}, {
.name = "pdma1",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
}, {
.name = "modem",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h,
.enable = s5pc1xx_clk_d10_ctrl,
.ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
},
.parent = &clk_dout_d0_bus,
.get_rate = s5pc100_clk_dout_pclkd0_get_rate,
};
/* Multimedia1 (D1_1) devices */
{
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_LCD,
}, {
.name = "rotator",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
}, {
.name = "fimc",
.id = 0,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
}, {
.name = "fimc",
.id = 1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
}, {
.name = "fimc",
.id = 2,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
}, {
.name = "jpeg",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_JPEG,
}, {
.name = "g3d",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d11_ctrl,
.ctrlbit = S5PC100_CLKGATE_D11_G3D,
},
static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
/* Multimedia2 (D1_2) devices */
{
.name = "tv",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_TV,
}, {
.name = "vp",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_VP,
}, {
.name = "mixer",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_MIXER,
}, {
.name = "hdmi",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_HDMI,
}, {
.name = "mfc",
.id = -1,
.parent = &clk_h,
.enable = s5pc1xx_clk_d12_ctrl,
.ctrlbit = S5PC100_CLKGATE_D12_MFC,
},
ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
/* System (D1_3) devices */
{
.name = "chipid",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_GPIO,
}, {
.name = "apc",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_APC,
}, {
.name = "iec",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_IEC,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_PWM,
}, {
.name = "systimer",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_WDT,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d13_ctrl,
.ctrlbit = S5PC100_CLKGATE_D13_RTC,
},
return rate / (ratio + 1);
}
/* Connectivity (D1_4) devices */
{
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_UART3,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_IIC,
}, {
.name = "hdmi-i2c",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI1,
}, {
.name = "spi",
.id = 2,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_SPI2,
}, {
.name = "irda",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_IRDA,
}, {
.name = "hsitx",
static struct clk clk_dout_apll2 = {
.name = "dout_apll2",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HSITX,
}, {
.name = "hsirx",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d14_ctrl,
.ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
},
.parent = &clk_mout_apll.clk,
.get_rate = s5pc100_clk_dout_apll2_get_rate,
};
/* Audio (D1_5) devices */
{
.name = "iis",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS0,
}, {
.name = "iis",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS1,
}, {
.name = "iis",
.id = 2,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_IIS2,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_AC97,
}, {
.name = "pcm",
.id = 0,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_PCM0,
}, {
.name = "pcm",
.id = 1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_PCM1,
}, {
.name = "spdif",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_TSADC,
}, {
.name = "keyif",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
}, {
.name = "cg",
.id = -1,
.parent = &clk_p,
.enable = s5pc1xx_clk_d15_ctrl,
.ctrlbit = S5PC100_CLKGATE_D15_CG,
},
/* MPLL */
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_fout_mpll,
};
/* Audio (D2_0) devices: all disabled */
static struct clk_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
/* Special Clocks 1 */
{
.name = "sclk_hpm",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM,
}, {
.name = "sclk_onenand",
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
}, {
.name = "sclk_spi_48",
.id = 0,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
}, {
.name = "sclk_spi_48",
.id = 1,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
}, {
.name = "sclk_spi_48",
.id = 2,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
}, {
.name = "sclk_mmc_48",
.id = 0,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
}, {
.name = "sclk_mmc_48",
.id = 1,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
}, {
.name = "sclk_mmc_48",
.id = 2,
.parent = &clk_48m,
.enable = s5pc1xx_sclk0_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
},
.shift = S5PC100_CLKSRC0_MPLL_SHIFT,
.mask = S5PC100_CLKSRC0_MPLL_MASK,
.sources = &clk_src_mpll,
.reg_source = S5PC100_CLKSRC0,
};
/* Special Clocks 2 */
{
.name = "sclk_tv_54",
.id = -1,
.parent = &clk_54m,
.enable = s5pc1xx_sclk1_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK1_TV54,
}, {
.name = "sclk_vdac_54",
.id = -1,
.parent = &clk_54m,
.enable = s5pc1xx_sclk1_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54,
}, {
.name = "sclk_spdif",
static struct clk *clkset_am_list[] = {
[0] = &clk_mout_mpll.clk,
[1] = &clk_dout_apll2,
};
static struct clk_sources clk_src_am = {
.sources = clkset_am_list,
.nr_sources = ARRAY_SIZE(clkset_am_list),
};
static struct clksrc_clk clk_mout_am = {
.clk = {
.name = "mout_am",
.id = -1,
.parent = NULL,
.enable = s5pc1xx_sclk1_ctrl,
.ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF,
},
.shift = S5PC100_CLKSRC0_AMMUX_SHIFT,
.mask = S5PC100_CLKSRC0_AMMUX_MASK,
.sources = &clk_src_am,
.reg_source = S5PC100_CLKSRC0,
};
void __init s5pc1xx_register_clocks(void)
static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
{
struct clk *clkp;
int ret;
int ptr;
clkp = init_clocks;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
clkp = init_clocks_disable;
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
(clkp->enable)(clkp, 0);
}
ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
s3c_pwmclk_init();
return rate / (ratio + 1);
}
static struct clk clk_fout_apll = {
.name = "fout_apll",
static struct clk clk_dout_d1_bus = {
.name = "dout_d1_bus",
.id = -1,
.parent = &clk_mout_am.clk,
.get_rate = s5pc100_clk_dout_d1_bus_get_rate,
};
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
[1] = &clk_fout_apll,
static struct clk *clkset_onenand_list[] = {
[0] = &clk_dout_d0_bus,
[1] = &clk_dout_d1_bus,
};
static struct clk_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
static struct clk_sources clk_src_onenand = {
.sources = clkset_onenand_list,
.nr_sources = ARRAY_SIZE(clkset_onenand_list),
};
static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_onenand = {
.clk = {
.name = "mout_apll",
.name = "mout_onenand",
.id = -1,
},
.shift = S5PC1XX_CLKSRC0_APLL_SHIFT,
.mask = S5PC1XX_CLKSRC0_APLL_MASK,
.sources = &clk_src_apll,
.reg_source = S5PC1XX_CLK_SRC0,
.shift = S5PC100_CLKSRC0_ONENAND_SHIFT,
.mask = S5PC100_CLKSRC0_ONENAND_MASK,
.sources = &clk_src_onenand,
.reg_source = S5PC100_CLKSRC0,
};
static struct clk clk_fout_epll = {
.name = "fout_epll",
.id = -1,
};
static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
};
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
static struct clk_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
return rate / (ratio + 1);
}
static struct clk clk_dout_pclkd1 = {
.name = "dout_pclkd1",
.id = -1,
},
.shift = S5PC1XX_CLKSRC0_EPLL_SHIFT,
.mask = S5PC1XX_CLKSRC0_EPLL_MASK,
.sources = &clk_src_epll,
.reg_source = S5PC1XX_CLK_SRC0,
.parent = &clk_dout_d1_bus,
.get_rate = s5pc100_clk_dout_pclkd1_get_rate,
};
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_fout_mpll,
};
static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned int ratio;
static struct clk_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
return rate / (ratio + 1);
}
static struct clk clk_dout_mpll2 = {
.name = "dout_mpll2",
.id = -1,
},
.shift = S5PC1XX_CLKSRC0_MPLL_SHIFT,
.mask = S5PC1XX_CLKSRC0_MPLL_MASK,
.sources = &clk_src_mpll,
.reg_source = S5PC1XX_CLK_SRC0,
.parent = &clk_mout_am.clk,
.get_rate = s5pc100_clk_dout_mpll2_get_rate,
};
static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned long clkdiv;
unsigned int ratio;
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
return rate;
return rate / (ratio + 1);
}
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
static struct clk clk_dout_cam = {
.name = "dout_cam",
.id = -1,
.parent = &clk_mout_mpll.clk,
.get_rate = s5pc1xx_clk_doutmpll_get_rate,
.parent = &clk_dout_mpll2,
.get_rate = s5pc100_clk_dout_cam_get_rate,
};
static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned long clkdiv;
unsigned int ratio;
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
return rate;
return rate / (ratio + 1);
}
struct clk clk_dout_mpll2 = {
.name = "dout_mpll2",
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
.get_rate = s5pc1xx_clk_doutmpll2_get_rate,
.parent = &clk_mout_am.clk,
.get_rate = s5pc100_clk_dout_mpll_get_rate,
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
NULL,
NULL
/* EPLL */
static struct clk clk_fout_epll = {
.name = "fout_epll",
.id = -1,
};
static struct clk_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
};
static struct clk_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
.id = -1,
},
.shift = S5PC100_CLKSRC0_EPLL_SHIFT,
.mask = S5PC100_CLKSRC0_EPLL_MASK,
.sources = &clk_src_epll,
.reg_source = S5PC100_CLKSRC0,
};
/* HPLL */
static struct clk clk_fout_hpll = {
.name = "fout_hpll",
.id = -1,
};
static struct clk *clk_src_hpll_list[] = {
[0] = &clk_27m,
[1] = &clk_fout_hpll,
};
static struct clk_sources clk_src_hpll = {
.sources = clk_src_hpll_list,
.nr_sources = ARRAY_SIZE(clk_src_hpll_list),
};
static struct clksrc_clk clk_mout_hpll = {
.clk = {
.name = "mout_hpll",
.id = -1,
},
.shift = S5PC100_CLKSRC0_HPLL_SHIFT,
.mask = S5PC100_CLKSRC0_HPLL_MASK,
.sources = &clk_src_hpll,
.reg_source = S5PC100_CLKSRC0,
};
/* Peripherals */
/*
* The peripheral clocks are all controlled via clocksource followed
* by an optional divider and gate stage. We currently roll this into
* one clock which hides the intermediate clock from the mux.
*
* Note, the JPEG clock can only be an even divider...
*
* The scaler and LCD clocks depend on the S5PC100 version, and also
* have a common parent divisor so are not included here.
*/
static inline struct clksrc_clk *to_clksrc(struct clk *clk)
{
return container_of(clk, struct clksrc_clk, clk);
}
static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
{
struct clksrc_clk *sclk = to_clksrc(clk);
unsigned long rate = clk_get_rate(clk->parent);
......@@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
return rate;
}
static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
{
struct clksrc_clk *sclk = to_clksrc(clk);
void __iomem *reg = sclk->reg_divider;
......@@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
return -EINVAL;
val = __raw_readl(reg);
val &= ~(0xf << sclk->shift);
val |= (div - 1) << sclk->shift;
val &= ~(0xf << sclk->divider_shift);
val |= (div - 1) << sclk->divider_shift;
__raw_writel(val, reg);
return 0;
}
static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
{
struct clksrc_clk *sclk = to_clksrc(clk);
struct clk_sources *srcs = sclk->sources;
......@@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
return -EINVAL;
}
static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
unsigned long rate)
{
unsigned long parent_rate = clk_get_rate(clk->parent);
......@@ -992,35 +540,466 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
return rate;
}
static struct clk *clkset_spi_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll2,
&clk_fin_epll,
&clk_mout_hpll.clk,
};
static struct clk_sources clkset_spi = {
.sources = clkset_spi_list,
.nr_sources = ARRAY_SIZE(clkset_spi_list),
};
static struct clksrc_clk clk_spi0 = {
.clk = {
.name = "spi_bus",
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC1_SPI0_SHIFT,
.mask = S5PC100_CLKSRC1_SPI0_MASK,
.sources = &clkset_spi,
.divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT,
.reg_divider = S5PC100_CLKDIV2,
.reg_source = S5PC100_CLKSRC1,
};
static struct clksrc_clk clk_spi1 = {
.clk = {
.name = "spi_bus",
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC1_SPI1_SHIFT,
.mask = S5PC100_CLKSRC1_SPI1_MASK,
.sources = &clkset_spi,
.divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT,
.reg_divider = S5PC100_CLKDIV2,
.reg_source = S5PC100_CLKSRC1,
};
static struct clksrc_clk clk_spi2 = {
.clk = {
.name = "spi_bus",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC1_SPI2_SHIFT,
.mask = S5PC100_CLKSRC1_SPI2_MASK,
.sources = &clkset_spi,
.divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT,
.reg_divider = S5PC100_CLKDIV2,
.reg_source = S5PC100_CLKSRC1,
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
};
static struct clk_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clksrc_clk clk_uart_uclk1 = {
.clk = {
.name = "uclk1",
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
.enable = s5pc1xx_sclk0_ctrl,
.set_parent = s5pc1xx_setparent_clksrc,
.get_rate = s5pc1xx_getrate_clksrc,
.set_rate = s5pc1xx_setrate_clksrc,
.round_rate = s5pc1xx_roundrate_clksrc,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC1_UART_SHIFT,
.mask = S5PC100_CLKSRC1_UART_MASK,
.sources = &clkset_uart,
.divider_shift = S5PC100_CLKDIV2_UART_SHIFT,
.reg_divider = S5PC1XX_CLK_DIV2,
.reg_source = S5PC1XX_CLK_SRC1,
.reg_divider = S5PC100_CLKDIV2,
.reg_source = S5PC100_CLKSRC1,
};
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
.id = -1,
};
static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1",
.id = -1,
};
static struct clk clk_iis_cd2 = {
.name = "iis_cdclk2",
.id = -1,
};
static struct clk clk_pcm_cd0 = {
.name = "pcm_cdclk0",
.id = -1,
};
static struct clk clk_pcm_cd1 = {
.name = "pcm_cdclk1",
.id = -1,
};
static struct clk *clkset_audio0_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_iis_cd0,
&clk_pcm_cd0,
&clk_mout_hpll.clk,
};
static struct clk_sources clkset_audio0 = {
.sources = clkset_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_audio0_list),
};
static struct clksrc_clk clk_audio0 = {
.clk = {
.name = "audio-bus",
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC3_AUDIO0_SHIFT,
.mask = S5PC100_CLKSRC3_AUDIO0_MASK,
.sources = &clkset_audio0,
.divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT,
.reg_divider = S5PC100_CLKDIV4,
.reg_source = S5PC100_CLKSRC3,
};
static struct clk *clkset_audio1_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_iis_cd1,
&clk_pcm_cd1,
&clk_mout_hpll.clk,
};
static struct clk_sources clkset_audio1 = {
.sources = clkset_audio1_list,
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
static struct clksrc_clk clk_audio1 = {
.clk = {
.name = "audio-bus",
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
.mask = S5PC100_CLKSRC3_AUDIO1_MASK,
.sources = &clkset_audio1,
.divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT,
.reg_divider = S5PC100_CLKDIV4,
.reg_source = S5PC100_CLKSRC3,
};
static struct clk *clkset_audio2_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_iis_cd2,
&clk_mout_hpll.clk,
};
static struct clk_sources clkset_audio2 = {
.sources = clkset_audio2_list,
.nr_sources = ARRAY_SIZE(clkset_audio2_list),
};
static struct clksrc_clk clk_audio2 = {
.clk = {
.name = "audio-bus",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
.mask = S5PC100_CLKSRC3_AUDIO2_MASK,
.sources = &clkset_audio2,
.divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT,
.reg_divider = S5PC100_CLKDIV4,
.reg_source = S5PC100_CLKSRC3,
};
static struct clk *clkset_spdif_list[] = {
&clk_audio0.clk,
&clk_audio1.clk,
&clk_audio2.clk,
};
static struct clk_sources clkset_spdif = {
.sources = clkset_spdif_list,
.nr_sources = ARRAY_SIZE(clkset_spdif_list),
};
static struct clksrc_clk clk_spdif = {
.clk = {
.name = "spdif",
.id = -1,
},
.shift = S5PC100_CLKSRC3_SPDIF_SHIFT,
.mask = S5PC100_CLKSRC3_SPDIF_MASK,
.sources = &clkset_spdif,
.reg_source = S5PC100_CLKSRC3,
};
static struct clk *clkset_lcd_fimc_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_mout_hpll.clk,
&clk_vclk_54m,
};
static struct clk_sources clkset_lcd_fimc = {
.sources = clkset_lcd_fimc_list,
.nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list),
};
static struct clksrc_clk clk_lcd = {
.clk = {
.name = "lcd",
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_LCD_SHIFT,
.mask = S5PC100_CLKSRC2_LCD_MASK,
.sources = &clkset_lcd_fimc,
.divider_shift = S5PC100_CLKDIV3_LCD_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clksrc_clk clk_fimc0 = {
.clk = {
.name = "fimc",
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
.mask = S5PC100_CLKSRC2_FIMC0_MASK,
.sources = &clkset_lcd_fimc,
.divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clksrc_clk clk_fimc1 = {
.clk = {
.name = "fimc",
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
.mask = S5PC100_CLKSRC2_FIMC1_MASK,
.sources = &clkset_lcd_fimc,
.divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clksrc_clk clk_fimc2 = {
.clk = {
.name = "fimc",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
.enable = s5pc100_sclk1_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
.mask = S5PC100_CLKSRC2_FIMC2_MASK,
.sources = &clkset_lcd_fimc,
.divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clk *clkset_mmc_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_mout_hpll.clk ,
};
static struct clk_sources clkset_mmc = {
.sources = clkset_mmc_list,
.nr_sources = ARRAY_SIZE(clkset_mmc_list),
};
static struct clksrc_clk clk_mmc0 = {
.clk = {
.name = "mmc_bus",
.id = 0,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_MMC0_SHIFT,
.mask = S5PC100_CLKSRC2_MMC0_MASK,
.sources = &clkset_mmc,
.divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clksrc_clk clk_mmc1 = {
.clk = {
.name = "mmc_bus",
.id = 1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_MMC1_SHIFT,
.mask = S5PC100_CLKSRC2_MMC1_MASK,
.sources = &clkset_mmc,
.divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clksrc_clk clk_mmc2 = {
.clk = {
.name = "mmc_bus",
.id = 2,
.ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC2_MMC2_SHIFT,
.mask = S5PC100_CLKSRC2_MMC2_MASK,
.sources = &clkset_mmc,
.divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT,
.reg_divider = S5PC100_CLKDIV3,
.reg_source = S5PC100_CLKSRC2,
};
static struct clk *clkset_usbhost_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_mout_hpll.clk,
&clk_48m,
};
static struct clk_sources clkset_usbhost = {
.sources = clkset_usbhost_list,
.nr_sources = ARRAY_SIZE(clkset_usbhost_list),
};
static struct clksrc_clk clk_usbhost = {
.clk = {
.name = "usbhost",
.id = -1,
.ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
.enable = s5pc100_sclk0_ctrl,
.set_parent = s5pc100_setparent_clksrc,
.get_rate = s5pc100_getrate_clksrc,
.set_rate = s5pc100_setrate_clksrc,
.round_rate = s5pc100_roundrate_clksrc,
},
.shift = S5PC100_CLKSRC1_UHOST_SHIFT,
.mask = S5PC100_CLKSRC1_UHOST_MASK,
.sources = &clkset_usbhost,
.divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT,
.reg_divider = S5PC100_CLKDIV2,
.reg_source = S5PC100_CLKSRC1,
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_mout_am,
&clk_mout_onenand,
&clk_mout_epll,
&clk_mout_hpll,
&clk_spi0,
&clk_spi1,
&clk_spi2,
&clk_uart_uclk1,
&clk_audio0,
&clk_audio1,
&clk_audio2,
&clk_spdif,
&clk_lcd,
&clk_fimc0,
&clk_fimc1,
&clk_fimc2,
&clk_mmc0,
&clk_mmc1,
&clk_mmc2,
&clk_usbhost,
};
static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
{
struct clk_sources *srcs = clk->sources;
u32 clksrc = __raw_readl(clk->reg_source);
......@@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
clk->clk.parent = srcs->sources[clksrc];
printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
clk->clk.name, clk->clk.parent->name, clksrc,
clk_get_rate(&clk->clk));
print_mhz(clk_get_rate(&clk->clk)));
}
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
......@@ -1052,20 +1031,16 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
unsigned long hclk;
unsigned long pclkd0;
unsigned long pclk;
unsigned long apll;
unsigned long mpll;
unsigned long hpll;
unsigned long epll;
unsigned long apll, mpll, epll, hpll;
unsigned int ptr;
u32 clkdiv0, clkdiv1;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
__func__, clkdiv0, clkdiv1);
printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
......@@ -1075,48 +1050,81 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
apll, mpll, epll, hpll);
printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
print_mhz(apll), print_mhz(mpll),
print_mhz(epll), print_mhz(hpll));
armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
armclk, hclkd0, pclkd0, hclk, pclk);
printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
" PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
" PCLK=%ld.%03ld MHz\n",
print_mhz(armclk), print_mhz(hclkd0),
print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_fout_hpll.rate = hpll;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_f.rate = armclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s5pc1xx_set_clksrc(init_parents[ptr]);
s5pc100_set_clksrc(init_parents[ptr]);
}
static struct clk *clks[] __initdata = {
&clk_ext_xtal_mux,
&clk_mout_epll.clk,
&clk_fout_epll,
&clk_mout_apll.clk,
&clk_dout_apll,
&clk_dout_d0_bus,
&clk_dout_pclkd0,
&clk_dout_apll2,
&clk_mout_mpll.clk,
&clk_mout_am.clk,
&clk_dout_d1_bus,
&clk_mout_onenand.clk,
&clk_dout_pclkd1,
&clk_dout_mpll2,
&clk_dout_cam,
&clk_dout_mpll,
&clk_mout_epll.clk,
&clk_fout_epll,
&clk_iis_cd0,
&clk_iis_cd1,
&clk_iis_cd2,
&clk_pcm_cd0,
&clk_pcm_cd1,
&clk_spi0.clk,
&clk_spi1.clk,
&clk_spi2.clk,
&clk_uart_uclk1.clk,
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
&clk_54m,
&clk_audio0.clk,
&clk_audio1.clk,
&clk_audio2.clk,
&clk_spdif.clk,
&clk_lcd.clk,
&clk_fimc0.clk,
&clk_fimc1.clk,
&clk_fimc2.clk,
&clk_mmc0.clk,
&clk_mmc1.clk,
&clk_mmc2.clk,
&clk_usbhost.clk,
&clk_arm,
};
void __init s5pc100_register_clocks(void)
......@@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void)
clkp->name, ret);
}
}
clk_mpll.parent = &clk_mout_mpll.clk;
clk_epll.parent = &clk_mout_epll.clk;
}
arch/arm/plat-s5pc1xx/setup-fb-24bpp.c 0 → 100644
View file @ 602fd7c3
/*
* linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
*
* Copyright 2009 Samsung Electronics
*
* Base S5PC1XX setup information for 24bpp LCD framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-s5pc1xx.h>
#define DISR_OFFSET 0x7008
void s5pc100_fb_gpio_setup_24bpp(void)
{
unsigned int gpio = 0;
for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
arch/arm/plat-s5pc1xx/setup-i2c0.c
View file @ 602fd7c3
......@@ -17,9 +17,14 @@
struct platform_device; /* don't need the contents */
#include <linux/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
/* Pin configuration would be needed */
s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
}
arch/arm/plat-s5pc1xx/setup-i2c1.c
View file @ 602fd7c3
......@@ -17,9 +17,14 @@
struct platform_device; /* don't need the contents */
#include <linux/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
/* Pin configuration would be needed */
s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
}
arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c 0 → 100644
View file @ 602fd7c3
/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
*
* Copyright 2009 Samsung Eletronics
*
* S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/card.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
unsigned int num;
num = width;
/* In case of 8 width, we should decrease the 2 */
if (width == 8)
num = width - 2;
end = S5PC100_GPG0(2 + num);
/* Set all the necessary GPG0/GPG1 pins to special-function 0 */
for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
if (width == 8) {
for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
}
void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S5PC100_GPG2(2 + width);
/* Set all the necessary GPG2 pins to special-function 2 */
for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
}
void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S5PC100_GPG3(2 + width);
/* Set all the necessary GPG3 pins to special-function 2 */
for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
}
arch/arm/plat-samsung/Kconfig 0 → 100644
View file @ 602fd7c3
# arch/arm/plat-samsung/Kconfig
#
# Copyright 2009 Simtec Electronics
#
# Licensed under GPLv2
config PLAT_SAMSUNG
bool
depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX
default y
help
Base platform code for all Samsung SoC based systems
if PLAT_SAMSUNG
endif
arch/arm/plat-samsung/Makefile 0 → 100644
View file @ 602fd7c3
# arch/arm/plat-s3c64xx/Makefile
#
# Copyright 2009 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n := dummy.o
obj- :=
drivers/serial/s3c2410.c
View file @ 602fd7c3
......@@ -2,7 +2,7 @@
*
* Driver for Samsung S3C2410 SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
drivers/serial/s3c2412.c
View file @ 602fd7c3
......@@ -2,7 +2,7 @@
*
* Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
drivers/serial/s3c2440.c
View file @ 602fd7c3
......@@ -2,7 +2,7 @@
*
* Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
drivers/serial/s3c24a0.c
View file @ 602fd7c3
......@@ -6,7 +6,7 @@
*
* Author: Sandeep Patil <sandeep.patil@azingo.com>
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
drivers/serial/samsung.c
View file @ 602fd7c3
......@@ -2,7 +2,7 @@
*
* Driver core for Samsung SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
drivers/serial/samsung.h
View file @ 602fd7c3
......@@ -2,7 +2,7 @@
*
* Driver for Samsung SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
......
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