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Commit 604a2785 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6:
  Blackfin arch: Fix PM building on BF52x: No ROTWE on BF52x, add USBWE
  Blackfin arch: sram: use 'unsigned long' for irqflags
  Blackfin arch: let PCI depend on BROKEN
  Blackfin arch: move include/asm-blackfin header files to arch/blackfin
  Blackfin arch: fix bug - MPU crashes under stress
  Blackfin arch: Fix bug - when to rmmod the L1_module, it stucks and then reboot the board.
  Blackfin arch: dont actually need to muck with EMAC_SYSTAT for BF52x for demuxing
  Blackfin arch: Add MTD Partitions for MTD_DATAFLASH, increase max SPI SCLK
parents 66833d5f d310fb4b
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arch/blackfin/Kconfig
View file @ 604a2785
...@@ -855,6 +855,7 @@ menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" ...@@ -855,6 +855,7 @@ menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
config PCI config PCI
bool "PCI support" bool "PCI support"
depends on BROKEN
help help
Support for PCI bus. Support for PCI bus.
......
arch/blackfin/Makefile
View file @ 604a2785
...@@ -98,36 +98,20 @@ libs-y += arch/$(ARCH)/lib/ ...@@ -98,36 +98,20 @@ libs-y += arch/$(ARCH)/lib/
drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/ drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include
# Update machine arch symlinks if something which affects KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
# them changed. We use .mach to indicate when they were updated
# last, otherwise make uses the target directory mtime.
show_mach_symlink = :
quiet_show_mach_symlink = echo ' SYMLINK include/asm-$(ARCH)/mach-$(MACHINE) -> include/asm-$(ARCH)/mach'
silent_show_mach_symlink = :
include/asm-blackfin/.mach: $(wildcard include/config/arch/*.h) include/config/auto.conf
@$($(quiet)show_mach_symlink)
ifneq ($(KBUILD_SRC),)
$(Q)mkdir -p include/asm-$(ARCH)
$(Q)ln -fsn $(srctree)/include/asm-$(ARCH)/mach-$(MACHINE) include/asm-$(ARCH)/mach
else
$(Q)ln -fsn mach-$(MACHINE) include/asm-$(ARCH)/mach
endif
@touch $@
CLEAN_FILES += \ CLEAN_FILES += \
include/asm-$(ARCH)/asm-offsets.h \ arch/$(ARCH)/include/asm/asm-offsets.h \
arch/$(ARCH)/kernel/asm-offsets.s \ arch/$(ARCH)/kernel/asm-offsets.s \
include/asm-$(ARCH)/mach \
include/asm-$(ARCH)/.mach
archprepare: include/asm-blackfin/.mach
archclean: archclean:
$(Q)$(MAKE) $(clean)=$(boot) $(Q)$(MAKE) $(clean)=$(boot)
INSTALL_PATH ?= /tftpboot INSTALL_PATH ?= /tftpboot
boot := arch/$(ARCH)/boot boot := arch/$(ARCH)/boot
BOOT_TARGETS = vmImage BOOT_TARGETS = vmImage
......
include/asm-blackfin/blackfin.h → arch/blackfin/include/asm/blackfin.h
View file @ 604a2785
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#define HI(con32) (((con32) >> 16) & 0xFFFF) #define HI(con32) (((con32) >> 16) & 0xFFFF)
#define hi(con32) (((con32) >> 16) & 0xFFFF) #define hi(con32) (((con32) >> 16) & 0xFFFF)
#include <asm/mach/anomaly.h> #include <mach/anomaly.h>
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
...@@ -86,7 +86,7 @@ static inline void CSYNC(void) ...@@ -86,7 +86,7 @@ static inline void CSYNC(void)
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#include <asm/mach/blackfin.h> #include <mach/blackfin.h>
#include <asm/bfin-global.h> #include <asm/bfin-global.h>
#endif /* _BLACKFIN_H_ */ #endif /* _BLACKFIN_H_ */
include/asm-blackfin/mach-common/cdef_LPBlackfin.h → arch/blackfin/include/asm/cdef_LPBlackfin.h
View file @ 604a2785
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#warning cdef_LPBlackfin.h should only be included for 532 compatible chips. #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
#endif #endif
*/ */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/*Cache & SRAM Memory*/ /*Cache & SRAM Memory*/
#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
......
include/asm-blackfin/cplb.h → arch/blackfin/include/asm/cplb.h
View file @ 604a2785
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#define _CPLB_H #define _CPLB_H
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/mach/anomaly.h> #include <mach/anomaly.h>
#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
......
include/asm-blackfin/mach-common/def_LPBlackfin.h → arch/blackfin/include/asm/def_LPBlackfin.h
View file @ 604a2785
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#ifndef _DEF_LPBLACKFIN_H #ifndef _DEF_LPBLACKFIN_H
#define _DEF_LPBLACKFIN_H #define _DEF_LPBLACKFIN_H
#include <asm/mach/anomaly.h> #include <mach/anomaly.h>
#define MK_BMSK_(x) (1<<x) #define MK_BMSK_(x) (1<<x)
......
include/asm-blackfin/delay.h → arch/blackfin/include/asm/delay.h
View file @ 604a2785
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#ifndef __ASM_DELAY_H__ #ifndef __ASM_DELAY_H__
#define __ASM_DELAY_H__ #define __ASM_DELAY_H__
#include <asm/mach/anomaly.h> #include <mach/anomaly.h>
static inline void __delay(unsigned long loops) static inline void __delay(unsigned long loops)
{ {
......
include/asm-blackfin/dma.h → arch/blackfin/include/asm/dma.h
View file @ 604a2785
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include <asm/signal.h> #include <asm/signal.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <asm/mach/dma.h> #include <mach/dma.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
......
include/asm-blackfin/gpio.h → arch/blackfin/include/asm/gpio.h
View file @ 604a2785
...@@ -224,7 +224,7 @@ ...@@ -224,7 +224,7 @@
#endif #endif
#ifdef BF548_FAMILY #ifdef BF548_FAMILY
#include <asm-blackfin/mach-bf548/gpio.h> #include <mach/gpio.h>
#endif #endif
#ifdef BF561_FAMILY #ifdef BF561_FAMILY
......
include/asm-blackfin/irq.h → arch/blackfin/include/asm/irq.h
View file @ 604a2785
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#ifndef _BFIN_IRQ_H_ #ifndef _BFIN_IRQ_H_
#define _BFIN_IRQ_H_ #define _BFIN_IRQ_H_
#include <asm/mach/irq.h> #include <mach/irq.h>
#include <asm/ptrace.h> #include <asm/ptrace.h>
/******************************************************************************* /*******************************************************************************
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
* interrupts apart (just the TX/RX for the various devices) * interrupts apart (just the TX/RX for the various devices)
*******************************************************************************/ *******************************************************************************/
/* SYS_IRQS and NR_IRQS are defined in <asm/mach-bf5xx/irq.h>*/ /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h>*/
/* /*
* Machine specific interrupt sources. * Machine specific interrupt sources.
......
include/asm-blackfin/mem_map.h → arch/blackfin/include/asm/mem_map.h
View file @ 604a2785
...@@ -7,6 +7,6 @@ ...@@ -7,6 +7,6 @@
#ifndef _MEM_MAP_H_ #ifndef _MEM_MAP_H_
#define _MEM_MAP_H_ #define _MEM_MAP_H_
#include <asm/mach/mem_map.h> #include <mach/mem_map.h>
#endif /* _MEM_MAP_H_ */ #endif /* _MEM_MAP_H_ */
include/asm-blackfin/mmu_context.h → arch/blackfin/include/asm/mmu_context.h
View file @ 604a2785
...@@ -173,8 +173,10 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr, ...@@ -173,8 +173,10 @@ static inline void protect_page(struct mm_struct *mm, unsigned long addr,
static inline void update_protections(struct mm_struct *mm) static inline void update_protections(struct mm_struct *mm)
{ {
flush_switched_cplbs(); if (mm->context.page_rwx_mask == current_rwx_mask) {
set_mask_dcplbs(mm->context.page_rwx_mask); flush_switched_cplbs();
set_mask_dcplbs(mm->context.page_rwx_mask);
}
} }
#endif #endif
......
include/asm-blackfin/pgtable.h → arch/blackfin/include/asm/pgtable.h
View file @ 604a2785
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
#include <asm-generic/4level-fixup.h> #include <asm-generic/4level-fixup.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
typedef pte_t *pte_addr_t; typedef pte_t *pte_addr_t;
/* /*
......
include/asm-blackfin/portmux.h → arch/blackfin/include/asm/portmux.h
View file @ 604a2785
...@@ -21,7 +21,7 @@ int peripheral_request_list(const unsigned short per[], const char *label); ...@@ -21,7 +21,7 @@ int peripheral_request_list(const unsigned short per[], const char *label);
void peripheral_free_list(const unsigned short per[]); void peripheral_free_list(const unsigned short per[]);
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/mach/portmux.h> #include <mach/portmux.h>
#ifndef P_SPORT2_TFS #ifndef P_SPORT2_TFS
#define P_SPORT2_TFS P_UNDEF #define P_SPORT2_TFS P_UNDEF
......
include/asm-blackfin/system.h → arch/blackfin/include/asm/system.h
View file @ 604a2785
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/compiler.h> #include <linux/compiler.h>
#include <asm/mach/anomaly.h> #include <mach/anomaly.h>
/* /*
* Interrupt configuring macros. * Interrupt configuring macros.
......
arch/blackfin/kernel/entry.S
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#include <asm/errno.h> #include <asm/errno.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/mach-common/context.S> #include <asm/context.S>
#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
.section .l1.text .section .l1.text
......
arch/blackfin/mach-bf527/head.S
View file @ 604a2785
...@@ -31,8 +31,8 @@ ...@@ -31,8 +31,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK #ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h> #include <asm/clocks.h>
#include <asm/mach/mem_init.h> #include <mach/mem_init.h>
#endif #endif
.section .l1.text .section .l1.text
......
include/asm-blackfin/mach-bf527/cdefBF522.h → arch/blackfin/mach-bf527/include/mach/cdefBF522.h
View file @ 604a2785
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include "defBF522.h" #include "defBF522.h"
/* include core specific register pointer definitions */ /* include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
......
include/asm-blackfin/mach-bf527/cdefBF525.h → arch/blackfin/mach-bf527/include/mach/cdefBF525.h
View file @ 604a2785
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include "defBF525.h" #include "defBF525.h"
/* include core specific register pointer definitions */ /* include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
......
include/asm-blackfin/mach-bf527/cdefBF527.h → arch/blackfin/mach-bf527/include/mach/cdefBF527.h
View file @ 604a2785
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include "defBF527.h" #include "defBF527.h"
/* include core specific register pointer definitions */ /* include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
......
include/asm-blackfin/mach-bf527/cdefBF52x_base.h → arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
View file @ 604a2785
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
#include "defBF52x_base.h" #include "defBF52x_base.h"
/* Include core specific register pointer definitions */ /* Include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* ==== begin from cdefBF534.h ==== */ /* ==== begin from cdefBF534.h ==== */
......
include/asm-blackfin/mach-bf527/defBF522.h → arch/blackfin/mach-bf527/include/mach/defBF522.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF522_H #define _DEF_BF522_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
......
include/asm-blackfin/mach-bf527/defBF525.h → arch/blackfin/mach-bf527/include/mach/defBF525.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF525_H #define _DEF_BF525_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
......
include/asm-blackfin/mach-bf527/defBF527.h → arch/blackfin/mach-bf527/include/mach/defBF527.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF527_H #define _DEF_BF527_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
......
include/asm-blackfin/mach-bf527/defBF52x_base.h → arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View file @ 604a2785
...@@ -151,7 +151,7 @@ ...@@ -151,7 +151,7 @@
#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
...@@ -634,18 +634,9 @@ ...@@ -634,18 +634,9 @@
/* PLL_DIV Macros */ /* PLL_DIV Macros */
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
/* VR_CTL Masks */ /* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ #define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define GAIN_10 0x0004 /* GAIN = 10 */
#define GAIN_20 0x0008 /* GAIN = 20 */
#define GAIN_50 0x000C /* GAIN = 50 */
#define VLEV 0x00F0 /* Internal Voltage Level */ #define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
...@@ -660,7 +651,7 @@ ...@@ -660,7 +651,7 @@
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ #define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
...@@ -697,16 +688,16 @@ ...@@ -697,16 +688,16 @@
#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
#define IRQ_TWI 0x00000200 /* TWI Interrupt */ #define IRQ_TWI 0x00000200 /* TWI Interrupt */
#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
...@@ -801,7 +792,7 @@ ...@@ -801,7 +792,7 @@
#define WDEV_NONE 0x0006 /* no event on roll over */ #define WDEV_NONE 0x0006 /* no event on roll over */
#define WDEN 0x0FF0 /* enable watchdog */ #define WDEN 0x0FF0 /* enable watchdog */
#define WDDIS 0x0AD0 /* disable watchdog */ #define WDDIS 0x0AD0 /* disable watchdog */
#define WDRO 0x8000 /* watchdog rolled over latch */ #define WDRO 0x8000 /* watchdog rolled over latch */
/* depreciated WDOG_CTL Register Masks for legacy code */ /* depreciated WDOG_CTL Register Masks for legacy code */
...@@ -882,7 +873,7 @@ ...@@ -882,7 +873,7 @@
#define NINT 0x01 /* Pending Interrupt */ #define NINT 0x01 /* Pending Interrupt */
#define IIR_TX_READY 0x02 /* UART_THR empty */ #define IIR_TX_READY 0x02 /* UART_THR empty */
#define IIR_RX_READY 0x04 /* Receive data ready */ #define IIR_RX_READY 0x04 /* Receive data ready */
#define IIR_LINE_CHANGE 0x06 /* Receive line status */ #define IIR_LINE_CHANGE 0x06 /* Receive line status */
#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
/* UARTx_GCTL Masks */ /* UARTx_GCTL Masks */
...@@ -1638,12 +1629,12 @@ ...@@ -1638,12 +1629,12 @@
/* entry addresses of the user-callable Boot ROM functions */ /* entry addresses of the user-callable Boot ROM functions */
#define _BOOTROM_RESET 0xEF000000 #define _BOOTROM_RESET 0xEF000000
#define _BOOTROM_FINAL_INIT 0xEF000002 #define _BOOTROM_FINAL_INIT 0xEF000002
#define _BOOTROM_DO_MEMORY_DMA 0xEF000006 #define _BOOTROM_DO_MEMORY_DMA 0xEF000006
#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
...@@ -1771,71 +1762,71 @@ ...@@ -1771,71 +1762,71 @@
/* Bit masks for CNT_CONFIG */ /* Bit masks for CNT_CONFIG */
#define CNTE 0x1 /* Counter Enable */ #define CNTE 0x1 /* Counter Enable */
#define nCNTE 0x0 #define nCNTE 0x0
#define DEBE 0x2 /* Debounce Enable */ #define DEBE 0x2 /* Debounce Enable */
#define nDEBE 0x0 #define nDEBE 0x0
#define CDGINV 0x10 /* CDG Pin Polarity Invert */ #define CDGINV 0x10 /* CDG Pin Polarity Invert */
#define nCDGINV 0x0 #define nCDGINV 0x0
#define CUDINV 0x20 /* CUD Pin Polarity Invert */ #define CUDINV 0x20 /* CUD Pin Polarity Invert */
#define nCUDINV 0x0 #define nCUDINV 0x0
#define CZMINV 0x40 /* CZM Pin Polarity Invert */ #define CZMINV 0x40 /* CZM Pin Polarity Invert */
#define nCZMINV 0x0 #define nCZMINV 0x0
#define CNTMODE 0x700 /* Counter Operating Mode */ #define CNTMODE 0x700 /* Counter Operating Mode */
#define ZMZC 0x800 /* CZM Zeroes Counter Enable */ #define ZMZC 0x800 /* CZM Zeroes Counter Enable */
#define nZMZC 0x0 #define nZMZC 0x0
#define BNDMODE 0x3000 /* Boundary register Mode */ #define BNDMODE 0x3000 /* Boundary register Mode */
#define INPDIS 0x8000 /* CUG and CDG Input Disable */ #define INPDIS 0x8000 /* CUG and CDG Input Disable */
#define nINPDIS 0x0 #define nINPDIS 0x0
/* Bit masks for CNT_IMASK */ /* Bit masks for CNT_IMASK */
#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
#define nICIE 0x0 #define nICIE 0x0
#define UCIE 0x2 /* Up count Interrupt Enable */ #define UCIE 0x2 /* Up count Interrupt Enable */
#define nUCIE 0x0 #define nUCIE 0x0
#define DCIE 0x4 /* Down count Interrupt Enable */ #define DCIE 0x4 /* Down count Interrupt Enable */
#define nDCIE 0x0 #define nDCIE 0x0
#define MINCIE 0x8 /* Min Count Interrupt Enable */ #define MINCIE 0x8 /* Min Count Interrupt Enable */
#define nMINCIE 0x0 #define nMINCIE 0x0
#define MAXCIE 0x10 /* Max Count Interrupt Enable */ #define MAXCIE 0x10 /* Max Count Interrupt Enable */
#define nMAXCIE 0x0 #define nMAXCIE 0x0
#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
#define nCOV31IE 0x0 #define nCOV31IE 0x0
#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
#define nCOV15IE 0x0 #define nCOV15IE 0x0
#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
#define nCZEROIE 0x0 #define nCZEROIE 0x0
#define CZMIE 0x100 /* CZM Pin Interrupt Enable */ #define CZMIE 0x100 /* CZM Pin Interrupt Enable */
#define nCZMIE 0x0 #define nCZMIE 0x0
#define CZMEIE 0x200 /* CZM Error Interrupt Enable */ #define CZMEIE 0x200 /* CZM Error Interrupt Enable */
#define nCZMEIE 0x0 #define nCZMEIE 0x0
#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
#define nCZMZIE 0x0 #define nCZMZIE 0x0
/* Bit masks for CNT_STATUS */ /* Bit masks for CNT_STATUS */
#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
#define nICII 0x0 #define nICII 0x0
#define UCII 0x2 /* Up count Interrupt Identifier */ #define UCII 0x2 /* Up count Interrupt Identifier */
#define nUCII 0x0 #define nUCII 0x0
#define DCII 0x4 /* Down count Interrupt Identifier */ #define DCII 0x4 /* Down count Interrupt Identifier */
#define nDCII 0x0 #define nDCII 0x0
#define MINCII 0x8 /* Min Count Interrupt Identifier */ #define MINCII 0x8 /* Min Count Interrupt Identifier */
#define nMINCII 0x0 #define nMINCII 0x0
#define MAXCII 0x10 /* Max Count Interrupt Identifier */ #define MAXCII 0x10 /* Max Count Interrupt Identifier */
#define nMAXCII 0x0 #define nMAXCII 0x0
#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
#define nCOV31II 0x0 #define nCOV31II 0x0
#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
#define nCOV15II 0x0 #define nCOV15II 0x0
#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
#define nCZEROII 0x0 #define nCZEROII 0x0
#define CZMII 0x100 /* CZM Pin Interrupt Identifier */ #define CZMII 0x100 /* CZM Pin Interrupt Identifier */
#define nCZMII 0x0 #define nCZMII 0x0
#define CZMEII 0x200 /* CZM Error Interrupt Identifier */ #define CZMEII 0x200 /* CZM Error Interrupt Identifier */
#define nCZMEII 0x0 #define nCZMEII 0x0
#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
#define nCZMZII 0x0 #define nCZMZII 0x0
/* Bit masks for CNT_COMMAND */ /* Bit masks for CNT_COMMAND */
...@@ -1843,7 +1834,7 @@ ...@@ -1843,7 +1834,7 @@
#define W1LMIN 0xf0 /* Load Min Register */ #define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */ #define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
#define nW1ZMONCE 0x0 #define nW1ZMONCE 0x0
/* Bit masks for CNT_DEBOUNCE */ /* Bit masks for CNT_DEBOUNCE */
...@@ -1853,15 +1844,15 @@ ...@@ -1853,15 +1844,15 @@
#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
#define nFIEN 0x0 #define nFIEN 0x0
#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
#define nFTESTDEC 0x0 #define nFTESTDEC 0x0
#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ #define FWRTEST 0x2000 /* OTP/Fuse Write Test */
#define nFWRTEST 0x0 #define nFWRTEST 0x0
#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ #define FRDEN 0x4000 /* OTP/Fuse Read Enable */
#define nFRDEN 0x0 #define nFRDEN 0x0
#define FWREN 0x8000 /* OTP/Fuse Write Enable */ #define FWREN 0x8000 /* OTP/Fuse Write Enable */
#define nFWREN 0x0 #define nFWREN 0x0
/* Bit masks for OTP_BEN */ /* Bit masks for OTP_BEN */
...@@ -1870,15 +1861,15 @@ ...@@ -1870,15 +1861,15 @@
/* Bit masks for OTP_STATUS */ /* Bit masks for OTP_STATUS */
#define FCOMP 0x1 /* OTP/Fuse Access Complete */ #define FCOMP 0x1 /* OTP/Fuse Access Complete */
#define nFCOMP 0x0 #define nFCOMP 0x0
#define FERROR 0x2 /* OTP/Fuse Access Error */ #define FERROR 0x2 /* OTP/Fuse Access Error */
#define nFERROR 0x0 #define nFERROR 0x0
#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
#define nMMRGLOAD 0x0 #define nMMRGLOAD 0x0
#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
#define nMMRGLOCK 0x0 #define nMMRGLOCK 0x0
#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ #define FPGMEN 0x40 /* OTP/Fuse Program Enable */
#define nFPGMEN 0x0 #define nFPGMEN 0x0
/* Bit masks for OTP_TIMING */ /* Bit masks for OTP_TIMING */
...@@ -1892,42 +1883,42 @@ ...@@ -1892,42 +1883,42 @@
/* Bit masks for SECURE_SYSSWT */ /* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */ #define EMUDABL 0x1 /* Emulation Disable. */
#define nEMUDABL 0x0 #define nEMUDABL 0x0
#define RSTDABL 0x2 /* Reset Disable */ #define RSTDABL 0x2 /* Reset Disable */
#define nRSTDABL 0x0 #define nRSTDABL 0x0
#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ #define DMA0OVR 0x800 /* DMA0 Memory Access Override */
#define nDMA0OVR 0x0 #define nDMA0OVR 0x0
#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
#define nDMA1OVR 0x0 #define nDMA1OVR 0x0
#define EMUOVR 0x4000 /* Emulation Override */ #define EMUOVR 0x4000 /* Emulation Override */
#define nEMUOVR 0x0 #define nEMUOVR 0x0
#define OTPSEN 0x8000 /* OTP Secrets Enable. */ #define OTPSEN 0x8000 /* OTP Secrets Enable. */
#define nOTPSEN 0x0 #define nOTPSEN 0x0
#define L2DABL 0x70000 /* L2 Memory Disable. */ #define L2DABL 0x70000 /* L2 Memory Disable. */
/* Bit masks for SECURE_CONTROL */ /* Bit masks for SECURE_CONTROL */
#define SECURE0 0x1 /* SECURE 0 */ #define SECURE0 0x1 /* SECURE 0 */
#define nSECURE0 0x0 #define nSECURE0 0x0
#define SECURE1 0x2 /* SECURE 1 */ #define SECURE1 0x2 /* SECURE 1 */
#define nSECURE1 0x0 #define nSECURE1 0x0
#define SECURE2 0x4 /* SECURE 2 */ #define SECURE2 0x4 /* SECURE 2 */
#define nSECURE2 0x0 #define nSECURE2 0x0
#define SECURE3 0x8 /* SECURE 3 */ #define SECURE3 0x8 /* SECURE 3 */
#define nSECURE3 0x0 #define nSECURE3 0x0
/* Bit masks for SECURE_STATUS */ /* Bit masks for SECURE_STATUS */
#define SECMODE 0x3 /* Secured Mode Control State */ #define SECMODE 0x3 /* Secured Mode Control State */
#define NMI 0x4 /* Non Maskable Interrupt */ #define NMI 0x4 /* Non Maskable Interrupt */
#define nNMI 0x0 #define nNMI 0x0
#define AFVALID 0x8 /* Authentication Firmware Valid */ #define AFVALID 0x8 /* Authentication Firmware Valid */
#define nAFVALID 0x0 #define nAFVALID 0x0
#define AFEXIT 0x10 /* Authentication Firmware Exit */ #define AFEXIT 0x10 /* Authentication Firmware Exit */
#define nAFEXIT 0x0 #define nAFEXIT 0x0
#define SECSTAT 0xe0 /* Secure Status */ #define SECSTAT 0xe0 /* Secure Status */
/* Bit masks for NFC_CTL */ /* Bit masks for NFC_CTL */
...@@ -1935,60 +1926,60 @@ ...@@ -1935,60 +1926,60 @@
#define WR_DLY 0xf /* Write Strobe Delay */ #define WR_DLY 0xf /* Write Strobe Delay */
#define RD_DLY 0xf0 /* Read Strobe Delay */ #define RD_DLY 0xf0 /* Read Strobe Delay */
#define NWIDTH 0x100 /* NAND Data Width */ #define NWIDTH 0x100 /* NAND Data Width */
#define nNWIDTH 0x0 #define nNWIDTH 0x0
#define PG_SIZE 0x200 /* Page Size */ #define PG_SIZE 0x200 /* Page Size */
#define nPG_SIZE 0x0 #define nPG_SIZE 0x0
/* Bit masks for NFC_STAT */ /* Bit masks for NFC_STAT */
#define NBUSY 0x1 /* Not Busy */ #define NBUSY 0x1 /* Not Busy */
#define nNBUSY 0x0 #define nNBUSY 0x0
#define WB_FULL 0x2 /* Write Buffer Full */ #define WB_FULL 0x2 /* Write Buffer Full */
#define nWB_FULL 0x0 #define nWB_FULL 0x0
#define PG_WR_STAT 0x4 /* Page Write Pending */ #define PG_WR_STAT 0x4 /* Page Write Pending */
#define nPG_WR_STAT 0x0 #define nPG_WR_STAT 0x0
#define PG_RD_STAT 0x8 /* Page Read Pending */ #define PG_RD_STAT 0x8 /* Page Read Pending */
#define nPG_RD_STAT 0x0 #define nPG_RD_STAT 0x0
#define WB_EMPTY 0x10 /* Write Buffer Empty */ #define WB_EMPTY 0x10 /* Write Buffer Empty */
#define nWB_EMPTY 0x0 #define nWB_EMPTY 0x0
/* Bit masks for NFC_IRQSTAT */ /* Bit masks for NFC_IRQSTAT */
#define NBUSYIRQ 0x1 /* Not Busy IRQ */ #define NBUSYIRQ 0x1 /* Not Busy IRQ */
#define nNBUSYIRQ 0x0 #define nNBUSYIRQ 0x0
#define WB_OVF 0x2 /* Write Buffer Overflow */ #define WB_OVF 0x2 /* Write Buffer Overflow */
#define nWB_OVF 0x0 #define nWB_OVF 0x0
#define WB_EDGE 0x4 /* Write Buffer Edge Detect */ #define WB_EDGE 0x4 /* Write Buffer Edge Detect */
#define nWB_EDGE 0x0 #define nWB_EDGE 0x0
#define RD_RDY 0x8 /* Read Data Ready */ #define RD_RDY 0x8 /* Read Data Ready */
#define nRD_RDY 0x0 #define nRD_RDY 0x0
#define WR_DONE 0x10 /* Page Write Done */ #define WR_DONE 0x10 /* Page Write Done */
#define nWR_DONE 0x0 #define nWR_DONE 0x0
/* Bit masks for NFC_IRQMASK */ /* Bit masks for NFC_IRQMASK */
#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
#define nMASK_BUSYIRQ 0x0 #define nMASK_BUSYIRQ 0x0
#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
#define nMASK_WBOVF 0x0 #define nMASK_WBOVF 0x0
#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
#define nMASK_WBEMPTY 0x0 #define nMASK_WBEMPTY 0x0
#define MASK_RDRDY 0x8 /* Mask Read Data Ready */ #define MASK_RDRDY 0x8 /* Mask Read Data Ready */
#define nMASK_RDRDY 0x0 #define nMASK_RDRDY 0x0
#define MASK_WRDONE 0x10 /* Mask Write Done */ #define MASK_WRDONE 0x10 /* Mask Write Done */
#define nMASK_WRDONE 0x0 #define nMASK_WRDONE 0x0
/* Bit masks for NFC_RST */ /* Bit masks for NFC_RST */
#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
#define nECC_RST 0x0 #define nECC_RST 0x0
/* Bit masks for NFC_PGCTL */ /* Bit masks for NFC_PGCTL */
#define PG_RD_START 0x1 /* Page Read Start */ #define PG_RD_START 0x1 /* Page Read Start */
#define nPG_RD_START 0x0 #define nPG_RD_START 0x0
#define PG_WR_START 0x2 /* Page Write Start */ #define PG_WR_START 0x2 /* Page Write Start */
#define nPG_WR_START 0x0 #define nPG_WR_START 0x0
/* Bit masks for NFC_ECC0 */ /* Bit masks for NFC_ECC0 */
......
arch/blackfin/mach-bf533/head.S
View file @ 604a2785
...@@ -31,8 +31,8 @@ ...@@ -31,8 +31,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK #ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h> #include <asm/clocks.h>
#include <asm/mach/mem_init.h> #include <mach/mem_init.h>
#endif #endif
.section .l1.text .section .l1.text
......
include/asm-blackfin/mach-bf533/cdefBF532.h → arch/blackfin/mach-bf533/include/mach/cdefBF532.h
View file @ 604a2785
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
#include "defBF532.h" #include "defBF532.h"
/*include core specific register pointer definitions*/ /*include core specific register pointer definitions*/
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
#include <asm/system.h> #include <asm/system.h>
......
include/asm-blackfin/mach-bf533/defBF532.h → arch/blackfin/mach-bf533/include/mach/defBF532.h
View file @ 604a2785
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
#define _DEF_BF532_H #define _DEF_BF532_H
/* include all Core registers and bit definitions */ /* include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/*********************************************************************************** */ /*********************************************************************************** */
/* System MMR Register Map */ /* System MMR Register Map */
......
arch/blackfin/mach-bf537/boards/stamp.c
View file @ 604a2785
...@@ -584,6 +584,30 @@ static struct bfin5xx_spi_chip spidev_chip_info = { ...@@ -584,6 +584,30 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
#if defined(CONFIG_MTD_DATAFLASH) \ #if defined(CONFIG_MTD_DATAFLASH) \
|| defined(CONFIG_MTD_DATAFLASH_MODULE) || defined(CONFIG_MTD_DATAFLASH_MODULE)
static struct mtd_partition bfin_spi_dataflash_partitions[] = {
{
.name = "bootloader(spi)",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_CAP_ROM
}, {
.name = "linux kernel(spi)",
.size = 0xe0000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(spi)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
static struct flash_platform_data bfin_spi_dataflash_data = {
.name = "SPI Dataflash",
.parts = bfin_spi_dataflash_partitions,
.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
};
/* DataFlash chip */ /* DataFlash chip */
static struct bfin5xx_spi_chip data_flash_chip_info = { static struct bfin5xx_spi_chip data_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/ .enable_dma = 0, /* use dma transfer with this chip*/
...@@ -609,9 +633,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { ...@@ -609,9 +633,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
|| defined(CONFIG_MTD_DATAFLASH_MODULE) || defined(CONFIG_MTD_DATAFLASH_MODULE)
{ /* DataFlash chip */ { /* DataFlash chip */
.modalias = "mtd_dataflash", .modalias = "mtd_dataflash",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */ .bus_num = 0, /* Framework bus number */
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
.platform_data = &bfin_spi_dataflash_data,
.controller_data = &data_flash_chip_info, .controller_data = &data_flash_chip_info,
.mode = SPI_MODE_3, .mode = SPI_MODE_3,
}, },
......
arch/blackfin/mach-bf537/head.S
View file @ 604a2785
...@@ -31,8 +31,8 @@ ...@@ -31,8 +31,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK #ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h> #include <asm/clocks.h>
#include <asm/mach/mem_init.h> #include <mach/mem_init.h>
#endif #endif
.section .l1.text .section .l1.text
......
include/asm-blackfin/mach-bf537/cdefBF534.h → arch/blackfin/mach-bf537/include/mach/cdefBF534.h
View file @ 604a2785
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
#include "defBF534.h" #include "defBF534.h"
/* Include core specific register pointer definitions */ /* Include core specific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
#include <asm/system.h> #include <asm/system.h>
......
include/asm-blackfin/mach-bf537/defBF534.h → arch/blackfin/mach-bf537/include/mach/defBF534.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF534_H #define _DEF_BF534_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/************************************************************************************ /************************************************************************************
** System MMR Register Map ** System MMR Register Map
......
include/asm-blackfin/mach-bf537/defBF537.h → arch/blackfin/mach-bf537/include/mach/defBF537.h
View file @ 604a2785
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#define _DEF_BF537_H #define _DEF_BF537_H
/* Include all Core registers and bit definitions*/ /* Include all Core registers and bit definitions*/
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* Include all MMR and bit defines common to BF534 */ /* Include all MMR and bit defines common to BF534 */
#include "defBF534.h" #include "defBF534.h"
......
arch/blackfin/mach-bf548/boards/cm_bf548.c
View file @ 604a2785
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/nand.h> #include <asm/nand.h>
#include <asm/portmux.h> #include <asm/portmux.h>
#include <asm/mach/bf54x_keys.h> #include <mach/bf54x_keys.h>
#include <asm/dpmc.h> #include <asm/dpmc.h>
#include <linux/input.h> #include <linux/input.h>
#include <linux/spi/ad7877.h> #include <linux/spi/ad7877.h>
...@@ -61,7 +61,7 @@ const char bfin_board_name[] = "Bluetechnix CM-BF548"; ...@@ -61,7 +61,7 @@ const char bfin_board_name[] = "Bluetechnix CM-BF548";
#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
#include <asm/mach/bf54x-lq043.h> #include <mach/bf54x-lq043.h>
static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
.width = 480, .width = 480,
......
arch/blackfin/mach-bf548/boards/ezkit.c
View file @ 604a2785
...@@ -48,7 +48,7 @@ ...@@ -48,7 +48,7 @@
#include <asm/nand.h> #include <asm/nand.h>
#include <asm/dpmc.h> #include <asm/dpmc.h>
#include <asm/portmux.h> #include <asm/portmux.h>
#include <asm/mach/bf54x_keys.h> #include <mach/bf54x_keys.h>
#include <linux/input.h> #include <linux/input.h>
#include <linux/spi/ad7877.h> #include <linux/spi/ad7877.h>
...@@ -106,7 +106,7 @@ arch_initcall(bfin_isp1761_init); ...@@ -106,7 +106,7 @@ arch_initcall(bfin_isp1761_init);
#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
#include <asm/mach/bf54x-lq043.h> #include <mach/bf54x-lq043.h>
static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
.width = 480, .width = 480,
......
arch/blackfin/mach-bf548/head.S
View file @ 604a2785
...@@ -31,8 +31,8 @@ ...@@ -31,8 +31,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK #ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h> #include <asm/clocks.h>
#include <asm/mach/mem_init.h> #include <mach/mem_init.h>
#endif #endif
.section .l1.text .section .l1.text
......
include/asm-blackfin/mach-bf548/cdefBF542.h → arch/blackfin/mach-bf548/include/mach/cdefBF542.h
View file @ 604a2785
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include "defBF542.h" #include "defBF542.h"
/* include core sbfin_read_()ecific register pointer definitions */ /* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
......
include/asm-blackfin/mach-bf548/cdefBF544.h → arch/blackfin/mach-bf548/include/mach/cdefBF544.h
View file @ 604a2785
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include "defBF544.h" #include "defBF544.h"
/* include core sbfin_read_()ecific register pointer definitions */ /* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
......
include/asm-blackfin/mach-bf548/cdefBF547.h → arch/blackfin/mach-bf548/include/mach/cdefBF547.h
View file @ 604a2785
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include "defBF548.h" #include "defBF548.h"
/* include core sbfin_read_()ecific register pointer definitions */ /* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
......
include/asm-blackfin/mach-bf548/cdefBF548.h → arch/blackfin/mach-bf548/include/mach/cdefBF548.h
View file @ 604a2785
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include "defBF548.h" #include "defBF548.h"
/* include core sbfin_read_()ecific register pointer definitions */ /* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
......
include/asm-blackfin/mach-bf548/cdefBF549.h → arch/blackfin/mach-bf548/include/mach/cdefBF549.h
View file @ 604a2785
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include "defBF549.h" #include "defBF549.h"
/* include core sbfin_read_()ecific register pointer definitions */ /* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
......
include/asm-blackfin/mach-bf548/defBF542.h → arch/blackfin/mach-bf548/include/mach/defBF542.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF542_H #define _DEF_BF542_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
......
include/asm-blackfin/mach-bf548/defBF544.h → arch/blackfin/mach-bf548/include/mach/defBF544.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF544_H #define _DEF_BF544_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
......
include/asm-blackfin/mach-bf548/defBF547.h → arch/blackfin/mach-bf548/include/mach/defBF547.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF548_H #define _DEF_BF548_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
......
include/asm-blackfin/mach-bf548/defBF548.h → arch/blackfin/mach-bf548/include/mach/defBF548.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF548_H #define _DEF_BF548_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
......
include/asm-blackfin/mach-bf548/defBF549.h → arch/blackfin/mach-bf548/include/mach/defBF549.h
View file @ 604a2785
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#define _DEF_BF549_H #define _DEF_BF549_H
/* Include all Core registers and bit definitions */ /* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
......
arch/blackfin/mach-bf561/head.S
View file @ 604a2785
...@@ -31,8 +31,8 @@ ...@@ -31,8 +31,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK #ifdef CONFIG_BFIN_KERNEL_CLOCK
#include <asm/mach-common/clocks.h> #include <asm/clocks.h>
#include <asm/mach/mem_init.h> #include <mach/mem_init.h>
#endif #endif
.section .l1.text .section .l1.text
......
include/asm-blackfin/mach-bf561/cdefBF561.h → arch/blackfin/mach-bf561/include/mach/cdefBF561.h
View file @ 604a2785
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
#include "defBF561.h" #include "defBF561.h"
/*include core specific register pointer definitions*/ /*include core specific register pointer definitions*/
#include <asm/mach-common/cdef_LPBlackfin.h> #include <asm/cdef_LPBlackfin.h>
#include <asm/system.h> #include <asm/system.h>
......
include/asm-blackfin/mach-bf561/defBF561.h → arch/blackfin/mach-bf561/include/mach/defBF561.h
View file @ 604a2785
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
#endif #endif
*/ */
/* include all Core registers and bit definitions */ /* include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h> #include <asm/def_LPBlackfin.h>
/*********************************************************************************** */ /*********************************************************************************** */
/* System MMR Register Map */ /* System MMR Register Map */
......
arch/blackfin/mach-common/arch_checks.c
View file @ 604a2785
...@@ -28,8 +28,8 @@ ...@@ -28,8 +28,8 @@
*/ */
#include <asm/fixed_code.h> #include <asm/fixed_code.h>
#include <asm/mach/anomaly.h> #include <mach/anomaly.h>
#include <asm/mach-common/clocks.h> #include <asm/clocks.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK #ifdef CONFIG_BFIN_KERNEL_CLOCK
......
arch/blackfin/mach-common/dpmc_modes.S
View file @ 604a2785
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/mach/irq.h> #include <mach/irq.h>
#include <asm/dpmc.h> #include <asm/dpmc.h>
.section .l1.text .section .l1.text
......
arch/blackfin/mach-common/entry.S
View file @ 604a2785
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/trace.h> #include <asm/trace.h>
#include <asm/mach-common/context.S> #include <asm/context.S>
#if defined(CONFIG_BFIN_SCRATCH_REG_RETN) #if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
# define EX_SCRATCH_REG RETN # define EX_SCRATCH_REG RETN
......
arch/blackfin/mach-common/interrupt.S
View file @ 604a2785
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
*/ */
#include <asm/blackfin.h> #include <asm/blackfin.h>
#include <asm/mach/irq.h> #include <mach/irq.h>
#include <linux/linkage.h> #include <linux/linkage.h>
#include <asm/entry.h> #include <asm/entry.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
#include <asm/traps.h> #include <asm/traps.h>
#include <asm/thread_info.h> #include <asm/thread_info.h>
#include <asm/mach-common/context.S> #include <asm/context.S>
.extern _ret_from_exception .extern _ret_from_exception
......
arch/blackfin/mach-common/ints-priority.c
View file @ 604a2785
...@@ -216,7 +216,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state) ...@@ -216,7 +216,7 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
wakeup |= KPADWE; wakeup |= KPADWE;
break; break;
#endif #endif
#ifdef IRQ_CNT #ifdef CONFIG_BF54x
case IRQ_CNT: case IRQ_CNT:
wakeup |= ROTWE; wakeup |= ROTWE;
break; break;
...@@ -983,7 +983,7 @@ int __init init_arch_irq(void) ...@@ -983,7 +983,7 @@ int __init init_arch_irq(void)
local_irq_disable(); local_irq_disable();
#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF537) #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
/* Clear EMAC Interrupt Status bits so we can demux it later */ /* Clear EMAC Interrupt Status bits so we can demux it later */
bfin_write_EMAC_SYSTAT(-1); bfin_write_EMAC_SYSTAT(-1);
#endif #endif
......
arch/blackfin/mm/blackfin_sram.c
View file @ 604a2785
...@@ -335,7 +335,7 @@ static int _sram_free(const void *addr, ...@@ -335,7 +335,7 @@ static int _sram_free(const void *addr,
plast->size += pavail->size; plast->size += pavail->size;
kmem_cache_free(sram_piece_cache, pavail); kmem_cache_free(sram_piece_cache, pavail);
} else { } else {
pavail->next = plast; pavail->next = plast->next;
plast->next = pavail; plast->next = pavail;
plast = pavail; plast = pavail;
} }
...@@ -379,7 +379,7 @@ EXPORT_SYMBOL(sram_free); ...@@ -379,7 +379,7 @@ EXPORT_SYMBOL(sram_free);
void *l1_data_A_sram_alloc(size_t size) void *l1_data_A_sram_alloc(size_t size)
{ {
unsigned flags; unsigned long flags;
void *addr = NULL; void *addr = NULL;
/* add mutex operation */ /* add mutex operation */
...@@ -402,7 +402,7 @@ EXPORT_SYMBOL(l1_data_A_sram_alloc); ...@@ -402,7 +402,7 @@ EXPORT_SYMBOL(l1_data_A_sram_alloc);
int l1_data_A_sram_free(const void *addr) int l1_data_A_sram_free(const void *addr)
{ {
unsigned flags; unsigned long flags;
int ret; int ret;
/* add mutex operation */ /* add mutex operation */
...@@ -425,7 +425,7 @@ EXPORT_SYMBOL(l1_data_A_sram_free); ...@@ -425,7 +425,7 @@ EXPORT_SYMBOL(l1_data_A_sram_free);
void *l1_data_B_sram_alloc(size_t size) void *l1_data_B_sram_alloc(size_t size)
{ {
#if L1_DATA_B_LENGTH != 0 #if L1_DATA_B_LENGTH != 0
unsigned flags; unsigned long flags;
void *addr; void *addr;
/* add mutex operation */ /* add mutex operation */
...@@ -450,7 +450,7 @@ EXPORT_SYMBOL(l1_data_B_sram_alloc); ...@@ -450,7 +450,7 @@ EXPORT_SYMBOL(l1_data_B_sram_alloc);
int l1_data_B_sram_free(const void *addr) int l1_data_B_sram_free(const void *addr)
{ {
#if L1_DATA_B_LENGTH != 0 #if L1_DATA_B_LENGTH != 0
unsigned flags; unsigned long flags;
int ret; int ret;
/* add mutex operation */ /* add mutex operation */
...@@ -504,7 +504,7 @@ EXPORT_SYMBOL(l1_data_sram_free); ...@@ -504,7 +504,7 @@ EXPORT_SYMBOL(l1_data_sram_free);
void *l1_inst_sram_alloc(size_t size) void *l1_inst_sram_alloc(size_t size)
{ {
#if L1_CODE_LENGTH != 0 #if L1_CODE_LENGTH != 0
unsigned flags; unsigned long flags;
void *addr; void *addr;
/* add mutex operation */ /* add mutex operation */
...@@ -529,7 +529,7 @@ EXPORT_SYMBOL(l1_inst_sram_alloc); ...@@ -529,7 +529,7 @@ EXPORT_SYMBOL(l1_inst_sram_alloc);
int l1_inst_sram_free(const void *addr) int l1_inst_sram_free(const void *addr)
{ {
#if L1_CODE_LENGTH != 0 #if L1_CODE_LENGTH != 0
unsigned flags; unsigned long flags;
int ret; int ret;
/* add mutex operation */ /* add mutex operation */
...@@ -551,7 +551,7 @@ EXPORT_SYMBOL(l1_inst_sram_free); ...@@ -551,7 +551,7 @@ EXPORT_SYMBOL(l1_inst_sram_free);
/* L1 Scratchpad memory allocate function */ /* L1 Scratchpad memory allocate function */
void *l1sram_alloc(size_t size) void *l1sram_alloc(size_t size)
{ {
unsigned flags; unsigned long flags;
void *addr; void *addr;
/* add mutex operation */ /* add mutex operation */
...@@ -569,7 +569,7 @@ void *l1sram_alloc(size_t size) ...@@ -569,7 +569,7 @@ void *l1sram_alloc(size_t size)
/* L1 Scratchpad memory allocate function */ /* L1 Scratchpad memory allocate function */
void *l1sram_alloc_max(size_t *psize) void *l1sram_alloc_max(size_t *psize)
{ {
unsigned flags; unsigned long flags;
void *addr; void *addr;
/* add mutex operation */ /* add mutex operation */
...@@ -587,7 +587,7 @@ void *l1sram_alloc_max(size_t *psize) ...@@ -587,7 +587,7 @@ void *l1sram_alloc_max(size_t *psize)
/* L1 Scratchpad memory free function */ /* L1 Scratchpad memory free function */
int l1sram_free(const void *addr) int l1sram_free(const void *addr)
{ {
unsigned flags; unsigned long flags;
int ret; int ret;
/* add mutex operation */ /* add mutex operation */
...@@ -605,7 +605,7 @@ int l1sram_free(const void *addr) ...@@ -605,7 +605,7 @@ int l1sram_free(const void *addr)
void *l2_sram_alloc(size_t size) void *l2_sram_alloc(size_t size)
{ {
#if L2_LENGTH != 0 #if L2_LENGTH != 0
unsigned flags; unsigned long flags;
void *addr; void *addr;
/* add mutex operation */ /* add mutex operation */
...@@ -641,7 +641,7 @@ EXPORT_SYMBOL(l2_sram_zalloc); ...@@ -641,7 +641,7 @@ EXPORT_SYMBOL(l2_sram_zalloc);
int l2_sram_free(const void *addr) int l2_sram_free(const void *addr)
{ {
#if L2_LENGTH != 0 #if L2_LENGTH != 0
unsigned flags; unsigned long flags;
int ret; int ret;
/* add mutex operation */ /* add mutex operation */
......
drivers/input/keyboard/bf54x-keys.c
View file @ 604a2785
...@@ -43,7 +43,7 @@ ...@@ -43,7 +43,7 @@
#include <linux/input.h> #include <linux/input.h>
#include <asm/portmux.h> #include <asm/portmux.h>
#include <asm/mach/bf54x_keys.h> #include <mach/bf54x_keys.h>
#define DRV_NAME "bf54x-keys" #define DRV_NAME "bf54x-keys"
#define TIME_SCALE 100 /* 100 ns */ #define TIME_SCALE 100 /* 100 ns */
......
drivers/serial/bfin_5xx.c
View file @ 604a2785
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#endif #endif
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/mach/bfin_serial_5xx.h> #include <mach/bfin_serial_5xx.h>
#ifdef CONFIG_SERIAL_BFIN_DMA #ifdef CONFIG_SERIAL_BFIN_DMA
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
......
drivers/video/bf54x-lq043fb.c
View file @ 604a2785
...@@ -58,7 +58,7 @@ ...@@ -58,7 +58,7 @@
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/portmux.h> #include <asm/portmux.h>
#include <asm/mach/bf54x-lq043.h> #include <mach/bf54x-lq043.h>
#define NO_BL_SUPPORT #define NO_BL_SUPPORT
......
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