Commit 63d0f3ea authored by Swathi Dhanavanthri's avatar Swathi Dhanavanthri Committed by Matt Roper

drm/i915/tgl: Make Wa_14010229206 permanent

This workaround now applies to all steppings, not just A0.
Wa_1409085225 is a temporary A0-only W/A however it is
identical to Wa_14010229206 and hence the combined workaround
is made permanent.
Bspec: 52890
Signed-off-by: default avatarSwathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Tested-by: default avatarRafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
[mattrope: added missing blank line]
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200326234955.16155-1-swathi.dhanavanthri@intel.com
parent 98d51316
...@@ -1380,12 +1380,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) ...@@ -1380,12 +1380,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_FF_THREAD_MODE, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE); GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
/*
* Wa_1409085225:tgl
* Wa_14010229206:tgl
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
/* Wa_1408615072:tgl */ /* Wa_1408615072:tgl */
wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
VSUNIT_CLKGATE_DIS_TGL); VSUNIT_CLKGATE_DIS_TGL);
...@@ -1403,6 +1397,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) ...@@ -1403,6 +1397,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_masked_en(wal, wa_masked_en(wal,
GEN9_CS_DEBUG_MODE1, GEN9_CS_DEBUG_MODE1,
FF_DOP_CLOCK_GATE_DISABLE); FF_DOP_CLOCK_GATE_DISABLE);
/*
* Wa_1409085225:tgl
* Wa_14010229206:tgl
*/
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
} }
if (IS_GEN(i915, 11)) { if (IS_GEN(i915, 11)) {
......
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