Commit 65ebf53f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski

ARM: dts: exynos: Add cooling levels for Exynos5420 CPUs

On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and
12 steps for big core (700-1800 MHz). Add respective cooling cells.
Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 1462b137
...@@ -33,6 +33,9 @@ cpu0: cpu@0 { ...@@ -33,6 +33,9 @@ cpu0: cpu@0 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
...@@ -42,6 +45,9 @@ cpu1: cpu@1 { ...@@ -42,6 +45,9 @@ cpu1: cpu@1 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu2: cpu@2 { cpu2: cpu@2 {
...@@ -51,6 +57,9 @@ cpu2: cpu@2 { ...@@ -51,6 +57,9 @@ cpu2: cpu@2 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu3: cpu@3 { cpu3: cpu@3 {
...@@ -60,6 +69,9 @@ cpu3: cpu@3 { ...@@ -60,6 +69,9 @@ cpu3: cpu@3 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu4: cpu@100 { cpu4: cpu@100 {
...@@ -70,6 +82,9 @@ cpu4: cpu@100 { ...@@ -70,6 +82,9 @@ cpu4: cpu@100 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu5: cpu@101 { cpu5: cpu@101 {
...@@ -79,6 +94,9 @@ cpu5: cpu@101 { ...@@ -79,6 +94,9 @@ cpu5: cpu@101 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu6: cpu@102 { cpu6: cpu@102 {
...@@ -88,6 +106,9 @@ cpu6: cpu@102 { ...@@ -88,6 +106,9 @@ cpu6: cpu@102 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu7: cpu@103 { cpu7: cpu@103 {
...@@ -97,6 +118,9 @@ cpu7: cpu@103 { ...@@ -97,6 +118,9 @@ cpu7: cpu@103 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <7>;
#cooling-cells = <2>; /* min followed by max */
}; };
}; };
}; };
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