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Commit 665ae581 authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'linux-4.1' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next 

- gk20a iommu support
- gm107 graphics support without needing proprietary ucode
- various random fixes
- more gm20x bring-up, fifo/ce are ok, gr is mostly complete with the
exception of ctxsw ucode.. nvidia aren't playing nice yet so there's
not much more that can be done at this point...

I spent a lot of time trying to find a viable way of doing gr ctxsw
without signed firmware, but the "security" restrictions on the
fecs/gpccs falcons are excessive and go beyond what'd be necessary to
protect the host from malicious firmware.  This newer nvidia hw is
VERY open-source unfriendly.

I have some experimental host-based ctxsw work that could be a viable
(albeit unsatisfactory and slow) workaround in the meantime, but it
needs some more work and i'd like to get the 3d driver working
properly before i commit to pushing it.

* 'linux-4.1' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (40 commits)
  drm/nouveau/bios: fix fetching from acpi on certain systems
  drm/nouveau/gr/gm206: initial init+ctx code
  drm/nouveau/ce/gm206: enable support via gm204 code
  drm/nouveau/fifo/gm206: enable support via gm204 code
  drm/nouveau/gr/gm204: initial init+ctx code
  drm/nouveau: support for buffer moves via MaxwellDmaCopyA
  drm/nouveau/ce/gm204: initial support
  drm/nouveau: add support for gm20x fifo channels
  drm/nouveau/fifo/gm204: initial support
  drm/nouveau/gr/gk104-: prevent reading non-existent regs in intr handler
  drm/nouveau/gr/gm107: very slightly demagic part of attrib cb setup
  drm/nouveau/gr/gk104-: correct crop/zrop num_active_fbps setting
  drm/nouveau/gr/gf100-: add symbolic names for classes
  drm/nouveau/gr/gm107: support tpc "strand" ctxsw in gpccs ucode
  drm/nouveau/gr/gf100-: support mmio access with gpc offset from gpccs ucode
  drm/nouveau/gr: fix engine name, cosmetic search+replace mistake
  drm/nouveau/pmu/gk20a: add some missing statics
  drm/nouveau/platform: fix probe error path
  drm/nouveau/platform: release IOMMU's mm upon exit
  drm/nouveau/gr/gk104-gk20a: call pmu to disable any power-gating before ctor()
  ...
parents 1d2add28 4195f406
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Showing with 3957 additions and 1314 deletions
drivers/gpu/drm/nouveau/include/nvif/class.h
View file @ 665ae581
...@@ -12,6 +12,13 @@ ...@@ -12,6 +12,13 @@
#define NV_DMA_TO_MEMORY 0x00000003 #define NV_DMA_TO_MEMORY 0x00000003
#define NV_DMA_IN_MEMORY 0x0000003d #define NV_DMA_IN_MEMORY 0x0000003d
#define FERMI_TWOD_A 0x0000902d
#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x0000903d
#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
#define NV04_DISP 0x00000046 #define NV04_DISP 0x00000046
#define NV03_CHANNEL_DMA 0x0000006b #define NV03_CHANNEL_DMA 0x0000006b
...@@ -25,6 +32,7 @@ ...@@ -25,6 +32,7 @@
#define G82_CHANNEL_GPFIFO 0x0000826f #define G82_CHANNEL_GPFIFO 0x0000826f
#define FERMI_CHANNEL_GPFIFO 0x0000906f #define FERMI_CHANNEL_GPFIFO 0x0000906f
#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
#define NV50_DISP 0x00005070 #define NV50_DISP 0x00005070
#define G82_DISP 0x00008270 #define G82_DISP 0x00008270
...@@ -84,6 +92,7 @@ ...@@ -84,6 +92,7 @@
#define KEPLER_C 0x0000a297 #define KEPLER_C 0x0000a297
#define MAXWELL_A 0x0000b097 #define MAXWELL_A 0x0000b097
#define MAXWELL_B 0x0000b197
#define FERMI_COMPUTE_A 0x000090c0 #define FERMI_COMPUTE_A 0x000090c0
#define FERMI_COMPUTE_B 0x000091c0 #define FERMI_COMPUTE_B 0x000091c0
...@@ -92,6 +101,7 @@ ...@@ -92,6 +101,7 @@
#define KEPLER_COMPUTE_B 0x0000a1c0 #define KEPLER_COMPUTE_B 0x0000a1c0
#define MAXWELL_COMPUTE_A 0x0000b0c0 #define MAXWELL_COMPUTE_A 0x0000b0c0
#define MAXWELL_COMPUTE_B 0x0000b1c0
/******************************************************************************* /*******************************************************************************
......
drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
View file @ 665ae581
...@@ -10,4 +10,7 @@ extern struct nvkm_oclass gf100_ce1_oclass; ...@@ -10,4 +10,7 @@ extern struct nvkm_oclass gf100_ce1_oclass;
extern struct nvkm_oclass gk104_ce0_oclass; extern struct nvkm_oclass gk104_ce0_oclass;
extern struct nvkm_oclass gk104_ce1_oclass; extern struct nvkm_oclass gk104_ce1_oclass;
extern struct nvkm_oclass gk104_ce2_oclass; extern struct nvkm_oclass gk104_ce2_oclass;
extern struct nvkm_oclass gm204_ce0_oclass;
extern struct nvkm_oclass gm204_ce1_oclass;
extern struct nvkm_oclass gm204_ce2_oclass;
#endif #endif
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View file @ 665ae581
...@@ -116,6 +116,7 @@ extern struct nvkm_oclass *gf100_fifo_oclass; ...@@ -116,6 +116,7 @@ extern struct nvkm_oclass *gf100_fifo_oclass;
extern struct nvkm_oclass *gk104_fifo_oclass; extern struct nvkm_oclass *gk104_fifo_oclass;
extern struct nvkm_oclass *gk20a_fifo_oclass; extern struct nvkm_oclass *gk20a_fifo_oclass;
extern struct nvkm_oclass *gk208_fifo_oclass; extern struct nvkm_oclass *gk208_fifo_oclass;
extern struct nvkm_oclass *gm204_fifo_oclass;
int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32, int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *); struct nvkm_notify *);
......
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
View file @ 665ae581
...@@ -38,7 +38,7 @@ nvkm_gr(void *obj) ...@@ -38,7 +38,7 @@ nvkm_gr(void *obj)
} }
#define nvkm_gr_create(p,e,c,y,d) \ #define nvkm_gr_create(p,e,c,y,d) \
nvkm_engine_create((p), (e), (c), (y), "PGR", "graphics", (d)) nvkm_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d))
#define nvkm_gr_destroy(d) \ #define nvkm_gr_destroy(d) \
nvkm_engine_destroy(&(d)->base) nvkm_engine_destroy(&(d)->base)
#define nvkm_gr_init(d) \ #define nvkm_gr_init(d) \
...@@ -72,6 +72,8 @@ extern struct nvkm_oclass *gk110_gr_oclass; ...@@ -72,6 +72,8 @@ extern struct nvkm_oclass *gk110_gr_oclass;
extern struct nvkm_oclass *gk110b_gr_oclass; extern struct nvkm_oclass *gk110b_gr_oclass;
extern struct nvkm_oclass *gk208_gr_oclass; extern struct nvkm_oclass *gk208_gr_oclass;
extern struct nvkm_oclass *gm107_gr_oclass; extern struct nvkm_oclass *gm107_gr_oclass;
extern struct nvkm_oclass *gm204_gr_oclass;
extern struct nvkm_oclass *gm206_gr_oclass;
#include <core/enum.h> #include <core/enum.h>
......
drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
View file @ 665ae581
...@@ -45,4 +45,5 @@ nvkm_instmem(void *obj) ...@@ -45,4 +45,5 @@ nvkm_instmem(void *obj)
extern struct nvkm_oclass *nv04_instmem_oclass; extern struct nvkm_oclass *nv04_instmem_oclass;
extern struct nvkm_oclass *nv40_instmem_oclass; extern struct nvkm_oclass *nv40_instmem_oclass;
extern struct nvkm_oclass *nv50_instmem_oclass; extern struct nvkm_oclass *nv50_instmem_oclass;
extern struct nvkm_oclass *gk20a_instmem_oclass;
#endif #endif
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
View file @ 665ae581
...@@ -35,6 +35,7 @@ extern struct nvkm_oclass *gt215_pmu_oclass; ...@@ -35,6 +35,7 @@ extern struct nvkm_oclass *gt215_pmu_oclass;
extern struct nvkm_oclass *gf100_pmu_oclass; extern struct nvkm_oclass *gf100_pmu_oclass;
extern struct nvkm_oclass *gf110_pmu_oclass; extern struct nvkm_oclass *gf110_pmu_oclass;
extern struct nvkm_oclass *gk104_pmu_oclass; extern struct nvkm_oclass *gk104_pmu_oclass;
extern struct nvkm_oclass *gk110_pmu_oclass;
extern struct nvkm_oclass *gk208_pmu_oclass; extern struct nvkm_oclass *gk208_pmu_oclass;
extern struct nvkm_oclass *gk20a_pmu_oclass; extern struct nvkm_oclass *gk20a_pmu_oclass;
......
drivers/gpu/drm/nouveau/nouveau_bo.c
View file @ 665ae581
...@@ -1110,6 +1110,8 @@ nouveau_bo_move_init(struct nouveau_drm *drm) ...@@ -1110,6 +1110,8 @@ nouveau_bo_move_init(struct nouveau_drm *drm)
struct ttm_mem_reg *, struct ttm_mem_reg *); struct ttm_mem_reg *, struct ttm_mem_reg *);
int (*init)(struct nouveau_channel *, u32 handle); int (*init)(struct nouveau_channel *, u32 handle);
} _methods[] = { } _methods[] = {
{ "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
{ "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
{ "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
{ "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
{ "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
......
drivers/gpu/drm/nouveau/nouveau_chan.c
View file @ 665ae581
...@@ -184,7 +184,8 @@ static int ...@@ -184,7 +184,8 @@ static int
nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
u32 handle, u32 engine, struct nouveau_channel **pchan) u32 handle, u32 engine, struct nouveau_channel **pchan)
{ {
static const u16 oclasses[] = { KEPLER_CHANNEL_GPFIFO_A, static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A,
KEPLER_CHANNEL_GPFIFO_A,
FERMI_CHANNEL_GPFIFO, FERMI_CHANNEL_GPFIFO,
G82_CHANNEL_GPFIFO, G82_CHANNEL_GPFIFO,
NV50_CHANNEL_GPFIFO, NV50_CHANNEL_GPFIFO,
......
drivers/gpu/drm/nouveau/nouveau_display.c
View file @ 665ae581
...@@ -869,13 +869,20 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, ...@@ -869,13 +869,20 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
struct drm_mode_create_dumb *args) struct drm_mode_create_dumb *args)
{ {
struct nouveau_bo *bo; struct nouveau_bo *bo;
uint32_t domain;
int ret; int ret;
args->pitch = roundup(args->width * (args->bpp / 8), 256); args->pitch = roundup(args->width * (args->bpp / 8), 256);
args->size = args->pitch * args->height; args->size = args->pitch * args->height;
args->size = roundup(args->size, PAGE_SIZE); args->size = roundup(args->size, PAGE_SIZE);
ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo); /* Use VRAM if there is any ; otherwise fallback to system memory */
if (nouveau_drm(dev)->device.info.ram_size != 0)
domain = NOUVEAU_GEM_DOMAIN_VRAM;
else
domain = NOUVEAU_GEM_DOMAIN_GART;
ret = nouveau_gem_new(dev, args->size, 0, domain, 0, 0, &bo);
if (ret) if (ret)
return ret; return ret;
......
drivers/gpu/drm/nouveau/nouveau_drm.c
View file @ 665ae581
...@@ -181,6 +181,7 @@ nouveau_accel_init(struct nouveau_drm *drm) ...@@ -181,6 +181,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
break; break;
case FERMI_CHANNEL_GPFIFO: case FERMI_CHANNEL_GPFIFO:
case KEPLER_CHANNEL_GPFIFO_A: case KEPLER_CHANNEL_GPFIFO_A:
case MAXWELL_CHANNEL_GPFIFO_A:
ret = nvc0_fence_create(drm); ret = nvc0_fence_create(drm);
break; break;
default: default:
......
drivers/gpu/drm/nouveau/nouveau_drm.h
View file @ 665ae581
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 2 #define DRIVER_MINOR 2
#define DRIVER_PATCHLEVEL 1 #define DRIVER_PATCHLEVEL 2
/* /*
* 1.1.1: * 1.1.1:
...@@ -28,6 +28,8 @@ ...@@ -28,6 +28,8 @@
* - fermi,kepler,maxwell zbc * - fermi,kepler,maxwell zbc
* 1.2.1: * 1.2.1:
* - allow concurrent access to bo's mapped read/write. * - allow concurrent access to bo's mapped read/write.
* 1.2.2:
* - add NOUVEAU_GEM_DOMAIN_COHERENT flag
*/ */
#include <nvif/client.h> #include <nvif/client.h>
......
drivers/gpu/drm/nouveau/nouveau_gem.c
View file @ 665ae581
...@@ -189,6 +189,9 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, ...@@ -189,6 +189,9 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain,
if (!flags || domain & NOUVEAU_GEM_DOMAIN_CPU) if (!flags || domain & NOUVEAU_GEM_DOMAIN_CPU)
flags |= TTM_PL_FLAG_SYSTEM; flags |= TTM_PL_FLAG_SYSTEM;
if (domain & NOUVEAU_GEM_DOMAIN_COHERENT)
flags |= TTM_PL_FLAG_UNCACHED;
ret = nouveau_bo_new(dev, size, align, flags, tile_mode, ret = nouveau_bo_new(dev, size, align, flags, tile_mode,
tile_flags, NULL, NULL, pnvbo); tile_flags, NULL, NULL, pnvbo);
if (ret) if (ret)
......
drivers/gpu/drm/nouveau/nouveau_platform.c
View file @ 665ae581
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/reset.h> #include <linux/reset.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
#include <linux/iommu.h>
#include <soc/tegra/fuse.h> #include <soc/tegra/fuse.h>
#include <soc/tegra/pmc.h> #include <soc/tegra/pmc.h>
...@@ -91,6 +92,72 @@ static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu) ...@@ -91,6 +92,72 @@ static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu)
return 0; return 0;
} }
static void nouveau_platform_probe_iommu(struct device *dev,
struct nouveau_platform_gpu *gpu)
{
int err;
unsigned long pgsize_bitmap;
mutex_init(&gpu->iommu.mutex);
if (iommu_present(&platform_bus_type)) {
gpu->iommu.domain = iommu_domain_alloc(&platform_bus_type);
if (IS_ERR(gpu->iommu.domain))
goto error;
/*
* A IOMMU is only usable if it supports page sizes smaller
* or equal to the system's PAGE_SIZE, with a preference if
* both are equal.
*/
pgsize_bitmap = gpu->iommu.domain->ops->pgsize_bitmap;
if (pgsize_bitmap & PAGE_SIZE) {
gpu->iommu.pgshift = PAGE_SHIFT;
} else {
gpu->iommu.pgshift = fls(pgsize_bitmap & ~PAGE_MASK);
if (gpu->iommu.pgshift == 0) {
dev_warn(dev, "unsupported IOMMU page size\n");
goto free_domain;
}
gpu->iommu.pgshift -= 1;
}
err = iommu_attach_device(gpu->iommu.domain, dev);
if (err)
goto free_domain;
err = nvkm_mm_init(&gpu->iommu._mm, 0,
(1ULL << 40) >> gpu->iommu.pgshift, 1);
if (err)
goto detach_device;
gpu->iommu.mm = &gpu->iommu._mm;
}
return;
detach_device:
iommu_detach_device(gpu->iommu.domain, dev);
free_domain:
iommu_domain_free(gpu->iommu.domain);
error:
gpu->iommu.domain = NULL;
gpu->iommu.pgshift = 0;
dev_err(dev, "cannot initialize IOMMU MM\n");
}
static void nouveau_platform_remove_iommu(struct device *dev,
struct nouveau_platform_gpu *gpu)
{
if (gpu->iommu.domain) {
nvkm_mm_fini(&gpu->iommu._mm);
iommu_detach_device(gpu->iommu.domain, dev);
iommu_domain_free(gpu->iommu.domain);
}
}
static int nouveau_platform_probe(struct platform_device *pdev) static int nouveau_platform_probe(struct platform_device *pdev)
{ {
struct nouveau_platform_gpu *gpu; struct nouveau_platform_gpu *gpu;
...@@ -118,6 +185,8 @@ static int nouveau_platform_probe(struct platform_device *pdev) ...@@ -118,6 +185,8 @@ static int nouveau_platform_probe(struct platform_device *pdev)
if (IS_ERR(gpu->clk_pwr)) if (IS_ERR(gpu->clk_pwr))
return PTR_ERR(gpu->clk_pwr); return PTR_ERR(gpu->clk_pwr);
nouveau_platform_probe_iommu(&pdev->dev, gpu);
err = nouveau_platform_power_up(gpu); err = nouveau_platform_power_up(gpu);
if (err) if (err)
return err; return err;
...@@ -140,10 +209,9 @@ static int nouveau_platform_probe(struct platform_device *pdev) ...@@ -140,10 +209,9 @@ static int nouveau_platform_probe(struct platform_device *pdev)
err_unref: err_unref:
drm_dev_unref(drm); drm_dev_unref(drm);
return 0;
power_down: power_down:
nouveau_platform_power_down(gpu); nouveau_platform_power_down(gpu);
nouveau_platform_remove_iommu(&pdev->dev, gpu);
return err; return err;
} }
...@@ -154,10 +222,15 @@ static int nouveau_platform_remove(struct platform_device *pdev) ...@@ -154,10 +222,15 @@ static int nouveau_platform_remove(struct platform_device *pdev)
struct nouveau_drm *drm = nouveau_drm(drm_dev); struct nouveau_drm *drm = nouveau_drm(drm_dev);
struct nvkm_device *device = nvxx_device(&drm->device); struct nvkm_device *device = nvxx_device(&drm->device);
struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu; struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu;
int err;
nouveau_drm_device_remove(drm_dev); nouveau_drm_device_remove(drm_dev);
return nouveau_platform_power_down(gpu); err = nouveau_platform_power_down(gpu);
nouveau_platform_remove_iommu(&pdev->dev, gpu);
return err;
} }
#if IS_ENABLED(CONFIG_OF) #if IS_ENABLED(CONFIG_OF)
......
drivers/gpu/drm/nouveau/nouveau_platform.h
View file @ 665ae581
...@@ -24,10 +24,12 @@ ...@@ -24,10 +24,12 @@
#define __NOUVEAU_PLATFORM_H__ #define __NOUVEAU_PLATFORM_H__
#include "core/device.h" #include "core/device.h"
#include "core/mm.h"
struct reset_control; struct reset_control;
struct clk; struct clk;
struct regulator; struct regulator;
struct iommu_domain;
struct platform_driver; struct platform_driver;
struct nouveau_platform_gpu { struct nouveau_platform_gpu {
...@@ -36,6 +38,22 @@ struct nouveau_platform_gpu { ...@@ -36,6 +38,22 @@ struct nouveau_platform_gpu {
struct clk *clk_pwr; struct clk *clk_pwr;
struct regulator *vdd; struct regulator *vdd;
struct {
/*
* Protects accesses to mm from subsystems
*/
struct mutex mutex;
struct nvkm_mm _mm;
/*
* Just points to _mm. We need this to avoid embedding
* struct nvkm_mm in os.h
*/
struct nvkm_mm *mm;
struct iommu_domain *domain;
unsigned long pgshift;
} iommu;
}; };
struct nouveau_platform_device { struct nouveau_platform_device {
......
drivers/gpu/drm/nouveau/nouveau_ttm.c
View file @ 665ae581
...@@ -82,6 +82,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, ...@@ -82,6 +82,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
u32 size_nc = 0; u32 size_nc = 0;
int ret; int ret;
if (drm->device.info.ram_size == 0)
return -ENOMEM;
if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
size_nc = 1 << nvbo->page_shift; size_nc = 1 << nvbo->page_shift;
......
drivers/gpu/drm/nouveau/nv84_fence.c
View file @ 665ae581
...@@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) ...@@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm)
{ {
struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device);
struct nv84_fence_priv *priv; struct nv84_fence_priv *priv;
u32 domain;
int ret; int ret;
priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
...@@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) ...@@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm)
priv->base.context_base = fence_context_alloc(priv->base.contexts); priv->base.context_base = fence_context_alloc(priv->base.contexts);
priv->base.uevent = true; priv->base.uevent = true;
ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, /* Use VRAM if there is any ; otherwise fallback to system memory */
TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL, &priv->bo); domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
/*
* fences created in sysmem must be non-cached or we
* will lose CPU/GPU coherency!
*/
TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0,
0, NULL, NULL, &priv->bo);
if (ret == 0) { if (ret == 0) {
ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); ret = nouveau_bo_pin(priv->bo, domain, false);
if (ret == 0) { if (ret == 0) {
ret = nouveau_bo_map(priv->bo); ret = nouveau_bo_map(priv->bo);
if (ret) if (ret)
......
drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
View file @ 665ae581
nvkm-y += nvkm/engine/ce/gt215.o nvkm-y += nvkm/engine/ce/gt215.o
nvkm-y += nvkm/engine/ce/gf100.o nvkm-y += nvkm/engine/ce/gf100.o
nvkm-y += nvkm/engine/ce/gk104.o nvkm-y += nvkm/engine/ce/gk104.o
nvkm-y += nvkm/engine/ce/gm204.o
drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c 0 → 100644
View file @ 665ae581
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <engine/ce.h>
#include <core/engctx.h>
struct gm204_ce_priv {
struct nvkm_engine base;
};
/*******************************************************************************
* Copy object classes
******************************************************************************/
static struct nvkm_oclass
gm204_ce_sclass[] = {
{ 0xb0b5, &nvkm_object_ofuncs },
{},
};
/*******************************************************************************
* PCE context
******************************************************************************/
static struct nvkm_ofuncs
gm204_ce_context_ofuncs = {
.ctor = _nvkm_engctx_ctor,
.dtor = _nvkm_engctx_dtor,
.init = _nvkm_engctx_init,
.fini = _nvkm_engctx_fini,
.rd32 = _nvkm_engctx_rd32,
.wr32 = _nvkm_engctx_wr32,
};
static struct nvkm_oclass
gm204_ce_cclass = {
.handle = NV_ENGCTX(CE0, 0x24),
.ofuncs = &gm204_ce_context_ofuncs,
};
/*******************************************************************************
* PCE engine/subdev functions
******************************************************************************/
static void
gm204_ce_intr(struct nvkm_subdev *subdev)
{
const int ce = nv_subidx(subdev) - NVDEV_ENGINE_CE0;
struct gm204_ce_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000));
if (stat) {
nv_warn(priv, "unhandled intr 0x%08x\n", stat);
nv_wr32(priv, 0x104908 + (ce * 0x1000), stat);
}
}
static int
gm204_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct gm204_ce_priv *priv;
int ret;
ret = nvkm_engine_create(parent, engine, oclass, true,
"PCE0", "ce0", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000040;
nv_subdev(priv)->intr = gm204_ce_intr;
nv_engine(priv)->cclass = &gm204_ce_cclass;
nv_engine(priv)->sclass = gm204_ce_sclass;
return 0;
}
static int
gm204_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct gm204_ce_priv *priv;
int ret;
ret = nvkm_engine_create(parent, engine, oclass, true,
"PCE1", "ce1", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000080;
nv_subdev(priv)->intr = gm204_ce_intr;
nv_engine(priv)->cclass = &gm204_ce_cclass;
nv_engine(priv)->sclass = gm204_ce_sclass;
return 0;
}
static int
gm204_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct gm204_ce_priv *priv;
int ret;
ret = nvkm_engine_create(parent, engine, oclass, true,
"PCE2", "ce2", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00200000;
nv_subdev(priv)->intr = gm204_ce_intr;
nv_engine(priv)->cclass = &gm204_ce_cclass;
nv_engine(priv)->sclass = gm204_ce_sclass;
return 0;
}
struct nvkm_oclass
gm204_ce0_oclass = {
.handle = NV_ENGINE(CE0, 0x24),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_ce0_ctor,
.dtor = _nvkm_engine_dtor,
.init = _nvkm_engine_init,
.fini = _nvkm_engine_fini,
},
};
struct nvkm_oclass
gm204_ce1_oclass = {
.handle = NV_ENGINE(CE1, 0x24),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_ce1_ctor,
.dtor = _nvkm_engine_dtor,
.init = _nvkm_engine_init,
.fini = _nvkm_engine_fini,
},
};
struct nvkm_oclass
gm204_ce2_oclass = {
.handle = NV_ENGINE(CE2, 0x24),
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_ce2_ctor,
.dtor = _nvkm_engine_dtor,
.init = _nvkm_engine_init,
.fini = _nvkm_engine_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @ 665ae581
...@@ -139,9 +139,13 @@ nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) ...@@ -139,9 +139,13 @@ nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size)
args->v0.chipset = device->chipset; args->v0.chipset = device->chipset;
args->v0.revision = device->chiprev; args->v0.revision = device->chiprev;
if (pfb) args->v0.ram_size = args->v0.ram_user = pfb->ram->size; if (pfb && pfb->ram)
else args->v0.ram_size = args->v0.ram_user = 0; args->v0.ram_size = args->v0.ram_user = pfb->ram->size;
if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved; else
args->v0.ram_size = args->v0.ram_user = 0;
if (imem && args->v0.ram_size > 0)
args->v0.ram_user = args->v0.ram_user - imem->reserved;
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View file @ 665ae581
...@@ -171,7 +171,7 @@ gk104_identify(struct nvkm_device *device) ...@@ -171,7 +171,7 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
...@@ -202,7 +202,7 @@ gk104_identify(struct nvkm_device *device) ...@@ -202,7 +202,7 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
...@@ -236,7 +236,7 @@ gk104_identify(struct nvkm_device *device) ...@@ -236,7 +236,7 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View file @ 665ae581
...@@ -127,16 +127,14 @@ gm100_identify(struct nvkm_device *device) ...@@ -127,16 +127,14 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif #endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
#if 0 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0
device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
...@@ -170,16 +168,14 @@ gm100_identify(struct nvkm_device *device) ...@@ -170,16 +168,14 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif #endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
#if 0 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0
device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
#if 0
device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
View file @ 665ae581
...@@ -413,8 +413,8 @@ gf110_disp_base_mthd_base = { ...@@ -413,8 +413,8 @@ gf110_disp_base_mthd_base = {
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
gf110_disp_base_mthd_image = { gf110_disp_base_mthd_image = {
.mthd = 0x0400, .mthd = 0x0020,
.addr = 0x000400, .addr = 0x000020,
.data = { .data = {
{ 0x0400, 0x661400 }, { 0x0400, 0x661400 },
{ 0x0404, 0x661404 }, { 0x0404, 0x661404 },
......
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View file @ 665ae581
...@@ -229,7 +229,7 @@ nv50_disp_dmac_create_(struct nvkm_object *parent, ...@@ -229,7 +229,7 @@ nv50_disp_dmac_create_(struct nvkm_object *parent,
switch (dmac->pushdma->target) { switch (dmac->pushdma->target) {
case NV_MEM_TARGET_VRAM: case NV_MEM_TARGET_VRAM:
dmac->push = 0x00000000 | dmac->pushdma->start >> 8; dmac->push = 0x00000001 | dmac->pushdma->start >> 8;
break; break;
case NV_MEM_TARGET_PCI_NOSNOOP: case NV_MEM_TARGET_PCI_NOSNOOP:
dmac->push = 0x00000003 | dmac->pushdma->start >> 8; dmac->push = 0x00000003 | dmac->pushdma->start >> 8;
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
View file @ 665ae581
...@@ -9,3 +9,4 @@ nvkm-y += nvkm/engine/fifo/gf100.o ...@@ -9,3 +9,4 @@ nvkm-y += nvkm/engine/fifo/gf100.o
nvkm-y += nvkm/engine/fifo/gk104.o nvkm-y += nvkm/engine/fifo/gk104.o
nvkm-y += nvkm/engine/fifo/gk20a.o nvkm-y += nvkm/engine/fifo/gk20a.o
nvkm-y += nvkm/engine/fifo/gk208.o nvkm-y += nvkm/engine/fifo/gk208.o
nvkm-y += nvkm/engine/fifo/gm204.o
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View file @ 665ae581
...@@ -323,8 +323,8 @@ gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) ...@@ -323,8 +323,8 @@ gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend)
return nvkm_fifo_channel_fini(&chan->base, suspend); return nvkm_fifo_channel_fini(&chan->base, suspend);
} }
static struct nvkm_ofuncs struct nvkm_ofuncs
gk104_fifo_ofuncs = { gk104_fifo_chan_ofuncs = {
.ctor = gk104_fifo_chan_ctor, .ctor = gk104_fifo_chan_ctor,
.dtor = _nvkm_fifo_channel_dtor, .dtor = _nvkm_fifo_channel_dtor,
.init = gk104_fifo_chan_init, .init = gk104_fifo_chan_init,
...@@ -337,7 +337,7 @@ gk104_fifo_ofuncs = { ...@@ -337,7 +337,7 @@ gk104_fifo_ofuncs = {
static struct nvkm_oclass static struct nvkm_oclass
gk104_fifo_sclass[] = { gk104_fifo_sclass[] = {
{ KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_ofuncs }, { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs },
{} {}
}; };
...@@ -774,6 +774,7 @@ gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) ...@@ -774,6 +774,7 @@ gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit)
while (object) { while (object) {
switch (nv_mclass(object)) { switch (nv_mclass(object)) {
case KEPLER_CHANNEL_GPFIFO_A: case KEPLER_CHANNEL_GPFIFO_A:
case MAXWELL_CHANNEL_GPFIFO_A:
gk104_fifo_recover(priv, engine, (void *)object); gk104_fifo_recover(priv, engine, (void *)object);
break; break;
} }
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
View file @ 665ae581
...@@ -13,4 +13,6 @@ struct gk104_fifo_impl { ...@@ -13,4 +13,6 @@ struct gk104_fifo_impl {
struct nvkm_oclass base; struct nvkm_oclass base;
u32 channels; u32 channels;
}; };
extern struct nvkm_ofuncs gk104_fifo_chan_ofuncs;
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c 0 → 100644
View file @ 665ae581
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "gk104.h"
#include <nvif/class.h>
static struct nvkm_oclass
gm204_fifo_sclass[] = {
{ MAXWELL_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs },
{}
};
static int
gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject);
if (ret == 0) {
struct gk104_fifo_priv *priv = (void *)*pobject;
nv_engine(priv)->sclass = gm204_fifo_sclass;
}
return ret;
}
struct nvkm_oclass *
gm204_fifo_oclass = &(struct gk104_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0x24),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gm204_fifo_ctor,
.dtor = gk104_fifo_dtor,
.init = gk104_fifo_init,
.fini = _nvkm_fifo_fini,
},
.channels = 4096,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
View file @ 665ae581
...@@ -12,6 +12,8 @@ nvkm-y += nvkm/engine/gr/ctxgk110.o ...@@ -12,6 +12,8 @@ nvkm-y += nvkm/engine/gr/ctxgk110.o
nvkm-y += nvkm/engine/gr/ctxgk110b.o nvkm-y += nvkm/engine/gr/ctxgk110b.o
nvkm-y += nvkm/engine/gr/ctxgk208.o nvkm-y += nvkm/engine/gr/ctxgk208.o
nvkm-y += nvkm/engine/gr/ctxgm107.o nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/ctxgm204.o
nvkm-y += nvkm/engine/gr/ctxgm206.o
nvkm-y += nvkm/engine/gr/nv04.o nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o nvkm-y += nvkm/engine/gr/nv10.o
nvkm-y += nvkm/engine/gr/nv20.o nvkm-y += nvkm/engine/gr/nv20.o
...@@ -34,3 +36,5 @@ nvkm-y += nvkm/engine/gr/gk110.o ...@@ -34,3 +36,5 @@ nvkm-y += nvkm/engine/gr/gk110.o
nvkm-y += nvkm/engine/gr/gk110b.o nvkm-y += nvkm/engine/gr/gk110b.o
nvkm-y += nvkm/engine/gr/gk208.o nvkm-y += nvkm/engine/gr/gk208.o
nvkm-y += nvkm/engine/gr/gm107.o nvkm-y += nvkm/engine/gr/gm107.o
nvkm-y += nvkm/engine/gr/gm204.o
nvkm-y += nvkm/engine/gr/gm206.o
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View file @ 665ae581
...@@ -88,11 +88,22 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *); ...@@ -88,11 +88,22 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *);
void gk104_grctx_generate_pagepool(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *);
void gk104_grctx_generate_unkn(struct gf100_gr_priv *); void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *); void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *);
extern struct nvkm_oclass *gk110_grctx_oclass; extern struct nvkm_oclass *gk110_grctx_oclass;
extern struct nvkm_oclass *gk110b_grctx_oclass; extern struct nvkm_oclass *gk110b_grctx_oclass;
extern struct nvkm_oclass *gk208_grctx_oclass; extern struct nvkm_oclass *gk208_grctx_oclass;
extern struct nvkm_oclass *gm107_grctx_oclass; extern struct nvkm_oclass *gm107_grctx_oclass;
void gm107_grctx_generate_bundle(struct gf100_grctx *);
void gm107_grctx_generate_pagepool(struct gf100_grctx *);
void gm107_grctx_generate_attrib(struct gf100_grctx *);
extern struct nvkm_oclass *gm204_grctx_oclass;
void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
extern struct nvkm_oclass *gm206_grctx_oclass;
/* context init value lists */ /* context init value lists */
...@@ -196,4 +207,22 @@ extern const struct gf100_gr_init gk208_grctx_init_rstr2d_0[]; ...@@ -196,4 +207,22 @@ extern const struct gf100_gr_init gk208_grctx_init_rstr2d_0[];
extern const struct gf100_gr_init gk208_grctx_init_prop_0[]; extern const struct gf100_gr_init gk208_grctx_init_prop_0[];
extern const struct gf100_gr_init gk208_grctx_init_crstr_0[]; extern const struct gf100_gr_init gk208_grctx_init_crstr_0[];
extern const struct gf100_gr_init gm107_grctx_init_gpc_unk_0[];
extern const struct gf100_gr_init gm107_grctx_init_wwdx_0[];
extern const struct gf100_gr_pack gm204_grctx_pack_icmd[];
extern const struct gf100_gr_pack gm204_grctx_pack_mthd[];
extern const struct gf100_gr_pack gm204_grctx_pack_hub[];
extern const struct gf100_gr_init gm204_grctx_init_prop_0[];
extern const struct gf100_gr_init gm204_grctx_init_setup_0[];
extern const struct gf100_gr_init gm204_grctx_init_gpm_0[];
extern const struct gf100_gr_init gm204_grctx_init_gpc_unk_2[];
extern const struct gf100_gr_pack gm204_grctx_pack_tpc[];
extern const struct gf100_gr_pack gm204_grctx_pack_ppc[];
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
View file @ 665ae581
...@@ -940,6 +940,14 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv) ...@@ -940,6 +940,14 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
nv_wr32(priv, 0x40780c + (i * 4), data[i]); nv_wr32(priv, 0x40780c + (i * 4), data[i]);
} }
void
gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv)
{
const u32 fbp_count = nv_rd32(priv, 0x120074);
nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */
nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */
}
void void
gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{ {
...@@ -970,13 +978,7 @@ gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) ...@@ -970,13 +978,7 @@ gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
if (priv->gpc_nr == 1) { gk104_grctx_generate_rop_active_fbps(priv);
nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
} else {
nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
gf100_gr_icmd(priv, oclass->icmd); gf100_gr_icmd(priv, oclass->icmd);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
View file @ 665ae581
...@@ -699,7 +699,7 @@ gm107_grctx_pack_hub[] = { ...@@ -699,7 +699,7 @@ gm107_grctx_pack_hub[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_grctx_init_gpc_unk_0[] = { gm107_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000056 }, { 0x418380, 1, 0x04, 0x00000056 },
{} {}
...@@ -834,7 +834,7 @@ gm107_grctx_init_cbm_0[] = { ...@@ -834,7 +834,7 @@ gm107_grctx_init_cbm_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_grctx_init_wwdx_0[] = { gm107_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 }, { 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 }, { 0x41bf04, 1, 0x04, 0x062080e6 },
...@@ -860,7 +860,7 @@ gm107_grctx_pack_ppc[] = { ...@@ -860,7 +860,7 @@ gm107_grctx_pack_ppc[] = {
* PGRAPH context implementation * PGRAPH context implementation
******************************************************************************/ ******************************************************************************/
static void void
gm107_grctx_generate_bundle(struct gf100_grctx *info) gm107_grctx_generate_bundle(struct gf100_grctx *info)
{ {
const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
...@@ -877,7 +877,7 @@ gm107_grctx_generate_bundle(struct gf100_grctx *info) ...@@ -877,7 +877,7 @@ gm107_grctx_generate_bundle(struct gf100_grctx *info)
mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);
} }
static void void
gm107_grctx_generate_pagepool(struct gf100_grctx *info) gm107_grctx_generate_pagepool(struct gf100_grctx *info)
{ {
const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
...@@ -892,7 +892,7 @@ gm107_grctx_generate_pagepool(struct gf100_grctx *info) ...@@ -892,7 +892,7 @@ gm107_grctx_generate_pagepool(struct gf100_grctx *info)
mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */ mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */
} }
static void void
gm107_grctx_generate_attrib(struct gf100_grctx *info) gm107_grctx_generate_attrib(struct gf100_grctx *info)
{ {
struct gf100_gr_priv *priv = info->priv; struct gf100_gr_priv *priv = info->priv;
...@@ -926,7 +926,7 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info) ...@@ -926,7 +926,7 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info)
mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xe4, as);
mmio_wr32(info, o + 0xf8, ao); mmio_wr32(info, o + 0xf8, ao);
ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc];
mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs); mmio_wr32(info, u, ((bs / 3 /*XXX*/) << 16) | bs);
} }
} }
} }
...@@ -982,13 +982,7 @@ gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) ...@@ -982,13 +982,7 @@ gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
if (priv->gpc_nr == 1) { gk104_grctx_generate_rop_active_fbps(priv);
nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
} else {
nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
gf100_gr_icmd(priv, oclass->icmd); gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400); nv_wr32(priv, 0x404154, 0x00000400);
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c 0 → 100644
View file @ 665ae581
This diff is collapsed.
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c 0 → 100644
View file @ 665ae581
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "ctxgf100.h"
static const struct gf100_gr_init
gm206_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
{ 0x418704, 1, 0x04, 0x00000080 },
{ 0x418708, 1, 0x04, 0x40000000 },
{ 0x41870c, 2, 0x04, 0x00000000 },
{ 0x418728, 1, 0x04, 0x00300020 },
{}
};
static const struct gf100_gr_pack
gm206_grctx_pack_gpc[] = {
{ gm107_grctx_init_gpc_unk_0 },
{ gm204_grctx_init_prop_0 },
{ gm206_grctx_init_gpc_unk_1 },
{ gm204_grctx_init_setup_0 },
{ gf100_grctx_init_zcull_0 },
{ gk208_grctx_init_crstr_0 },
{ gm204_grctx_init_gpm_0 },
{ gm204_grctx_init_gpc_unk_2 },
{ gf100_grctx_init_gcc_0 },
{}
};
struct nvkm_oclass *
gm206_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x26),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_context_ctor,
.dtor = gf100_gr_context_dtor,
.init = _nvkm_gr_context_init,
.fini = _nvkm_gr_context_fini,
.rd32 = _nvkm_gr_context_rd32,
.wr32 = _nvkm_gr_context_wr32,
},
.main = gm204_grctx_generate_main,
.unkn = gk104_grctx_generate_unkn,
.hub = gm204_grctx_pack_hub,
.gpc = gm206_grctx_pack_gpc,
.zcull = gf100_grctx_pack_zcull,
.tpc = gm204_grctx_pack_tpc,
.ppc = gm204_grctx_pack_ppc,
.icmd = gm204_grctx_pack_icmd,
.mthd = gm204_grctx_pack_mthd,
.bundle = gm107_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x780,
.pagepool = gm107_grctx_generate_pagepool,
.pagepool_size = 0x20000,
.attrib = gm107_grctx_generate_attrib,
.attrib_nr_max = 0x600,
.attrib_nr = 0x400,
.alpha_nr_max = 0x1800,
.alpha_nr = 0x1000,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
View file @ 665ae581
...@@ -52,6 +52,12 @@ mmio_list_base: ...@@ -52,6 +52,12 @@ mmio_list_base:
#endif #endif
#ifdef INCLUDE_CODE #ifdef INCLUDE_CODE
#define gpc_wr32(addr,reg) /*
*/ mov b32 $r15 reg /*
*/ imm32($r14, addr) /*
*/ or $r14 NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE /*
*/ call(nv_wr32)
// reports an exception to the host // reports an exception to the host
// //
// In: $r15 error code (see os.h) // In: $r15 error code (see os.h)
...@@ -64,6 +70,43 @@ error: ...@@ -64,6 +70,43 @@ error:
pop $r14 pop $r14
ret ret
#if CHIPSET >= GM107
tpc_strand_wait:
push $r9
trace_set(T_STRTPC)
tpc_strand_busy:
nv_iord($r9, NV_PGRAPH_GPCX_GPCCS_TPC_STATUS, 0)
bra b32 $r9 0x0 ne #tpc_strand_busy
trace_clr(T_STRTPC)
pop $r9
ret
#define tpc_strand_wait() call(tpc_strand_wait)
#define tpc_strand_enable() /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ tpc_strand_wait()
#define tpc_strand_disable() /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ tpc_strand_wait()
#define tpc_strand_seek(p) /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15) /*
*/ mov $r15 p /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_SELECT, $r15) /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK /*
*/ tpc_strand_wait()
#define tpc_strand_info(m) /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ mov $r15 m /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_DATA, $r15) /*
*/ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO /*
*/ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*
*/ tpc_strand_wait()
#endif
// GPC fuc initialisation, executed by triggering ucode start, will // GPC fuc initialisation, executed by triggering ucode start, will
// fall through to main loop after completion. // fall through to main loop after completion.
// //
...@@ -101,7 +144,7 @@ init: ...@@ -101,7 +144,7 @@ init:
// enable interrupts // enable interrupts
bset $flags ie0 bset $flags ie0
// figure out which GPC we are, and how many TPCs we have // how many TPCs do we have?
nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0) nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
mov $r3 1 mov $r3 1
and $r2 0x1f and $r2 0x1f
...@@ -109,8 +152,12 @@ init: ...@@ -109,8 +152,12 @@ init:
sub b32 $r3 1 sub b32 $r3 1
st b32 D[$r0 + #tpc_count] $r2 st b32 D[$r0 + #tpc_count] $r2
st b32 D[$r0 + #tpc_mask] $r3 st b32 D[$r0 + #tpc_mask] $r3
// determine which GPC we are, setup (optional) mmio access offset
nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0) nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
st b32 D[$r0 + #gpc_id] $r2 st b32 D[$r0 + #gpc_id] $r2
shl b32 $r2 15
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)
#if NV_PGRAPH_GPCX_UNK__SIZE > 0 #if NV_PGRAPH_GPCX_UNK__SIZE > 0
// figure out which, and how many, UNKs are actually present // figure out which, and how many, UNKs are actually present
...@@ -186,8 +233,56 @@ init: ...@@ -186,8 +233,56 @@ init:
// calculate size of strand context data // calculate size of strand context data
mov b32 $r15 $r2 mov b32 $r15 $r2
call(strand_ctx_init) call(strand_ctx_init)
add b32 $r2 $r15
add b32 $r3 $r15 add b32 $r3 $r15
#if CHIPSET >= GM107
// calculate size of tpc strand context data
mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
tpc_strand_enable();
tpc_strand_seek(0);
tpc_strand_info(-1);
ld b32 $r4 D[$r0 + #tpc_count]
mov $r5 NV_PGRAPH_GPC0_TPC0
ld b32 $r6 D[$r0 + #gpc_id]
shl b32 $r6 15
add b32 $r5 $r6
tpc_strand_init_tpc_loop:
add b32 $r14 $r5 NV_TPC_STRAND_CNT
call(nv_rd32)
mov b32 $r6 $r15
clear b32 $r7
tpc_strand_init_idx_loop:
add b32 $r14 $r5 NV_TPC_STRAND_INDEX
mov b32 $r15 $r7
call(nv_wr32)
add b32 $r14 $r5 NV_TPC_STRAND_SAVE_SWBASE
shr b32 $r15 $r2 8
call(nv_wr32)
add b32 $r14 $r5 NV_TPC_STRAND_LOAD_SWBASE
shr b32 $r15 $r2 8
call(nv_wr32)
add b32 $r14 $r5 NV_TPC_STRAND_WORDS
call(nv_rd32)
shr b32 $r15 6
add b32 $r15 1
shl b32 $r15 8
add b32 $r2 $r15
add b32 $r3 $r15
add b32 $r7 1
sub b32 $r6 1
bra nz #tpc_strand_init_idx_loop
add b32 $r5 NV_PGRAPH_GPC0_TPC0__SIZE
sub b32 $r4 1
bra nz #tpc_strand_init_tpc_loop
mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_INDEX, $r15)
tpc_strand_disable();
#endif
// save context size, and tell HUB we're done // save context size, and tell HUB we're done
nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3) nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
clear b32 $r2 clear b32 $r2
...@@ -306,6 +401,9 @@ ctx_redswitch: ...@@ -306,6 +401,9 @@ ctx_redswitch:
ctx_xfer: ctx_xfer:
// set context base address // set context base address
nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15) nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15)
#if CHIPSET >= GM107
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE, $r15)
#endif
bra not $p1 #ctx_xfer_not_load bra not $p1 #ctx_xfer_not_load
call(ctx_redswitch) call(ctx_redswitch)
ctx_xfer_not_load: ctx_xfer_not_load:
...@@ -318,6 +416,14 @@ ctx_xfer: ...@@ -318,6 +416,14 @@ ctx_xfer:
add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE
nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2) nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2)
#if CHIPSET >= GM107
tpc_strand_enable();
tpc_strand_seek(0);
xbit $r15 $flags $p1 // SAVE/LOAD
add b32 $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE
gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15)
#endif
// mmio context // mmio context
xbit $r10 $flags $p1 // direction xbit $r10 $flags $p1 // direction
or $r10 2 // first or $r10 2 // first
...@@ -362,6 +468,9 @@ ctx_xfer: ...@@ -362,6 +468,9 @@ ctx_xfer:
// wait for strands to finish // wait for strands to finish
call(strand_wait) call(strand_wait)
#if CHIPSET >= GM107
tpc_strand_wait()
#endif
// if load, or a save without a load following, do some // if load, or a save without a load following, do some
// unknown stuff that's done after finishing a block of // unknown stuff that's done after finishing a block of
...@@ -370,6 +479,9 @@ ctx_xfer: ...@@ -370,6 +479,9 @@ ctx_xfer:
bra not $p2 #ctx_xfer_done bra not $p2 #ctx_xfer_done
ctx_xfer_post: ctx_xfer_post:
call(strand_post) call(strand_post)
#if CHIPSET >= GM107
tpc_strand_disable()
#endif
// mark completion in HUB's barrier // mark completion in HUB's barrier
ctx_xfer_done: ctx_xfer_done:
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
View file @ 665ae581
...@@ -310,7 +310,7 @@ uint32_t gf100_grgpc_code[] = { ...@@ -310,7 +310,7 @@ uint32_t gf100_grgpc_code[] = {
0x03f01200, 0x03f01200,
0x0002d000, 0x0002d000,
0x17f104bd, 0x17f104bd,
0x10fe04e6, 0x10fe04f8,
0x0007f100, 0x0007f100,
0x0003f007, 0x0003f007,
0xbd0000d0, 0xbd0000d0,
...@@ -329,157 +329,157 @@ uint32_t gf100_grgpc_code[] = { ...@@ -329,157 +329,157 @@ uint32_t gf100_grgpc_code[] = {
0xf0860027, 0xf0860027,
0x22cf0123, 0x22cf0123,
0x04028000, 0x04028000,
0x010027f1, 0xf10f24b6,
0xcf0223f0, 0xf0c90007,
0x34bd0022, 0x02d00103,
0xf1082595,
0xf0c00007,
0x05d00103,
0xf104bd00, 0xf104bd00,
0xf0c10007, 0xf0010027,
0x05d00103, 0x22cf0223,
0x9804bd00, 0x9534bd00,
0x0f98000e, 0x07f10825,
0x5021f501, 0x03f0c000,
0x002fbb01, 0x0005d001,
0x98003fbb, 0x07f104bd,
0x0f98010e, 0x03f0c100,
0x5021f502, 0x0005d001,
0x050e9801, 0x0e9804bd,
0xbb00effd, 0x010f9800,
0x3ebb002e, 0x015021f5,
0x0235b600, 0xbb002fbb,
0xd30007f1, 0x0e98003f,
0xd00103f0, 0x020f9801,
0x04bd0003, 0x015021f5,
0xb60825b6, 0xfd050e98,
0x20b60635, 0x2ebb00ef,
0x0130b601, 0x003ebb00,
0xb60824b6, 0xf10235b6,
0x2fb90834, 0xf0d30007,
0xd321f502, 0x03d00103,
0x003fbb02, 0xb604bd00,
0x010007f1, 0x35b60825,
0x0120b606,
0xb60130b6,
0x34b60824,
0x022fb908,
0x02d321f5,
0xbb002fbb,
0x07f1003f,
0x03f00100,
0x0003d002,
0x24bd04bd,
0xf11f29f0,
0xf0080007,
0x02d00203,
/* 0x04bb: main */
0xf404bd00,
0x28f40031,
0x1cd7f000,
0xf43921f4,
0xe4b0f401,
0x1e18f404,
0xf00181fe,
0x20bd0627,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x05b021f5,
/* 0x04eb: main_not_ctx_xfer */
0x94d30ef4,
0xf5f010ef,
0x7e21f501,
0xc60ef403,
/* 0x04f8: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x00a7f104,
0x00a3f002,
0xc400aacf,
0x0bf404ab,
0x1cd7f02c,
0x1a00e7f1,
0xcf00e3f0,
0xf7f100ee,
0xf3f01900,
0x00ffcf00,
0xf00421f4,
0x07f101e7,
0x03f01d00,
0x000ed000,
/* 0x0546: ih_no_fifo */
0x07f104bd,
0x03f00100,
0x000ad000,
0xf0fc04bd,
0xd0fce0fc,
0xa0fcb0fc,
0x80fc90fc,
0xfc0088fe,
0x0032f480,
/* 0x056a: hub_barrier_done */
0xf7f001f8,
0x040e9801,
0xb904febb,
0xe7f102ff,
0xe3f09418,
0x9d21f440,
/* 0x0582: ctx_redswitch */
0xf7f000f8,
0x0007f120,
0x0103f085,
0xbd000fd0,
0x08e7f004,
/* 0x0594: ctx_redswitch_delay */
0xf401e2b6,
0xf5f1fd1b,
0xf5f10800,
0x07f10200,
0x03f08500,
0x000fd001,
0x00f804bd,
/* 0x05b0: ctx_xfer */
0x810007f1,
0xd00203f0, 0xd00203f0,
0x04bd0003,
0x29f024bd,
0x0007f11f,
0x0203f008,
0xbd0002d0,
/* 0x04a9: main */
0x0031f404,
0xf00028f4,
0x21f41cd7,
0xf401f439,
0xf404e4b0,
0x81fe1e18,
0x0627f001,
0x12fd20bd,
0x01e4b604,
0xfe051efd,
0x21f50018,
0x0ef4059e,
/* 0x04d9: main_not_ctx_xfer */
0x10ef94d3,
0xf501f5f0,
0xf4037e21,
/* 0x04e6: ih */
0x80f9c60e,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0xf104bdf0,
0xf00200a7,
0xaacf00a3,
0x04abc400,
0xf02c0bf4,
0xe7f11cd7,
0xe3f01a00,
0x00eecf00,
0x1900f7f1,
0xcf00f3f0,
0x21f400ff,
0x01e7f004,
0x1d0007f1,
0xd00003f0,
0x04bd000e,
/* 0x0534: ih_no_fifo */
0x010007f1,
0xd00003f0,
0x04bd000a,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xf480fc00,
0x01f80032,
/* 0x0558: hub_barrier_done */
0x9801f7f0,
0xfebb040e,
0x02ffb904,
0x9418e7f1,
0xf440e3f0,
0x00f89d21,
/* 0x0570: ctx_redswitch */
0xf120f7f0,
0xf0850007,
0x0fd00103,
0xf004bd00,
/* 0x0582: ctx_redswitch_delay */
0xe2b608e7,
0xfd1bf401,
0x0800f5f1,
0x0200f5f1,
0x850007f1,
0xd00103f0,
0x04bd000f, 0x04bd000f,
/* 0x059e: ctx_xfer */ 0xf50711f4,
0x07f100f8, /* 0x05c3: ctx_xfer_not_load */
0x03f08100, 0xf5058221,
0x000fd002, 0xbd026a21,
0x11f404bd, 0xfc07f124,
0x7021f507, 0x0203f047,
/* 0x05b1: ctx_xfer_not_load */ 0xbd0002d0,
0x6a21f505, 0x012cf004,
0xf124bd02, 0xf10320b6,
0xf047fc07, 0xf04afc07,
0x02d00203, 0x02d00203,
0xf004bd00, 0xf004bd00,
0x20b6012c, 0xa5f001ac,
0xfc07f103, 0x00b7f102,
0x0203f04a, 0x50b3f000,
0xbd0002d0, 0xb6040c98,
0x01acf004, 0xbcbb0fc4,
0xf102a5f0, 0x000c9800,
0xf00000b7, 0xf0010d98,
0x0c9850b3, 0x21f500e7,
0x0fc4b604, 0xacf0016f,
0x9800bcbb, 0x04a5f001,
0x0d98000c, 0x4000b7f1,
0x00e7f001, 0x9850b3f0,
0x016f21f5, 0xc4b6040c,
0xf001acf0, 0x00bcbb0f,
0xb7f104a5, 0x98010c98,
0xb3f04000, 0x0f98020d,
0x040c9850, 0x00e7f106,
0xbb0fc4b6, 0x6f21f508,
0x0c9800bc, 0x5e21f501,
0x020d9801, 0x0601f402,
0xf1060f98, /* 0x063b: ctx_xfer_post */
0xf50800e7, 0xf50712f4,
0xf5016f21, /* 0x063f: ctx_xfer_done */
0xf4025e21, 0xf5027f21,
0x12f40601, 0xf8056a21,
/* 0x0629: ctx_xfer_post */
0x7f21f507,
/* 0x062d: ctx_xfer_done */
0x5821f502,
0x0000f805,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
View file @ 665ae581
...@@ -314,7 +314,7 @@ uint32_t gf117_grgpc_code[] = { ...@@ -314,7 +314,7 @@ uint32_t gf117_grgpc_code[] = {
0x03f01200, 0x03f01200,
0x0002d000, 0x0002d000,
0x17f104bd, 0x17f104bd,
0x10fe0530, 0x10fe0542,
0x0007f100, 0x0007f100,
0x0003f007, 0x0003f007,
0xbd0000d0, 0xbd0000d0,
...@@ -333,188 +333,188 @@ uint32_t gf117_grgpc_code[] = { ...@@ -333,188 +333,188 @@ uint32_t gf117_grgpc_code[] = {
0xf0860027, 0xf0860027,
0x22cf0123, 0x22cf0123,
0x04028000, 0x04028000,
0x0c30e7f1, 0xf10f24b6,
0xbd50e3f0, 0xf0c90007,
0xbd34bd24, 0x02d00103,
/* 0x0421: init_unk_loop */
0x6821f444,
0xf400f6b0,
0xf7f00f0b,
0x04f2bb01,
0xb6054ffd,
/* 0x0436: init_unk_next */
0x20b60130,
0x04e0b601,
0xf40126b0,
/* 0x0442: init_unk_done */
0x0380e21b,
0x08048007,
0x010027f1,
0xcf0223f0,
0x34bd0022,
0xf1082595,
0xf0c00007,
0x05d00103,
0xf104bd00, 0xf104bd00,
0xf0c10007, 0xf00c30e7,
0x05d00103, 0x24bd50e3,
0x9804bd00, 0x44bd34bd,
0x0f98000e, /* 0x0430: init_unk_loop */
0x5021f501, 0xb06821f4,
0x002fbb01, 0x0bf400f6,
0x98003fbb, 0x01f7f00f,
0x0f98010e, 0xfd04f2bb,
0x5021f502, 0x30b6054f,
0x050e9801, /* 0x0445: init_unk_next */
0xbb00effd, 0x0120b601,
0x3ebb002e, 0xb004e0b6,
0x020e9800, 0x1bf40126,
0xf5030f98, /* 0x0451: init_unk_done */
0x98015021, 0x070380e2,
0xeffd070e, 0xf1080480,
0x002ebb00, 0xf0010027,
0xb6003ebb, 0x22cf0223,
0x07f10235, 0x9534bd00,
0x03f0d300, 0x07f10825,
0x0003d001, 0x03f0c000,
0x25b604bd, 0x0005d001,
0x0635b608,
0xb60120b6,
0x24b60130,
0x0834b608,
0xf5022fb9,
0xbb02d321,
0x07f1003f,
0x03f00100,
0x0003d002,
0x24bd04bd,
0xf11f29f0,
0xf0080007,
0x02d00203,
/* 0x04f3: main */
0xf404bd00,
0x28f40031,
0x24d7f000,
0xf43921f4,
0xe4b0f401,
0x1e18f404,
0xf00181fe,
0x20bd0627,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x05e821f5,
/* 0x0523: main_not_ctx_xfer */
0x94d30ef4,
0xf5f010ef,
0x7e21f501,
0xc60ef403,
/* 0x0530: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x00a7f104,
0x00a3f002,
0xc400aacf,
0x0bf404ab,
0x24d7f02c,
0x1a00e7f1,
0xcf00e3f0,
0xf7f100ee,
0xf3f01900,
0x00ffcf00,
0xf00421f4,
0x07f101e7,
0x03f01d00,
0x000ed000,
/* 0x057e: ih_no_fifo */
0x07f104bd, 0x07f104bd,
0x03f00100, 0x03f0c100,
0x000ad000, 0x0005d001,
0xf0fc04bd, 0x0e9804bd,
0xd0fce0fc, 0x010f9800,
0xa0fcb0fc, 0x015021f5,
0x80fc90fc, 0xbb002fbb,
0xfc0088fe, 0x0e98003f,
0x0032f480, 0x020f9801,
/* 0x05a2: hub_barrier_done */ 0x015021f5,
0xf7f001f8, 0xfd050e98,
0x040e9801, 0x2ebb00ef,
0xb904febb, 0x003ebb00,
0xe7f102ff, 0x98020e98,
0xe3f09418, 0x21f5030f,
0x9d21f440, 0x0e980150,
/* 0x05ba: ctx_redswitch */ 0x00effd07,
0xf7f000f8, 0xbb002ebb,
0x0007f120, 0x35b6003e,
0x0103f085, 0x0007f102,
0xbd000fd0, 0x0103f0d3,
0x08e7f004, 0xbd0003d0,
/* 0x05cc: ctx_redswitch_delay */ 0x0825b604,
0xf401e2b6, 0xb60635b6,
0xf5f1fd1b, 0x30b60120,
0xf5f10800, 0x0824b601,
0x07f10200, 0xb90834b6,
0x03f08500, 0x21f5022f,
0x000fd001, 0x2fbb02d3,
0x00f804bd, 0x003fbb00,
/* 0x05e8: ctx_xfer */ 0x010007f1,
0x810007f1,
0xd00203f0, 0xd00203f0,
0x04bd000f, 0x04bd0003,
0xf50711f4, 0x29f024bd,
/* 0x05fb: ctx_xfer_not_load */ 0x0007f11f,
0xf505ba21, 0x0203f008,
0xbd026a21,
0xfc07f124,
0x0203f047,
0xbd0002d0, 0xbd0002d0,
0x012cf004, /* 0x0505: main */
0xf10320b6, 0x0031f404,
0xf04afc07, 0xf00028f4,
0x21f424d7,
0xf401f439,
0xf404e4b0,
0x81fe1e18,
0x0627f001,
0x12fd20bd,
0x01e4b604,
0xfe051efd,
0x21f50018,
0x0ef405fa,
/* 0x0535: main_not_ctx_xfer */
0x10ef94d3,
0xf501f5f0,
0xf4037e21,
/* 0x0542: ih */
0x80f9c60e,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0xf104bdf0,
0xf00200a7,
0xaacf00a3,
0x04abc400,
0xf02c0bf4,
0xe7f124d7,
0xe3f01a00,
0x00eecf00,
0x1900f7f1,
0xcf00f3f0,
0x21f400ff,
0x01e7f004,
0x1d0007f1,
0xd00003f0,
0x04bd000e,
/* 0x0590: ih_no_fifo */
0x010007f1,
0xd00003f0,
0x04bd000a,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xf480fc00,
0x01f80032,
/* 0x05b4: hub_barrier_done */
0x9801f7f0,
0xfebb040e,
0x02ffb904,
0x9418e7f1,
0xf440e3f0,
0x00f89d21,
/* 0x05cc: ctx_redswitch */
0xf120f7f0,
0xf0850007,
0x0fd00103,
0xf004bd00,
/* 0x05de: ctx_redswitch_delay */
0xe2b608e7,
0xfd1bf401,
0x0800f5f1,
0x0200f5f1,
0x850007f1,
0xd00103f0,
0x04bd000f,
/* 0x05fa: ctx_xfer */
0x07f100f8,
0x03f08100,
0x000fd002,
0x11f404bd,
0xcc21f507,
/* 0x060d: ctx_xfer_not_load */
0x6a21f505,
0xf124bd02,
0xf047fc07,
0x02d00203, 0x02d00203,
0xf004bd00, 0xf004bd00,
0xa5f001ac, 0x20b6012c,
0x00b7f102, 0xfc07f103,
0x50b3f000, 0x0203f04a,
0xb6040c98, 0xbd0002d0,
0xbcbb0fc4, 0x01acf004,
0x000c9800, 0xf102a5f0,
0xf0010d98, 0xf00000b7,
0x21f500e7, 0x0c9850b3,
0xacf0016f, 0x0fc4b604,
0x00b7f101, 0x9800bcbb,
0x50b3f040, 0x0d98000c,
0xb6040c98, 0x00e7f001,
0xbcbb0fc4, 0x016f21f5,
0x010c9800, 0xf101acf0,
0x98020d98, 0xf04000b7,
0xe7f1060f, 0x0c9850b3,
0x21f50800, 0x0fc4b604,
0xacf0016f, 0x9800bcbb,
0x04a5f001, 0x0d98010c,
0x3000b7f1, 0x060f9802,
0x9850b3f0, 0x0800e7f1,
0xc4b6040c, 0x016f21f5,
0x00bcbb0f, 0xf001acf0,
0x98020c98, 0xb7f104a5,
0x0f98030d, 0xb3f03000,
0x00e7f108, 0x040c9850,
0x6f21f502, 0xbb0fc4b6,
0x5e21f501, 0x0c9800bc,
0x0601f402, 0x030d9802,
/* 0x0697: ctx_xfer_post */ 0xf1080f98,
0xf50712f4, 0xf50200e7,
/* 0x069b: ctx_xfer_done */ 0xf5016f21,
0xf5027f21, 0xf4025e21,
0xf805a221, 0x12f40601,
0x00000000, /* 0x06a9: ctx_xfer_post */
0x00000000, 0x7f21f507,
0x00000000, /* 0x06ad: ctx_xfer_done */
0x00000000, 0xb421f502,
0x00000000, 0x0000f805,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
View file @ 665ae581
...@@ -314,7 +314,7 @@ uint32_t gk104_grgpc_code[] = { ...@@ -314,7 +314,7 @@ uint32_t gk104_grgpc_code[] = {
0x03f01200, 0x03f01200,
0x0002d000, 0x0002d000,
0x17f104bd, 0x17f104bd,
0x10fe0530, 0x10fe0542,
0x0007f100, 0x0007f100,
0x0003f007, 0x0003f007,
0xbd0000d0, 0xbd0000d0,
...@@ -333,188 +333,188 @@ uint32_t gk104_grgpc_code[] = { ...@@ -333,188 +333,188 @@ uint32_t gk104_grgpc_code[] = {
0xf0860027, 0xf0860027,
0x22cf0123, 0x22cf0123,
0x04028000, 0x04028000,
0x0c30e7f1, 0xf10f24b6,
0xbd50e3f0, 0xf0c90007,
0xbd34bd24, 0x02d00103,
/* 0x0421: init_unk_loop */
0x6821f444,
0xf400f6b0,
0xf7f00f0b,
0x04f2bb01,
0xb6054ffd,
/* 0x0436: init_unk_next */
0x20b60130,
0x04e0b601,
0xf40126b0,
/* 0x0442: init_unk_done */
0x0380e21b,
0x08048007,
0x010027f1,
0xcf0223f0,
0x34bd0022,
0xf1082595,
0xf0c00007,
0x05d00103,
0xf104bd00, 0xf104bd00,
0xf0c10007, 0xf00c30e7,
0x05d00103, 0x24bd50e3,
0x9804bd00, 0x44bd34bd,
0x0f98000e, /* 0x0430: init_unk_loop */
0x5021f501, 0xb06821f4,
0x002fbb01, 0x0bf400f6,
0x98003fbb, 0x01f7f00f,
0x0f98010e, 0xfd04f2bb,
0x5021f502, 0x30b6054f,
0x050e9801, /* 0x0445: init_unk_next */
0xbb00effd, 0x0120b601,
0x3ebb002e, 0xb004e0b6,
0x020e9800, 0x1bf40126,
0xf5030f98, /* 0x0451: init_unk_done */
0x98015021, 0x070380e2,
0xeffd070e, 0xf1080480,
0x002ebb00, 0xf0010027,
0xb6003ebb, 0x22cf0223,
0x07f10235, 0x9534bd00,
0x03f0d300, 0x07f10825,
0x0003d001, 0x03f0c000,
0x25b604bd, 0x0005d001,
0x0635b608,
0xb60120b6,
0x24b60130,
0x0834b608,
0xf5022fb9,
0xbb02d321,
0x07f1003f,
0x03f00100,
0x0003d002,
0x24bd04bd,
0xf11f29f0,
0xf0080007,
0x02d00203,
/* 0x04f3: main */
0xf404bd00,
0x28f40031,
0x24d7f000,
0xf43921f4,
0xe4b0f401,
0x1e18f404,
0xf00181fe,
0x20bd0627,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x05e821f5,
/* 0x0523: main_not_ctx_xfer */
0x94d30ef4,
0xf5f010ef,
0x7e21f501,
0xc60ef403,
/* 0x0530: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x00a7f104,
0x00a3f002,
0xc400aacf,
0x0bf404ab,
0x24d7f02c,
0x1a00e7f1,
0xcf00e3f0,
0xf7f100ee,
0xf3f01900,
0x00ffcf00,
0xf00421f4,
0x07f101e7,
0x03f01d00,
0x000ed000,
/* 0x057e: ih_no_fifo */
0x07f104bd, 0x07f104bd,
0x03f00100, 0x03f0c100,
0x000ad000, 0x0005d001,
0xf0fc04bd, 0x0e9804bd,
0xd0fce0fc, 0x010f9800,
0xa0fcb0fc, 0x015021f5,
0x80fc90fc, 0xbb002fbb,
0xfc0088fe, 0x0e98003f,
0x0032f480, 0x020f9801,
/* 0x05a2: hub_barrier_done */ 0x015021f5,
0xf7f001f8, 0xfd050e98,
0x040e9801, 0x2ebb00ef,
0xb904febb, 0x003ebb00,
0xe7f102ff, 0x98020e98,
0xe3f09418, 0x21f5030f,
0x9d21f440, 0x0e980150,
/* 0x05ba: ctx_redswitch */ 0x00effd07,
0xf7f000f8, 0xbb002ebb,
0x0007f120, 0x35b6003e,
0x0103f085, 0x0007f102,
0xbd000fd0, 0x0103f0d3,
0x08e7f004, 0xbd0003d0,
/* 0x05cc: ctx_redswitch_delay */ 0x0825b604,
0xf401e2b6, 0xb60635b6,
0xf5f1fd1b, 0x30b60120,
0xf5f10800, 0x0824b601,
0x07f10200, 0xb90834b6,
0x03f08500, 0x21f5022f,
0x000fd001, 0x2fbb02d3,
0x00f804bd, 0x003fbb00,
/* 0x05e8: ctx_xfer */ 0x010007f1,
0x810007f1,
0xd00203f0, 0xd00203f0,
0x04bd000f, 0x04bd0003,
0xf50711f4, 0x29f024bd,
/* 0x05fb: ctx_xfer_not_load */ 0x0007f11f,
0xf505ba21, 0x0203f008,
0xbd026a21,
0xfc07f124,
0x0203f047,
0xbd0002d0, 0xbd0002d0,
0x012cf004, /* 0x0505: main */
0xf10320b6, 0x0031f404,
0xf04afc07, 0xf00028f4,
0x21f424d7,
0xf401f439,
0xf404e4b0,
0x81fe1e18,
0x0627f001,
0x12fd20bd,
0x01e4b604,
0xfe051efd,
0x21f50018,
0x0ef405fa,
/* 0x0535: main_not_ctx_xfer */
0x10ef94d3,
0xf501f5f0,
0xf4037e21,
/* 0x0542: ih */
0x80f9c60e,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0xf104bdf0,
0xf00200a7,
0xaacf00a3,
0x04abc400,
0xf02c0bf4,
0xe7f124d7,
0xe3f01a00,
0x00eecf00,
0x1900f7f1,
0xcf00f3f0,
0x21f400ff,
0x01e7f004,
0x1d0007f1,
0xd00003f0,
0x04bd000e,
/* 0x0590: ih_no_fifo */
0x010007f1,
0xd00003f0,
0x04bd000a,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xf480fc00,
0x01f80032,
/* 0x05b4: hub_barrier_done */
0x9801f7f0,
0xfebb040e,
0x02ffb904,
0x9418e7f1,
0xf440e3f0,
0x00f89d21,
/* 0x05cc: ctx_redswitch */
0xf120f7f0,
0xf0850007,
0x0fd00103,
0xf004bd00,
/* 0x05de: ctx_redswitch_delay */
0xe2b608e7,
0xfd1bf401,
0x0800f5f1,
0x0200f5f1,
0x850007f1,
0xd00103f0,
0x04bd000f,
/* 0x05fa: ctx_xfer */
0x07f100f8,
0x03f08100,
0x000fd002,
0x11f404bd,
0xcc21f507,
/* 0x060d: ctx_xfer_not_load */
0x6a21f505,
0xf124bd02,
0xf047fc07,
0x02d00203, 0x02d00203,
0xf004bd00, 0xf004bd00,
0xa5f001ac, 0x20b6012c,
0x00b7f102, 0xfc07f103,
0x50b3f000, 0x0203f04a,
0xb6040c98, 0xbd0002d0,
0xbcbb0fc4, 0x01acf004,
0x000c9800, 0xf102a5f0,
0xf0010d98, 0xf00000b7,
0x21f500e7, 0x0c9850b3,
0xacf0016f, 0x0fc4b604,
0x00b7f101, 0x9800bcbb,
0x50b3f040, 0x0d98000c,
0xb6040c98, 0x00e7f001,
0xbcbb0fc4, 0x016f21f5,
0x010c9800, 0xf101acf0,
0x98020d98, 0xf04000b7,
0xe7f1060f, 0x0c9850b3,
0x21f50800, 0x0fc4b604,
0xacf0016f, 0x9800bcbb,
0x04a5f001, 0x0d98010c,
0x3000b7f1, 0x060f9802,
0x9850b3f0, 0x0800e7f1,
0xc4b6040c, 0x016f21f5,
0x00bcbb0f, 0xf001acf0,
0x98020c98, 0xb7f104a5,
0x0f98030d, 0xb3f03000,
0x00e7f108, 0x040c9850,
0x6f21f502, 0xbb0fc4b6,
0x5e21f501, 0x0c9800bc,
0x0601f402, 0x030d9802,
/* 0x0697: ctx_xfer_post */ 0xf1080f98,
0xf50712f4, 0xf50200e7,
/* 0x069b: ctx_xfer_done */ 0xf5016f21,
0xf5027f21, 0xf4025e21,
0xf805a221, 0x12f40601,
0x00000000, /* 0x06a9: ctx_xfer_post */
0x00000000, 0x7f21f507,
0x00000000, /* 0x06ad: ctx_xfer_done */
0x00000000, 0xb421f502,
0x00000000, 0x0000f805,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
View file @ 665ae581
...@@ -314,7 +314,7 @@ uint32_t gk110_grgpc_code[] = { ...@@ -314,7 +314,7 @@ uint32_t gk110_grgpc_code[] = {
0x03f01200, 0x03f01200,
0x0002d000, 0x0002d000,
0x17f104bd, 0x17f104bd,
0x10fe0530, 0x10fe0542,
0x0007f100, 0x0007f100,
0x0003f007, 0x0003f007,
0xbd0000d0, 0xbd0000d0,
...@@ -333,188 +333,188 @@ uint32_t gk110_grgpc_code[] = { ...@@ -333,188 +333,188 @@ uint32_t gk110_grgpc_code[] = {
0xf0860027, 0xf0860027,
0x22cf0123, 0x22cf0123,
0x04028000, 0x04028000,
0x0c30e7f1, 0xf10f24b6,
0xbd50e3f0, 0xf0c90007,
0xbd34bd24, 0x02d00103,
/* 0x0421: init_unk_loop */
0x6821f444,
0xf400f6b0,
0xf7f00f0b,
0x04f2bb01,
0xb6054ffd,
/* 0x0436: init_unk_next */
0x20b60130,
0x04e0b601,
0xf40226b0,
/* 0x0442: init_unk_done */
0x0380e21b,
0x08048007,
0x010027f1,
0xcf0223f0,
0x34bd0022,
0xf1082595,
0xf0c00007,
0x05d00103,
0xf104bd00, 0xf104bd00,
0xf0c10007, 0xf00c30e7,
0x05d00103, 0x24bd50e3,
0x9804bd00, 0x44bd34bd,
0x0f98000e, /* 0x0430: init_unk_loop */
0x5021f501, 0xb06821f4,
0x002fbb01, 0x0bf400f6,
0x98003fbb, 0x01f7f00f,
0x0f98010e, 0xfd04f2bb,
0x5021f502, 0x30b6054f,
0x050e9801, /* 0x0445: init_unk_next */
0xbb00effd, 0x0120b601,
0x3ebb002e, 0xb004e0b6,
0x020e9800, 0x1bf40226,
0xf5030f98, /* 0x0451: init_unk_done */
0x98015021, 0x070380e2,
0xeffd070e, 0xf1080480,
0x002ebb00, 0xf0010027,
0xb6003ebb, 0x22cf0223,
0x07f10235, 0x9534bd00,
0x03f0d300, 0x07f10825,
0x0003d001, 0x03f0c000,
0x25b604bd, 0x0005d001,
0x0635b608,
0xb60120b6,
0x24b60130,
0x0834b608,
0xf5022fb9,
0xbb02d321,
0x07f1003f,
0x03f00100,
0x0003d002,
0x24bd04bd,
0xf11f29f0,
0xf0300007,
0x02d00203,
/* 0x04f3: main */
0xf404bd00,
0x28f40031,
0x24d7f000,
0xf43921f4,
0xe4b0f401,
0x1e18f404,
0xf00181fe,
0x20bd0627,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x05e821f5,
/* 0x0523: main_not_ctx_xfer */
0x94d30ef4,
0xf5f010ef,
0x7e21f501,
0xc60ef403,
/* 0x0530: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x00a7f104,
0x00a3f002,
0xc400aacf,
0x0bf404ab,
0x24d7f02c,
0x1a00e7f1,
0xcf00e3f0,
0xf7f100ee,
0xf3f01900,
0x00ffcf00,
0xf00421f4,
0x07f101e7,
0x03f01d00,
0x000ed000,
/* 0x057e: ih_no_fifo */
0x07f104bd, 0x07f104bd,
0x03f00100, 0x03f0c100,
0x000ad000, 0x0005d001,
0xf0fc04bd, 0x0e9804bd,
0xd0fce0fc, 0x010f9800,
0xa0fcb0fc, 0x015021f5,
0x80fc90fc, 0xbb002fbb,
0xfc0088fe, 0x0e98003f,
0x0032f480, 0x020f9801,
/* 0x05a2: hub_barrier_done */ 0x015021f5,
0xf7f001f8, 0xfd050e98,
0x040e9801, 0x2ebb00ef,
0xb904febb, 0x003ebb00,
0xe7f102ff, 0x98020e98,
0xe3f09418, 0x21f5030f,
0x9d21f440, 0x0e980150,
/* 0x05ba: ctx_redswitch */ 0x00effd07,
0xf7f000f8, 0xbb002ebb,
0x0007f120, 0x35b6003e,
0x0103f085, 0x0007f102,
0xbd000fd0, 0x0103f0d3,
0x08e7f004, 0xbd0003d0,
/* 0x05cc: ctx_redswitch_delay */ 0x0825b604,
0xf401e2b6, 0xb60635b6,
0xf5f1fd1b, 0x30b60120,
0xf5f10800, 0x0824b601,
0x07f10200, 0xb90834b6,
0x03f08500, 0x21f5022f,
0x000fd001, 0x2fbb02d3,
0x00f804bd, 0x003fbb00,
/* 0x05e8: ctx_xfer */ 0x010007f1,
0x810007f1,
0xd00203f0, 0xd00203f0,
0x04bd000f, 0x04bd0003,
0xf50711f4, 0x29f024bd,
/* 0x05fb: ctx_xfer_not_load */ 0x0007f11f,
0xf505ba21, 0x0203f030,
0xbd026a21,
0xfc07f124,
0x0203f047,
0xbd0002d0, 0xbd0002d0,
0x012cf004, /* 0x0505: main */
0xf10320b6, 0x0031f404,
0xf04afc07, 0xf00028f4,
0x21f424d7,
0xf401f439,
0xf404e4b0,
0x81fe1e18,
0x0627f001,
0x12fd20bd,
0x01e4b604,
0xfe051efd,
0x21f50018,
0x0ef405fa,
/* 0x0535: main_not_ctx_xfer */
0x10ef94d3,
0xf501f5f0,
0xf4037e21,
/* 0x0542: ih */
0x80f9c60e,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0xf104bdf0,
0xf00200a7,
0xaacf00a3,
0x04abc400,
0xf02c0bf4,
0xe7f124d7,
0xe3f01a00,
0x00eecf00,
0x1900f7f1,
0xcf00f3f0,
0x21f400ff,
0x01e7f004,
0x1d0007f1,
0xd00003f0,
0x04bd000e,
/* 0x0590: ih_no_fifo */
0x010007f1,
0xd00003f0,
0x04bd000a,
0xe0fcf0fc,
0xb0fcd0fc,
0x90fca0fc,
0x88fe80fc,
0xf480fc00,
0x01f80032,
/* 0x05b4: hub_barrier_done */
0x9801f7f0,
0xfebb040e,
0x02ffb904,
0x9418e7f1,
0xf440e3f0,
0x00f89d21,
/* 0x05cc: ctx_redswitch */
0xf120f7f0,
0xf0850007,
0x0fd00103,
0xf004bd00,
/* 0x05de: ctx_redswitch_delay */
0xe2b608e7,
0xfd1bf401,
0x0800f5f1,
0x0200f5f1,
0x850007f1,
0xd00103f0,
0x04bd000f,
/* 0x05fa: ctx_xfer */
0x07f100f8,
0x03f08100,
0x000fd002,
0x11f404bd,
0xcc21f507,
/* 0x060d: ctx_xfer_not_load */
0x6a21f505,
0xf124bd02,
0xf047fc07,
0x02d00203, 0x02d00203,
0xf004bd00, 0xf004bd00,
0xa5f001ac, 0x20b6012c,
0x00b7f102, 0xfc07f103,
0x50b3f000, 0x0203f04a,
0xb6040c98, 0xbd0002d0,
0xbcbb0fc4, 0x01acf004,
0x000c9800, 0xf102a5f0,
0xf0010d98, 0xf00000b7,
0x21f500e7, 0x0c9850b3,
0xacf0016f, 0x0fc4b604,
0x00b7f101, 0x9800bcbb,
0x50b3f040, 0x0d98000c,
0xb6040c98, 0x00e7f001,
0xbcbb0fc4, 0x016f21f5,
0x010c9800, 0xf101acf0,
0x98020d98, 0xf04000b7,
0xe7f1060f, 0x0c9850b3,
0x21f50800, 0x0fc4b604,
0xacf0016f, 0x9800bcbb,
0x04a5f001, 0x0d98010c,
0x3000b7f1, 0x060f9802,
0x9850b3f0, 0x0800e7f1,
0xc4b6040c, 0x016f21f5,
0x00bcbb0f, 0xf001acf0,
0x98020c98, 0xb7f104a5,
0x0f98030d, 0xb3f03000,
0x00e7f108, 0x040c9850,
0x6f21f502, 0xbb0fc4b6,
0x5e21f501, 0x0c9800bc,
0x0601f402, 0x030d9802,
/* 0x0697: ctx_xfer_post */ 0xf1080f98,
0xf50712f4, 0xf50200e7,
/* 0x069b: ctx_xfer_done */ 0xf5016f21,
0xf5027f21, 0xf4025e21,
0xf805a221, 0x12f40601,
0x00000000, /* 0x06a9: ctx_xfer_post */
0x00000000, 0x7f21f507,
0x00000000, /* 0x06ad: ctx_xfer_done */
0x00000000, 0xb421f502,
0x00000000, 0x0000f805,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
View file @ 665ae581
...@@ -276,7 +276,7 @@ uint32_t gk208_grgpc_code[] = { ...@@ -276,7 +276,7 @@ uint32_t gk208_grgpc_code[] = {
0x02020014, 0x02020014,
0xf6120040, 0xf6120040,
0x04bd0002, 0x04bd0002,
0xfe047241, 0xfe048141,
0x00400010, 0x00400010,
0x0000f607, 0x0000f607,
0x040204bd, 0x040204bd,
...@@ -291,20 +291,23 @@ uint32_t gk208_grgpc_code[] = { ...@@ -291,20 +291,23 @@ uint32_t gk208_grgpc_code[] = {
0x820603b5, 0x820603b5,
0xcf018600, 0xcf018600,
0x02b50022, 0x02b50022,
0x0f24b604,
0x01c90080,
0xbd0002f6,
0x0c308e04, 0x0c308e04,
0xbd24bd50, 0xbd24bd50,
/* 0x0377: init_unk_loop */ /* 0x0383: init_unk_loop */
0x7e44bd34, 0x7e44bd34,
0xb0000065, 0xb0000065,
0x0bf400f6, 0x0bf400f6,
0xbb010f0e, 0xbb010f0e,
0x4ffd04f2, 0x4ffd04f2,
0x0130b605, 0x0130b605,
/* 0x038c: init_unk_next */ /* 0x0398: init_unk_next */
0xb60120b6, 0xb60120b6,
0x26b004e0, 0x26b004e0,
0xe21bf401, 0xe21bf401,
/* 0x0398: init_unk_done */ /* 0x03a4: init_unk_done */
0xb50703b5, 0xb50703b5,
0x00820804, 0x00820804,
0x22cf0201, 0x22cf0201,
...@@ -338,121 +341,118 @@ uint32_t gk208_grgpc_code[] = { ...@@ -338,121 +341,118 @@ uint32_t gk208_grgpc_code[] = {
0xb60824b6, 0xb60824b6,
0x2fb20834, 0x2fb20834,
0x0002687e, 0x0002687e,
0x80003fbb, 0xbb002fbb,
0xf6020100, 0x0080003f,
0x04bd0003, 0x03f60201,
0x29f024bd, 0xbd04bd00,
0x3000801f, 0x1f29f024,
0x0002f602, 0x02300080,
/* 0x0436: main */ 0xbd0002f6,
0x31f404bd, /* 0x0445: main */
0x0028f400, 0x0031f404,
0x377e240d, 0x0d0028f4,
0x01f40000, 0x00377e24,
0x04e4b0f4, 0xf401f400,
0xfe1d18f4, 0xf404e4b0,
0x06020181, 0x81fe1d18,
0x12fd20bd, 0xbd060201,
0x01e4b604, 0x0412fd20,
0xfe051efd, 0xfd01e4b6,
0x097e0018, 0x18fe051e,
0x0ef40005, 0x05187e00,
/* 0x0465: main_not_ctx_xfer */ 0xd40ef400,
0x10ef94d4, /* 0x0474: main_not_ctx_xfer */
0x7e01f5f0, 0xf010ef94,
0xf40002f8, 0xf87e01f5,
/* 0x0472: ih */ 0x0ef40002,
0x80f9c70e, /* 0x0481: ih */
0xf90188fe, 0xfe80f9c7,
0xf990f980, 0x80f90188,
0xf9b0f9a0, 0xa0f990f9,
0xf9e0f9d0, 0xd0f9b0f9,
0x4a04bdf0, 0xf0f9e0f9,
0xaacf0200, 0x004a04bd,
0x04abc400, 0x00aacf02,
0x0d1f0bf4, 0xf404abc4,
0x1a004e24, 0x240d1f0b,
0x4f00eecf, 0xcf1a004e,
0xffcf1900, 0x004f00ee,
0x00047e00, 0x00ffcf19,
0x40010e00, 0x0000047e,
0x0ef61d00, 0x0040010e,
/* 0x04af: ih_no_fifo */ 0x000ef61d,
0x4004bd00, /* 0x04be: ih_no_fifo */
0x0af60100, 0x004004bd,
0xfc04bd00, 0x000af601,
0xfce0fcf0, 0xf0fc04bd,
0xfcb0fcd0, 0xd0fce0fc,
0xfc90fca0, 0xa0fcb0fc,
0x0088fe80, 0x80fc90fc,
0x32f480fc, 0xfc0088fe,
/* 0x04cf: hub_barrier_done */ 0x0032f480,
0x0f01f800, /* 0x04de: hub_barrier_done */
0x040e9801, 0x010f01f8,
0xb204febb, 0xbb040e98,
0x94188eff, 0xffb204fe,
0x008f7e40, 0x4094188e,
/* 0x04e3: ctx_redswitch */ 0x00008f7e,
0x0f00f800, /* 0x04f2: ctx_redswitch */
0x85008020, 0x200f00f8,
0x01850080,
0xbd000ff6,
/* 0x04ff: ctx_redswitch_delay */
0xb6080e04,
0x1bf401e2,
0x00f5f1fd,
0x00f5f108,
0x85008002,
0x000ff601, 0x000ff601,
0x080e04bd, 0x00f804bd,
/* 0x04f0: ctx_redswitch_delay */ /* 0x0518: ctx_xfer */
0xf401e2b6, 0x02810080,
0xf5f1fd1b, 0xbd000ff6,
0xf5f10800, 0x0711f404,
0x00800200, 0x0004f27e,
0x0ff60185, /* 0x0528: ctx_xfer_not_load */
0xf804bd00, 0x0002167e,
/* 0x0509: ctx_xfer */ 0xfc8024bd,
0x81008000, 0x02f60247,
0x000ff602,
0x11f404bd,
0x04e37e07,
/* 0x0519: ctx_xfer_not_load */
0x02167e00,
0x8024bd00,
0xf60247fc,
0x04bd0002,
0xb6012cf0,
0xfc800320,
0x02f6024a,
0xf004bd00, 0xf004bd00,
0xa5f001ac, 0x20b6012c,
0x00008b02, 0x4afc8003,
0x040c9850, 0x0002f602,
0xbb0fc4b6, 0xacf004bd,
0x0c9800bc, 0x02a5f001,
0x010d9800, 0x5000008b,
0x3d7e000e,
0xacf00001,
0x40008b01,
0x040c9850,
0xbb0fc4b6,
0x0c9800bc,
0x020d9801,
0x4e060f98,
0x3d7e0800,
0xacf00001,
0x04a5f001,
0x5030008b,
0xb6040c98, 0xb6040c98,
0xbcbb0fc4, 0xbcbb0fc4,
0x020c9800, 0x000c9800,
0x98030d98, 0x0e010d98,
0x004e080f, 0x013d7e00,
0x013d7e02, 0x01acf000,
0x020a7e00, 0x5040008b,
0x0601f400, 0xb6040c98,
/* 0x05a3: ctx_xfer_post */ 0xbcbb0fc4,
0x7e0712f4, 0x010c9800,
/* 0x05a7: ctx_xfer_done */ 0x98020d98,
0x7e000227, 0x004e060f,
0xf80004cf, 0x013d7e08,
0x00000000, 0x01acf000,
0x00000000, 0x8b04a5f0,
0x00000000, 0x98503000,
0x00000000, 0xc4b6040c,
0x00bcbb0f,
0x98020c98,
0x0f98030d,
0x02004e08,
0x00013d7e,
0x00020a7e,
0xf40601f4,
/* 0x05b2: ctx_xfer_post */
0x277e0712,
/* 0x05b6: ctx_xfer_done */
0xde7e0002,
0x00f80004,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5
View file @ 665ae581
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 #define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002
#define CHIPSET GK208 #define CHIPSET GM107
#include "macros.fuc" #include "macros.fuc"
.section #gm107_grgpc_data .section #gm107_grgpc_data
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h
View file @ 665ae581
...@@ -41,7 +41,7 @@ uint32_t gm107_grgpc_data[] = { ...@@ -41,7 +41,7 @@ uint32_t gm107_grgpc_data[] = {
}; };
uint32_t gm107_grgpc_code[] = { uint32_t gm107_grgpc_code[] = {
0x03140ef5, 0x03410ef5,
/* 0x0004: queue_put */ /* 0x0004: queue_put */
0x9800d898, 0x9800d898,
0x86f001d9, 0x86f001d9,
...@@ -268,187 +268,319 @@ uint32_t gm107_grgpc_code[] = { ...@@ -268,187 +268,319 @@ uint32_t gm107_grgpc_code[] = {
0x409c1c8e, 0x409c1c8e,
0x00008f7e, 0x00008f7e,
0x00f8e0fc, 0x00f8e0fc,
/* 0x0314: init */ /* 0x0314: tpc_strand_wait */
0x004104bd, 0x94bd90f9,
0x0011cf42, 0x800a99f0,
0x010911e7, 0xf6023700,
0xfe0814b6, 0x04bd0009,
0x02020014, /* 0x0324: tpc_strand_busy */
0xf6120040, 0x033f0089,
0x04bd0002, 0xb30099cf,
0xfe047241, 0xbdf90094,
0x00400010, 0x0a99f094,
0x0000f607, 0x02170080,
0x040204bd, 0xbd0009f6,
0xf6040040, 0xf890fc04,
0x04bd0002, /* 0x0341: init */
0x821031f4, 0x4104bd00,
0xcf018200, 0x11cf4200,
0x01030022, 0x0911e700,
0xbb1f24f0, 0x0814b601,
0x32b60432, 0x020014fe,
0x0502b501, 0x12004002,
0x820603b5, 0xbd0002f6,
0xcf018600, 0x05b04104,
0x02b50022, 0x400010fe,
0x0c308e04, 0x00f60700,
0xbd24bd50, 0x0204bd00,
/* 0x0377: init_unk_loop */ 0x04004004,
0x7e44bd34, 0xbd0002f6,
0xb0000065, 0x1031f404,
0x0bf400f6, 0x01820082,
0xbb010f0e, 0x030022cf,
0x4ffd04f2, 0x1f24f001,
0x0130b605, 0xb60432bb,
/* 0x038c: init_unk_next */ 0x02b50132,
0xb60120b6, 0x0603b505,
0x26b004e0, 0x01860082,
0xe21bf402, 0xb50022cf,
/* 0x0398: init_unk_done */ 0x24b60402,
0xb50703b5, 0xc900800f,
0x00820804, 0x0002f601,
0x22cf0201, 0x308e04bd,
0x9534bd00, 0x24bd500c,
0x00800825, 0x44bd34bd,
0x05f601c0, /* 0x03b0: init_unk_loop */
0x8004bd00, 0x0000657e,
0xf601c100, 0xf400f6b0,
0x010f0e0b,
0xfd04f2bb,
0x30b6054f,
/* 0x03c5: init_unk_next */
0x0120b601,
0xb004e0b6,
0x1bf40226,
/* 0x03d1: init_unk_done */
0x0703b5e2,
0x820804b5,
0xcf020100,
0x34bd0022,
0x80082595,
0xf601c000,
0x04bd0005, 0x04bd0005,
0x98000e98, 0x01c10080,
0x207e010f, 0xbd0005f6,
0x2fbb0001, 0x000e9804,
0x7e010f98,
0xbb000120,
0x3fbb002f,
0x010e9800,
0x7e020f98,
0x98000120,
0xeffd050e,
0x002ebb00,
0x98003ebb,
0x0f98020e,
0x01207e03,
0x070e9800,
0xbb00effd,
0x3ebb002e,
0x0235b600,
0x01d30080,
0xbd0003f6,
0x0825b604,
0xb60635b6,
0x30b60120,
0x0824b601,
0xb20834b6,
0x02687e2f,
0x002fbb00,
0x0f003fbb,
0x8effb23f,
0xf0501d60,
0x8f7e01e5,
0x0c0f0000,
0xa88effb2,
0xe5f0501d,
0x008f7e01,
0x03147e00,
0xb23f0f00,
0x1d608eff,
0x01e5f050,
0x00008f7e,
0xffb2000f,
0x501d9c8e,
0x7e01e5f0,
0x0f00008f,
0x03147e01,
0x8effb200,
0xf0501da8,
0x8f7e01e5,
0xff0f0000,
0x988effb2,
0xe5f0501d,
0x008f7e01,
0xb2020f00,
0x1da88eff,
0x01e5f050,
0x00008f7e,
0x0003147e,
0x85050498,
0x98504000,
0x64b60406,
0x0056bb0f,
/* 0x04e0: tpc_strand_init_tpc_loop */
0x05705eb8,
0x00657e00,
0xbdf6b200,
/* 0x04ed: tpc_strand_init_idx_loop */
0x605eb874,
0x7fb20005,
0x00008f7e,
0x05885eb8,
0x082f9500,
0x00008f7e,
0x058c5eb8,
0x082f9500,
0x00008f7e,
0x05905eb8,
0x00657e00,
0x06f5b600,
0xb601f0b6,
0x2fbb08f4,
0x003fbb00, 0x003fbb00,
0x98010e98, 0xb60170b6,
0x207e020f, 0x1bf40162,
0x0e980001, 0x0050b7bf,
0x00effd05, 0x0142b608,
0xbb002ebb, 0x0fa81bf4,
0x0e98003e, 0x8effb23f,
0x030f9802, 0xf0501d60,
0x0001207e, 0x8f7e01e5,
0xfd070e98, 0x0d0f0000,
0x2ebb00ef, 0xa88effb2,
0x003ebb00, 0xe5f0501d,
0x800235b6, 0x008f7e01,
0xf601d300, 0x03147e00,
0x04bd0003, 0x01008000,
0xb60825b6, 0x0003f602,
0x20b60635, 0x24bd04bd,
0x0130b601, 0x801f29f0,
0xb60824b6, 0xf6023000,
0x2fb20834,
0x0002687e,
0x80003fbb,
0xf6020100,
0x04bd0003,
0x29f024bd,
0x3000801f,
0x0002f602,
/* 0x0436: main */
0x31f404bd,
0x0028f400,
0x377e240d,
0x01f40000,
0x04e4b0f4,
0xfe1d18f4,
0x06020181,
0x12fd20bd,
0x01e4b604,
0xfe051efd,
0x097e0018,
0x0ef40005,
/* 0x0465: main_not_ctx_xfer */
0x10ef94d4,
0x7e01f5f0,
0xf40002f8,
/* 0x0472: ih */
0x80f9c70e,
0xf90188fe,
0xf990f980,
0xf9b0f9a0,
0xf9e0f9d0,
0x4a04bdf0,
0xaacf0200,
0x04abc400,
0x0d1f0bf4,
0x1a004e24,
0x4f00eecf,
0xffcf1900,
0x00047e00,
0x40010e00,
0x0ef61d00,
/* 0x04af: ih_no_fifo */
0x4004bd00,
0x0af60100,
0xfc04bd00,
0xfce0fcf0,
0xfcb0fcd0,
0xfc90fca0,
0x0088fe80,
0x32f480fc,
/* 0x04cf: hub_barrier_done */
0x0f01f800,
0x040e9801,
0xb204febb,
0x94188eff,
0x008f7e40,
/* 0x04e3: ctx_redswitch */
0x0f00f800,
0x85008020,
0x000ff601,
0x080e04bd,
/* 0x04f0: ctx_redswitch_delay */
0xf401e2b6,
0xf5f1fd1b,
0xf5f10800,
0x00800200,
0x0ff60185,
0xf804bd00,
/* 0x0509: ctx_xfer */
0x81008000,
0x000ff602,
0x11f404bd,
0x04e37e07,
/* 0x0519: ctx_xfer_not_load */
0x02167e00,
0x8024bd00,
0xf60247fc,
0x04bd0002, 0x04bd0002,
0xb6012cf0, /* 0x0574: main */
0xfc800320, 0xf40031f4,
0x02f6024a, 0x240d0028,
0x0000377e,
0xb0f401f4,
0x18f404e4,
0x0181fe1d,
0x20bd0602,
0xb60412fd,
0x1efd01e4,
0x0018fe05,
0x0006477e,
/* 0x05a3: main_not_ctx_xfer */
0x94d40ef4,
0xf5f010ef,
0x02f87e01,
0xc70ef400,
/* 0x05b0: ih */
0x88fe80f9,
0xf980f901,
0xf9a0f990,
0xf9d0f9b0,
0xbdf0f9e0,
0x02004a04,
0xc400aacf,
0x0bf404ab,
0x4e240d1f,
0xeecf1a00,
0x19004f00,
0x7e00ffcf,
0x0e000004,
0x1d004001,
0xbd000ef6,
/* 0x05ed: ih_no_fifo */
0x01004004,
0xbd000af6,
0xfcf0fc04,
0xfcd0fce0,
0xfca0fcb0,
0xfe80fc90,
0x80fc0088,
0xf80032f4,
/* 0x060d: hub_barrier_done */
0x98010f01,
0xfebb040e,
0x8effb204,
0x7e409418,
0xf800008f,
/* 0x0621: ctx_redswitch */
0x80200f00,
0xf6018500,
0x04bd000f,
/* 0x062e: ctx_redswitch_delay */
0xe2b6080e,
0xfd1bf401,
0x0800f5f1,
0x0200f5f1,
0x01850080,
0xbd000ff6,
/* 0x0647: ctx_xfer */
0x8000f804,
0xf6028100,
0x04bd000f,
0xc48effb2,
0xe5f0501d,
0x008f7e01,
0x0711f400,
0x0006217e,
/* 0x0664: ctx_xfer_not_load */
0x0002167e,
0xfc8024bd,
0x02f60247,
0xf004bd00, 0xf004bd00,
0x20b6012c,
0x4afc8003,
0x0002f602,
0x0c0f04bd,
0xa88effb2,
0xe5f0501d,
0x008f7e01,
0x03147e00,
0xb23f0f00,
0x1d608eff,
0x01e5f050,
0x00008f7e,
0xffb2000f,
0x501d9c8e,
0x7e01e5f0,
0x0f00008f,
0x03147e01,
0x01fcf000,
0xb203f0b6,
0x1da88eff,
0x01e5f050,
0x00008f7e,
0xf001acf0,
0x008b02a5,
0x0c985000,
0x0fc4b604,
0x9800bcbb,
0x0d98000c,
0x7e000e01,
0xf000013d,
0x008b01ac,
0x0c985040,
0x0fc4b604,
0x9800bcbb,
0x0d98010c,
0x060f9802,
0x7e08004e,
0xf000013d,
0xa5f001ac, 0xa5f001ac,
0x00008b02, 0x30008b04,
0x040c9850, 0x040c9850,
0xbb0fc4b6, 0xbb0fc4b6,
0x0c9800bc, 0x0c9800bc,
0x010d9800, 0x030d9802,
0x3d7e000e, 0x4e080f98,
0xacf00001, 0x3d7e0200,
0x40008b01, 0x0a7e0001,
0x040c9850, 0x147e0002,
0xbb0fc4b6, 0x01f40003,
0x0c9800bc, 0x1a12f406,
0x020d9801, /* 0x073c: ctx_xfer_post */
0x4e060f98, 0x0002277e,
0x3d7e0800, 0xffb20d0f,
0xacf00001, 0x501da88e,
0x04a5f001, 0x7e01e5f0,
0x5030008b, 0x7e00008f,
0xb6040c98, /* 0x0753: ctx_xfer_done */
0xbcbb0fc4, 0x7e000314,
0x020c9800, 0xf800060d,
0x98030d98, 0x00000000,
0x004e080f, 0x00000000,
0x013d7e02, 0x00000000,
0x020a7e00, 0x00000000,
0x0601f400, 0x00000000,
/* 0x05a3: ctx_xfer_post */ 0x00000000,
0x7e0712f4, 0x00000000,
/* 0x05a7: ctx_xfer_done */ 0x00000000,
0x7e000227, 0x00000000,
0xf80004cf, 0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/macros.fuc
View file @ 665ae581
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#define GK100 0xe0 #define GK100 0xe0
#define GK110 0xf0 #define GK110 0xf0
#define GK208 0x108 #define GK208 0x108
#define GM107 0x117
#define NV_PGRAPH_TRAPPED_ADDR 0x400704 #define NV_PGRAPH_TRAPPED_ADDR 0x400704
#define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 #define NV_PGRAPH_TRAPPED_DATA_LO 0x400708
...@@ -79,7 +80,9 @@ ...@@ -79,7 +80,9 @@
#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718 #define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718
#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c #define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c
#define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720 #define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720
#define NV_PGRAPH_FECS_MMIO_BASE 0x409724
#define NV_PGRAPH_FECS_MMIO_CTRL 0x409728 #define NV_PGRAPH_FECS_MMIO_CTRL 0x409728
#define NV_PGRAPH_FECS_MMIO_CTRL_BASE_ENABLE 0x00000001
#define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c #define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c
#define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730 #define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730
#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c
...@@ -147,6 +150,11 @@ ...@@ -147,6 +150,11 @@
#define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618 #define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700 #define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704 #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704
#define NV_PGRAPH_GPCX_GPCCS_MMIO_BASE 0x41a724
#define NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL 0x41a728
#define NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE 0x00000001
#define NV_PGRAPH_GPCX_GPCCS_MMIO_RDVAL 0x41a72c
#define NV_PGRAPH_GPCX_GPCCS_MMIO_WRVAL 0x41a730
#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c
#if CHIPSET < GK110 #if CHIPSET < GK110
#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800)
...@@ -164,6 +172,29 @@ ...@@ -164,6 +172,29 @@
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003 #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004 #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04 #define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04
#define NV_PGRAPH_GPCX_GPCCS_TPC_STATUS 0x41acfc
#define NV_PGRAPH_GPC0_TPC0 0x504000
#define NV_PGRAPH_GPC0_TPC0__SIZE 0x000800
#define NV_PGRAPH_GPC0_TPCX_STRAND_INDEX 0x501d60
#define NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL 0x0000003f
#define NV_PGRAPH_GPC0_TPCX_STRAND_DATA 0x501d98
#define NV_PGRAPH_GPC0_TPCX_STRAND_SELECT 0x501d9c
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD 0x501da8
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SEEK 0x00000001
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_GET_INFO 0x00000002
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_SAVE 0x00000003
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_LOAD 0x00000004
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE 0x0000000c
#define NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE 0x0000000d
#define NV_PGRAPH_GPC0_TPCX_STRAND_MEM_BASE 0x501dc4
#define NV_TPC_STRAND_INDEX 0x560
#define NV_TPC_STRAND_CNT 0x570
#define NV_TPC_STRAND_SAVE_SWBASE 0x588
#define NV_TPC_STRAND_LOAD_SWBASE 0x58c
#define NV_TPC_STRAND_WORDS 0x590
#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2)
...@@ -178,6 +209,7 @@ ...@@ -178,6 +209,7 @@
#define T_SAVE 7 #define T_SAVE 7
#define T_LCHAN 8 #define T_LCHAN 8
#define T_LCTXH 9 #define T_LCTXH 9
#define T_STRTPC 10
#if CHIPSET < GK208 #if CHIPSET < GK208
#define imm32(reg,val) /* #define imm32(reg,val) /*
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View file @ 665ae581
...@@ -236,7 +236,7 @@ static int ...@@ -236,7 +236,7 @@ static int
gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
void *pdata, u32 size) void *pdata, u32 size)
{ {
struct gf100_gr_priv *priv = (void *)nv_engine(object); struct gf100_gr_priv *priv = (void *)object->engine;
if (size >= sizeof(u32)) { if (size >= sizeof(u32)) {
u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
nv_wr32(priv, 0x419e44, data); nv_wr32(priv, 0x419e44, data);
...@@ -260,8 +260,8 @@ gf100_gr_90c0_omthds[] = { ...@@ -260,8 +260,8 @@ gf100_gr_90c0_omthds[] = {
struct nvkm_oclass struct nvkm_oclass
gf100_gr_sclass[] = { gf100_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0x9039, &nvkm_object_ofuncs }, { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs },
{ FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{} {}
...@@ -1097,12 +1097,26 @@ gf100_gr_intr(struct nvkm_subdev *subdev) ...@@ -1097,12 +1097,26 @@ gf100_gr_intr(struct nvkm_subdev *subdev)
u32 subc = (addr & 0x00070000) >> 16; u32 subc = (addr & 0x00070000) >> 16;
u32 data = nv_rd32(priv, 0x400708); u32 data = nv_rd32(priv, 0x400708);
u32 code = nv_rd32(priv, 0x400110); u32 code = nv_rd32(priv, 0x400110);
u32 class = nv_rd32(priv, 0x404200 + (subc * 4)); u32 class;
int chid; int chid;
if (nv_device(priv)->card_type < NV_E0 || subc < 4)
class = nv_rd32(priv, 0x404200 + (subc * 4));
else
class = 0x0000;
engctx = nvkm_engctx_get(engine, inst); engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx); chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000001) {
/*
* notifier interrupt, only needed for cyclestats
* can be safely ignored
*/
nv_wr32(priv, 0x400100, 0x00000001);
stat &= ~0x00000001;
}
if (stat & 0x00000010) { if (stat & 0x00000010) {
handle = nvkm_handle_get_class(engctx, class); handle = nvkm_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) { if (!handle || nv_call(handle->object, mthd, data)) {
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View file @ 665ae581
...@@ -124,10 +124,12 @@ void gf100_gr_dtor(struct nvkm_object *); ...@@ -124,10 +124,12 @@ void gf100_gr_dtor(struct nvkm_object *);
int gf100_gr_init(struct nvkm_object *); int gf100_gr_init(struct nvkm_object *);
void gf100_gr_zbc_init(struct gf100_gr_priv *); void gf100_gr_zbc_init(struct gf100_gr_priv *);
int gk104_gr_fini(struct nvkm_object *, bool); int gk104_gr_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
int gk104_gr_init(struct nvkm_object *); int gk104_gr_init(struct nvkm_object *);
int gk110_gr_fini(struct nvkm_object *, bool); int gm204_gr_init(struct nvkm_object *);
extern struct nvkm_ofuncs gf100_fermi_ofuncs; extern struct nvkm_ofuncs gf100_fermi_ofuncs;
...@@ -136,6 +138,7 @@ extern struct nvkm_omthds gf100_gr_9097_omthds[]; ...@@ -136,6 +138,7 @@ extern struct nvkm_omthds gf100_gr_9097_omthds[];
extern struct nvkm_omthds gf100_gr_90c0_omthds[]; extern struct nvkm_omthds gf100_gr_90c0_omthds[];
extern struct nvkm_oclass gf110_gr_sclass[]; extern struct nvkm_oclass gf110_gr_sclass[];
extern struct nvkm_oclass gk110_gr_sclass[]; extern struct nvkm_oclass gk110_gr_sclass[];
extern struct nvkm_oclass gm204_gr_sclass[];
struct gf100_gr_init { struct gf100_gr_init {
u32 addr; u32 addr;
...@@ -247,4 +250,17 @@ extern const struct gf100_gr_init gk110_gr_init_tex_0[]; ...@@ -247,4 +250,17 @@ extern const struct gf100_gr_init gk110_gr_init_tex_0[];
extern const struct gf100_gr_init gk110_gr_init_sm_0[]; extern const struct gf100_gr_init gk110_gr_init_sm_0[];
extern const struct gf100_gr_init gk208_gr_init_gpc_unk_0[]; extern const struct gf100_gr_init gk208_gr_init_gpc_unk_0[];
extern const struct gf100_gr_init gm107_gr_init_scc_0[];
extern const struct gf100_gr_init gm107_gr_init_prop_0[];
extern const struct gf100_gr_init gm107_gr_init_setup_1[];
extern const struct gf100_gr_init gm107_gr_init_zcull_0[];
extern const struct gf100_gr_init gm107_gr_init_gpc_unk_1[];
extern const struct gf100_gr_init gm107_gr_init_tex_0[];
extern const struct gf100_gr_init gm107_gr_init_l1c_0[];
extern const struct gf100_gr_init gm107_gr_init_wwdx_0[];
extern const struct gf100_gr_init gm107_gr_init_cbm_0[];
void gm107_gr_init_bios(struct gf100_gr_priv *);
extern const struct gf100_gr_pack gm204_gr_pack_mmio[];
#endif #endif
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
View file @ 665ae581
...@@ -32,8 +32,8 @@ ...@@ -32,8 +32,8 @@
static struct nvkm_oclass static struct nvkm_oclass
gf108_gr_sclass[] = { gf108_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0x9039, &nvkm_object_ofuncs }, { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs },
{ FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
View file @ 665ae581
...@@ -32,8 +32,8 @@ ...@@ -32,8 +32,8 @@
struct nvkm_oclass struct nvkm_oclass
gf110_gr_sclass[] = { gf110_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0x9039, &nvkm_object_ofuncs }, { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs },
{ FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ FERMI_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { FERMI_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View file @ 665ae581
...@@ -34,8 +34,8 @@ ...@@ -34,8 +34,8 @@
static struct nvkm_oclass static struct nvkm_oclass
gk104_gr_sclass[] = { gk104_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0xa040, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs },
{ KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{} {}
...@@ -310,6 +310,17 @@ gk104_gr_init(struct nvkm_object *object) ...@@ -310,6 +310,17 @@ gk104_gr_init(struct nvkm_object *object)
return gf100_gr_init_ctxctl(priv); return gf100_gr_init_ctxctl(priv);
} }
int
gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_pmu *pmu = nvkm_pmu(parent);
if (pmu)
pmu->pgob(pmu, false);
return gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
}
#include "fuc/hubgk104.fuc3.h" #include "fuc/hubgk104.fuc3.h"
static struct gf100_gr_ucode static struct gf100_gr_ucode
...@@ -334,7 +345,7 @@ struct nvkm_oclass * ...@@ -334,7 +345,7 @@ struct nvkm_oclass *
gk104_gr_oclass = &(struct gf100_gr_oclass) { gk104_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xe4), .base.handle = NV_ENGINE(GR, 0xe4),
.base.ofuncs = &(struct nvkm_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_ctor, .ctor = gk104_gr_ctor,
.dtor = gf100_gr_dtor, .dtor = gf100_gr_dtor,
.init = gk104_gr_init, .init = gk104_gr_init,
.fini = _nvkm_gr_fini, .fini = _nvkm_gr_fini,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View file @ 665ae581
...@@ -34,8 +34,8 @@ ...@@ -34,8 +34,8 @@
struct nvkm_oclass struct nvkm_oclass
gk110_gr_sclass[] = { gk110_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0xa140, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs },
{ KEPLER_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { KEPLER_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ KEPLER_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, { KEPLER_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{} {}
...@@ -173,43 +173,6 @@ gk110_gr_pack_mmio[] = { ...@@ -173,43 +173,6 @@ gk110_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions * PGRAPH engine/subdev functions
******************************************************************************/ ******************************************************************************/
int
gk110_gr_fini(struct nvkm_object *object, bool suspend)
{
struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
} magic[] = {
{ 0x020520, 0xfffffffc },
{ 0x020524, 0xfffffffe },
{ 0x020524, 0xfffffffc },
{ 0x020524, 0xfffffff8 },
{ 0x020524, 0xffffffe0 },
{ 0x020530, 0xfffffffe },
{ 0x02052c, 0xfffffffa },
{ 0x02052c, 0xfffffff0 },
{ 0x02052c, 0xffffffc0 },
{ 0x02052c, 0xffffff00 },
{ 0x02052c, 0xfffffc00 },
{ 0x02052c, 0xfffcfc00 },
{ 0x02052c, 0xfff0fc00 },
{ 0x02052c, 0xff80fc00 },
{ 0x020528, 0xfffffffe },
{ 0x020528, 0xfffffffc },
};
int i;
nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
for (i = 0; i < ARRAY_SIZE(magic); i++) {
nv_wr32(priv, magic[i].addr, magic[i].data);
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
return nvkm_gr_fini(&priv->base, suspend);
}
#include "fuc/hubgk110.fuc3.h" #include "fuc/hubgk110.fuc3.h"
struct gf100_gr_ucode struct gf100_gr_ucode
...@@ -234,10 +197,10 @@ struct nvkm_oclass * ...@@ -234,10 +197,10 @@ struct nvkm_oclass *
gk110_gr_oclass = &(struct gf100_gr_oclass) { gk110_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf0), .base.handle = NV_ENGINE(GR, 0xf0),
.base.ofuncs = &(struct nvkm_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_ctor, .ctor = gk104_gr_ctor,
.dtor = gf100_gr_dtor, .dtor = gf100_gr_dtor,
.init = gk104_gr_init, .init = gk104_gr_init,
.fini = gk110_gr_fini, .fini = _nvkm_gr_fini,
}, },
.cclass = &gk110_grctx_oclass, .cclass = &gk110_grctx_oclass,
.sclass = gk110_gr_sclass, .sclass = gk110_gr_sclass,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View file @ 665ae581
...@@ -102,10 +102,10 @@ struct nvkm_oclass * ...@@ -102,10 +102,10 @@ struct nvkm_oclass *
gk110b_gr_oclass = &(struct gf100_gr_oclass) { gk110b_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf1), .base.handle = NV_ENGINE(GR, 0xf1),
.base.ofuncs = &(struct nvkm_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_ctor, .ctor = gk104_gr_ctor,
.dtor = gf100_gr_dtor, .dtor = gf100_gr_dtor,
.init = gk104_gr_init, .init = gk104_gr_init,
.fini = gk110_gr_fini, .fini = _nvkm_gr_fini,
}, },
.cclass = &gk110b_grctx_oclass, .cclass = &gk110b_grctx_oclass,
.sclass = gk110_gr_sclass, .sclass = gk110_gr_sclass,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
View file @ 665ae581
...@@ -34,10 +34,10 @@ ...@@ -34,10 +34,10 @@
static struct nvkm_oclass static struct nvkm_oclass
gk208_gr_sclass[] = { gk208_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0xa140, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs },
{ KEPLER_B, &gf100_fermi_ofuncs }, { KEPLER_B, &gf100_fermi_ofuncs },
{ 0xa1c0, &nvkm_object_ofuncs }, { KEPLER_COMPUTE_B, &nvkm_object_ofuncs },
{} {}
}; };
...@@ -152,43 +152,6 @@ gk208_gr_pack_mmio[] = { ...@@ -152,43 +152,6 @@ gk208_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions * PGRAPH engine/subdev functions
******************************************************************************/ ******************************************************************************/
static int
gk208_gr_fini(struct nvkm_object *object, bool suspend)
{
struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
} magic[] = {
{ 0x020520, 0xfffffffc },
{ 0x020524, 0xfffffffe },
{ 0x020524, 0xfffffffc },
{ 0x020524, 0xfffffff8 },
{ 0x020524, 0xffffffe0 },
{ 0x020530, 0xfffffffe },
{ 0x02052c, 0xfffffffa },
{ 0x02052c, 0xfffffff0 },
{ 0x02052c, 0xffffffc0 },
{ 0x02052c, 0xffffff00 },
{ 0x02052c, 0xfffffc00 },
{ 0x02052c, 0xfffcfc00 },
{ 0x02052c, 0xfff0fc00 },
{ 0x02052c, 0xff80fc00 },
{ 0x020528, 0xfffffffe },
{ 0x020528, 0xfffffffc },
};
int i;
nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
for (i = 0; i < ARRAY_SIZE(magic); i++) {
nv_wr32(priv, magic[i].addr, magic[i].data);
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
return nvkm_gr_fini(&priv->base, suspend);
}
#include "fuc/hubgk208.fuc5.h" #include "fuc/hubgk208.fuc5.h"
static struct gf100_gr_ucode static struct gf100_gr_ucode
...@@ -213,10 +176,10 @@ struct nvkm_oclass * ...@@ -213,10 +176,10 @@ struct nvkm_oclass *
gk208_gr_oclass = &(struct gf100_gr_oclass) { gk208_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x08), .base.handle = NV_ENGINE(GR, 0x08),
.base.ofuncs = &(struct nvkm_ofuncs) { .base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_ctor, .ctor = gk104_gr_ctor,
.dtor = gf100_gr_dtor, .dtor = gf100_gr_dtor,
.init = gk104_gr_init, .init = gk104_gr_init,
.fini = gk208_gr_fini, .fini = _nvkm_gr_fini,
}, },
.cclass = &gk208_grctx_oclass, .cclass = &gk208_grctx_oclass,
.sclass = gk208_gr_sclass, .sclass = gk208_gr_sclass,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View file @ 665ae581
...@@ -26,8 +26,8 @@ ...@@ -26,8 +26,8 @@
static struct nvkm_oclass static struct nvkm_oclass
gk20a_gr_sclass[] = { gk20a_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0xa040, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs },
{ KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{} {}
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View file @ 665ae581
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
static struct nvkm_oclass static struct nvkm_oclass
gm107_gr_sclass[] = { gm107_gr_sclass[] = {
{ 0x902d, &nvkm_object_ofuncs }, { FERMI_TWOD_A, &nvkm_object_ofuncs },
{ 0xa140, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs },
{ MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, { MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
{ MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{} {}
...@@ -71,7 +71,7 @@ gm107_gr_init_ds_0[] = { ...@@ -71,7 +71,7 @@ gm107_gr_init_ds_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_scc_0[] = { gm107_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000010 }, { 0x40803c, 1, 0x04, 0x00000010 },
{} {}
...@@ -85,14 +85,14 @@ gm107_gr_init_sked_0[] = { ...@@ -85,14 +85,14 @@ gm107_gr_init_sked_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_prop_0[] = { gm107_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 }, { 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 }, { 0x4184a0, 1, 0x04, 0x00000000 },
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_setup_1[] = { gm107_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 }, { 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 }, { 0x4188d0, 1, 0x04, 0x00010000 },
...@@ -100,7 +100,7 @@ gm107_gr_init_setup_1[] = { ...@@ -100,7 +100,7 @@ gm107_gr_init_setup_1[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_zcull_0[] = { gm107_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 }, { 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 }, { 0x418914, 1, 0x04, 0x00000301 },
...@@ -111,7 +111,7 @@ gm107_gr_init_zcull_0[] = { ...@@ -111,7 +111,7 @@ gm107_gr_init_zcull_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_gpc_unk_1[] = { gm107_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 }, { 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 }, { 0x418f00, 1, 0x04, 0x00000400 },
...@@ -134,7 +134,7 @@ gm107_gr_init_tpccs_0[] = { ...@@ -134,7 +134,7 @@ gm107_gr_init_tpccs_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_tex_0[] = { gm107_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 }, { 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 }, { 0x419ab8, 1, 0x04, 0x000000e7 },
...@@ -160,7 +160,7 @@ gm107_gr_init_pe_0[] = { ...@@ -160,7 +160,7 @@ gm107_gr_init_pe_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_l1c_0[] = { gm107_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 }, { 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419cc0, 2, 0x04, 0x00000000 }, { 0x419cc0, 2, 0x04, 0x00000000 },
...@@ -206,14 +206,14 @@ gm107_gr_init_pes_0[] = { ...@@ -206,14 +206,14 @@ gm107_gr_init_pes_0[] = {
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_wwdx_0[] = { gm107_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 }, { 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 }, { 0x41bfdc, 1, 0x04, 0x00000000 },
{} {}
}; };
static const struct gf100_gr_init const struct gf100_gr_init
gm107_gr_init_cbm_0[] = { gm107_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 }, { 0x41becc, 1, 0x04, 0x00000000 },
{} {}
...@@ -291,7 +291,7 @@ gm107_gr_pack_mmio[] = { ...@@ -291,7 +291,7 @@ gm107_gr_pack_mmio[] = {
* PGRAPH engine/subdev functions * PGRAPH engine/subdev functions
******************************************************************************/ ******************************************************************************/
static void void
gm107_gr_init_bios(struct gf100_gr_priv *priv) gm107_gr_init_bios(struct gf100_gr_priv *priv)
{ {
static const struct { static const struct {
...@@ -464,7 +464,7 @@ gm107_gr_oclass = &(struct gf100_gr_oclass) { ...@@ -464,7 +464,7 @@ gm107_gr_oclass = &(struct gf100_gr_oclass) {
.cclass = &gm107_grctx_oclass, .cclass = &gm107_grctx_oclass,
.sclass = gm107_gr_sclass, .sclass = gm107_gr_sclass,
.mmio = gm107_gr_pack_mmio, .mmio = gm107_gr_pack_mmio,
.fecs.ucode = 0 ? &gm107_gr_fecs_ucode : NULL, .fecs.ucode = &gm107_gr_fecs_ucode,
.gpccs.ucode = &gm107_gr_gpccs_ucode, .gpccs.ucode = &gm107_gr_gpccs_ucode,
.ppc_nr = 2, .ppc_nr = 2,
}.base; }.base;
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c 0 → 100644
View file @ 665ae581
This diff is collapsed.
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c 0 → 100644
View file @ 665ae581
/*
* Copyright 2015 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "gf100.h"
#include "ctxgf100.h"
struct nvkm_oclass *
gm206_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x26),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gf100_gr_ctor,
.dtor = gf100_gr_dtor,
.init = gm204_gr_init,
.fini = _nvkm_gr_fini,
},
.cclass = &gm206_grctx_oclass,
.sclass = gm204_gr_sclass,
.mmio = gm204_gr_pack_mmio,
.ppc_nr = 2,
}.base;
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c
View file @ 665ae581
...@@ -52,7 +52,7 @@ acpi_read_fast(void *data, u32 offset, u32 length, struct nvkm_bios *bios) ...@@ -52,7 +52,7 @@ acpi_read_fast(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
u32 start = offset & ~0x00000fff; u32 start = offset & ~0x00000fff;
u32 fetch = limit - start; u32 fetch = limit - start;
if (nvbios_extend(bios, limit) > 0) { if (nvbios_extend(bios, limit) >= 0) {
int ret = nouveau_acpi_get_bios_chunk(bios->data, start, fetch); int ret = nouveau_acpi_get_bios_chunk(bios->data, start, fetch);
if (ret == fetch) if (ret == fetch)
return fetch; return fetch;
...@@ -73,7 +73,7 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios) ...@@ -73,7 +73,7 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
u32 start = offset & ~0xfff; u32 start = offset & ~0xfff;
u32 fetch = 0; u32 fetch = 0;
if (nvbios_extend(bios, limit) > 0) { if (nvbios_extend(bios, limit) >= 0) {
while (start + fetch < limit) { while (start + fetch < limit) {
int ret = nouveau_acpi_get_bios_chunk(bios->data, int ret = nouveau_acpi_get_bios_chunk(bios->data,
start + fetch, start + fetch,
......
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c
View file @ 665ae581
...@@ -29,7 +29,7 @@ struct nvkm_hwsq { ...@@ -29,7 +29,7 @@ struct nvkm_hwsq {
u32 data; u32 data;
struct { struct {
u8 data[512]; u8 data[512];
u8 size; u16 size;
} c; } c;
}; };
......
drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h
View file @ 665ae581
...@@ -11,17 +11,34 @@ struct hwsq { ...@@ -11,17 +11,34 @@ struct hwsq {
struct hwsq_reg { struct hwsq_reg {
int sequence; int sequence;
bool force; bool force;
u32 addr[2]; u32 addr;
u32 stride; /* in bytes */
u32 mask;
u32 data; u32 data;
}; };
static inline struct hwsq_reg
hwsq_stride(u32 addr, u32 stride, u32 mask)
{
return (struct hwsq_reg) {
.sequence = 0,
.force = 0,
.addr = addr,
.stride = stride,
.mask = mask,
.data = 0xdeadbeef,
};
}
static inline struct hwsq_reg static inline struct hwsq_reg
hwsq_reg2(u32 addr1, u32 addr2) hwsq_reg2(u32 addr1, u32 addr2)
{ {
return (struct hwsq_reg) { return (struct hwsq_reg) {
.sequence = 0, .sequence = 0,
.force = 0, .force = 0,
.addr = { addr1, addr2 }, .addr = addr1,
.stride = addr2 - addr1,
.mask = 0x3,
.data = 0xdeadbeef, .data = 0xdeadbeef,
}; };
} }
...@@ -29,7 +46,14 @@ hwsq_reg2(u32 addr1, u32 addr2) ...@@ -29,7 +46,14 @@ hwsq_reg2(u32 addr1, u32 addr2)
static inline struct hwsq_reg static inline struct hwsq_reg
hwsq_reg(u32 addr) hwsq_reg(u32 addr)
{ {
return hwsq_reg2(addr, addr); return (struct hwsq_reg) {
.sequence = 0,
.force = 0,
.addr = addr,
.stride = 0,
.mask = 0x1,
.data = 0xdeadbeef,
};
} }
static inline int static inline int
...@@ -62,18 +86,24 @@ static inline u32 ...@@ -62,18 +86,24 @@ static inline u32
hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
{ {
if (reg->sequence != ram->sequence) if (reg->sequence != ram->sequence)
reg->data = nv_rd32(ram->subdev, reg->addr[0]); reg->data = nv_rd32(ram->subdev, reg->addr);
return reg->data; return reg->data;
} }
static inline void static inline void
hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
{ {
u32 mask, off = 0;
reg->sequence = ram->sequence; reg->sequence = ram->sequence;
reg->data = data; reg->data = data;
if (reg->addr[0] != reg->addr[1])
nvkm_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data); for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) {
nvkm_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data); if (mask & 1)
nvkm_hwsq_wr32(ram->hwsq, reg->addr+off, reg->data);
off += reg->stride;
}
} }
static inline void static inline void
......
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
View file @ 665ae581
...@@ -184,7 +184,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) ...@@ -184,7 +184,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
nv_debug(clk, "setting performance state %d\n", pstatei); nv_debug(clk, "setting performance state %d\n", pstatei);
clk->pstate = pstatei; clk->pstate = pstatei;
if (pfb->ram->calc) { if (pfb->ram && pfb->ram->calc) {
int khz = pstate->base.domain[nv_clk_src_mem]; int khz = pstate->base.domain[nv_clk_src_mem];
do { do {
ret = pfb->ram->calc(pfb, khz); ret = pfb->ram->calc(pfb, khz);
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h
View file @ 665ae581
...@@ -5,7 +5,7 @@ struct nvkm_pll_vals; ...@@ -5,7 +5,7 @@ struct nvkm_pll_vals;
struct nv04_devinit_priv { struct nv04_devinit_priv {
struct nvkm_devinit base; struct nvkm_devinit base;
u8 owner; int owner;
}; };
int nv04_devinit_ctor(struct nvkm_object *, struct nvkm_object *, int nv04_devinit_ctor(struct nvkm_object *, struct nvkm_object *,
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
View file @ 665ae581
...@@ -37,7 +37,6 @@ nvkm-y += nvkm/subdev/fb/ramgt215.o ...@@ -37,7 +37,6 @@ nvkm-y += nvkm/subdev/fb/ramgt215.o
nvkm-y += nvkm/subdev/fb/rammcp77.o nvkm-y += nvkm/subdev/fb/rammcp77.o
nvkm-y += nvkm/subdev/fb/ramgf100.o nvkm-y += nvkm/subdev/fb/ramgf100.o
nvkm-y += nvkm/subdev/fb/ramgk104.o nvkm-y += nvkm/subdev/fb/ramgk104.o
nvkm-y += nvkm/subdev/fb/ramgk20a.o
nvkm-y += nvkm/subdev/fb/ramgm107.o nvkm-y += nvkm/subdev/fb/ramgm107.o
nvkm-y += nvkm/subdev/fb/sddr2.o nvkm-y += nvkm/subdev/fb/sddr2.o
nvkm-y += nvkm/subdev/fb/sddr3.o nvkm-y += nvkm/subdev/fb/sddr3.o
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c
View file @ 665ae581
...@@ -65,5 +65,4 @@ gk20a_fb_oclass = &(struct nvkm_fb_impl) { ...@@ -65,5 +65,4 @@ gk20a_fb_oclass = &(struct nvkm_fb_impl) {
.fini = _nvkm_fb_fini, .fini = _nvkm_fb_fini,
}, },
.memtype = gf100_fb_memtype_valid, .memtype = gf100_fb_memtype_valid,
.ram = &gk20a_ram_oclass,
}.base; }.base;
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
View file @ 665ae581
...@@ -32,7 +32,6 @@ extern struct nvkm_oclass gt215_ram_oclass; ...@@ -32,7 +32,6 @@ extern struct nvkm_oclass gt215_ram_oclass;
extern struct nvkm_oclass mcp77_ram_oclass; extern struct nvkm_oclass mcp77_ram_oclass;
extern struct nvkm_oclass gf100_ram_oclass; extern struct nvkm_oclass gf100_ram_oclass;
extern struct nvkm_oclass gk104_ram_oclass; extern struct nvkm_oclass gk104_ram_oclass;
extern struct nvkm_oclass gk20a_ram_oclass;
extern struct nvkm_oclass gm107_ram_oclass; extern struct nvkm_oclass gm107_ram_oclass;
int nvkm_sddr2_calc(struct nvkm_ram *ram); int nvkm_sddr2_calc(struct nvkm_ram *ram);
......
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c deleted 100644 → 0
View file @ 1d2add28
This diff is collapsed.
drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c
View file @ 665ae581
...@@ -45,10 +45,8 @@ gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ...@@ -45,10 +45,8 @@ gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
ret = nvkm_fuse_create(parent, engine, oclass, &priv); ret = nvkm_fuse_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv); *pobject = nv_object(priv);
if (ret)
return ret;
return 0; return ret;
} }
struct nvkm_oclass struct nvkm_oclass
......
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/Kbuild
View file @ 665ae581
...@@ -2,3 +2,4 @@ nvkm-y += nvkm/subdev/instmem/base.o ...@@ -2,3 +2,4 @@ nvkm-y += nvkm/subdev/instmem/base.o
nvkm-y += nvkm/subdev/instmem/nv04.o nvkm-y += nvkm/subdev/instmem/nv04.o
nvkm-y += nvkm/subdev/instmem/nv40.o nvkm-y += nvkm/subdev/instmem/nv40.o
nvkm-y += nvkm/subdev/instmem/nv50.o nvkm-y += nvkm/subdev/instmem/nv50.o
nvkm-y += nvkm/subdev/instmem/gk20a.o
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c 0 → 100644
View file @ 665ae581
This diff is collapsed.
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c 0 → 100644
View file @ 665ae581
This diff is collapsed.
include/uapi/drm/nouveau_drm.h
View file @ 665ae581
This diff is collapsed.
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