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Commit 66ee1973 authored by Linus Walleij's avatar Linus Walleij
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Merge tag 'sh-pfc-for-v5.5-tag1' of... 

Merge tag 'sh-pfc-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.5

  - Add support for the new RZ/G2N (r8a774b1) SoC,
  - Small fixes and cleanups.
parents fa679767 f846d1e7
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Showing with 504 additions and 445 deletions
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
View file @ 66ee1973
...@@ -18,6 +18,7 @@ Required Properties: ...@@ -18,6 +18,7 @@ Required Properties:
- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller. - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
- "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller. - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
......
drivers/pinctrl/pinctrl-rza2.c
View file @ 66ee1973
...@@ -213,8 +213,8 @@ static const char * const rza2_gpio_names[] = { ...@@ -213,8 +213,8 @@ static const char * const rza2_gpio_names[] = {
"PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7", "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
"PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7", "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
"PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7", "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
"PF_0", "PF_1", "PF_2", "PF_3", "P0_4", "PF_5", "PF_6", "PF_7", "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
"PG_0", "PG_1", "PG_2", "P0_3", "PG_4", "PG_5", "PG_6", "PG_7", "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
"PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7", "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
/* port I does not exist */ /* port I does not exist */
"PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7", "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
......
drivers/pinctrl/pinctrl-rzn1.c
View file @ 66ee1973
...@@ -487,7 +487,7 @@ static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, ...@@ -487,7 +487,7 @@ static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
{ {
struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config); enum pin_config_param param = pinconf_to_config_param(*config);
const u32 reg_drive[4] = { 4, 6, 8, 12 }; static const u32 reg_drive[4] = { 4, 6, 8, 12 };
u32 pull, drive, l1mux; u32 pull, drive, l1mux;
u32 l1, l2, arg = 0; u32 l1, l2, arg = 0;
......
drivers/pinctrl/sh-pfc/Kconfig
View file @ 66ee1973
...@@ -17,6 +17,7 @@ config PINCTRL_SH_PFC ...@@ -17,6 +17,7 @@ config PINCTRL_SH_PFC
select PINCTRL_PFC_R8A7745 if ARCH_R8A7745 select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
select PINCTRL_PFC_R8A77470 if ARCH_R8A77470 select PINCTRL_PFC_R8A77470 if ARCH_R8A77470
select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1 select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
select PINCTRL_PFC_R8A774B1 if ARCH_R8A774B1
select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0 select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
select PINCTRL_PFC_R8A7778 if ARCH_R8A7778 select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
select PINCTRL_PFC_R8A7779 if ARCH_R8A7779 select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
...@@ -86,6 +87,9 @@ config PINCTRL_PFC_R8A77470 ...@@ -86,6 +87,9 @@ config PINCTRL_PFC_R8A77470
config PINCTRL_PFC_R8A774A1 config PINCTRL_PFC_R8A774A1
bool "RZ/G2M pin control support" if COMPILE_TEST bool "RZ/G2M pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774B1
bool "RZ/G2N pin control support" if COMPILE_TEST
config PINCTRL_PFC_R8A774C0 config PINCTRL_PFC_R8A774C0
bool "RZ/G2E pin control support" if COMPILE_TEST bool "RZ/G2E pin control support" if COMPILE_TEST
......
drivers/pinctrl/sh-pfc/Makefile
View file @ 66ee1973
...@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o ...@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A77470) += pfc-r8a77470.o obj-$(CONFIG_PINCTRL_PFC_R8A77470) += pfc-r8a77470.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
......
drivers/pinctrl/sh-pfc/core.c
View file @ 66ee1973
...@@ -518,6 +518,12 @@ static const struct of_device_id sh_pfc_of_table[] = { ...@@ -518,6 +518,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a774a1_pinmux_info, .data = &r8a774a1_pinmux_info,
}, },
#endif #endif
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
{
.compatible = "renesas,pfc-r8a774b1",
.data = &r8a774b1_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774C0 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
{ {
.compatible = "renesas,pfc-r8a774c0", .compatible = "renesas,pfc-r8a774c0",
......
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
View file @ 66ee1973
...@@ -718,7 +718,7 @@ static const u16 pinmux_data[] = { ...@@ -718,7 +718,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0), PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
......
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View file @ 66ee1973
...@@ -726,7 +726,7 @@ static const u16 pinmux_data[] = { ...@@ -726,7 +726,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
......
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View file @ 66ee1973
...@@ -729,7 +729,7 @@ static const u16 pinmux_data[] = { ...@@ -729,7 +729,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
......
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
View file @ 66ee1973
...@@ -732,7 +732,7 @@ static const u16 pinmux_data[] = { ...@@ -732,7 +732,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
...@@ -4378,355 +4378,362 @@ static const unsigned int vin5_clk_mux[] = { ...@@ -4378,355 +4378,362 @@ static const unsigned int vin5_clk_mux[] = {
VI5_CLK_MARK, VI5_CLK_MARK,
}; };
static const struct sh_pfc_pin_group pinmux_groups[] = { static const struct {
SH_PFC_PIN_GROUP(audio_clk_a_a), struct sh_pfc_pin_group common[318];
SH_PFC_PIN_GROUP(audio_clk_a_b), struct sh_pfc_pin_group automotive[30];
SH_PFC_PIN_GROUP(audio_clk_a_c), } pinmux_groups = {
SH_PFC_PIN_GROUP(audio_clk_b_a), .common = {
SH_PFC_PIN_GROUP(audio_clk_b_b), SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_c_a), SH_PFC_PIN_GROUP(audio_clk_a_b),
SH_PFC_PIN_GROUP(audio_clk_c_b), SH_PFC_PIN_GROUP(audio_clk_a_c),
SH_PFC_PIN_GROUP(audio_clkout_a), SH_PFC_PIN_GROUP(audio_clk_b_a),
SH_PFC_PIN_GROUP(audio_clkout_b), SH_PFC_PIN_GROUP(audio_clk_b_b),
SH_PFC_PIN_GROUP(audio_clkout_c), SH_PFC_PIN_GROUP(audio_clk_c_a),
SH_PFC_PIN_GROUP(audio_clkout_d), SH_PFC_PIN_GROUP(audio_clk_c_b),
SH_PFC_PIN_GROUP(audio_clkout1_a), SH_PFC_PIN_GROUP(audio_clkout_a),
SH_PFC_PIN_GROUP(audio_clkout1_b), SH_PFC_PIN_GROUP(audio_clkout_b),
SH_PFC_PIN_GROUP(audio_clkout2_a), SH_PFC_PIN_GROUP(audio_clkout_c),
SH_PFC_PIN_GROUP(audio_clkout2_b), SH_PFC_PIN_GROUP(audio_clkout_d),
SH_PFC_PIN_GROUP(audio_clkout3_a), SH_PFC_PIN_GROUP(audio_clkout1_a),
SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(audio_clkout1_b),
SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(audio_clkout2_a),
SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(audio_clkout2_b),
SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(audio_clkout3_a),
SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ SH_PFC_PIN_GROUP(audio_clkout3_b),
SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_avtp_match_a), SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_mdio),
SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_capture_b), SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(can0_data_a), SH_PFC_PIN_GROUP(avb_avtp_match_a),
SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(avb_avtp_capture_a),
SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(avb_avtp_match_b),
SH_PFC_PIN_GROUP(can_clk), SH_PFC_PIN_GROUP(avb_avtp_capture_b),
SH_PFC_PIN_GROUP(canfd0_data_a), SH_PFC_PIN_GROUP(can0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b), SH_PFC_PIN_GROUP(can0_data_b),
SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(drif0_data1_a), SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(drif0_ctrl_b), SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(drif0_data0_b), SH_PFC_PIN_GROUP(du_rgb666),
SH_PFC_PIN_GROUP(drif0_data1_b), SH_PFC_PIN_GROUP(du_rgb888),
SH_PFC_PIN_GROUP(drif0_ctrl_c), SH_PFC_PIN_GROUP(du_clk_out_0),
SH_PFC_PIN_GROUP(drif0_data0_c), SH_PFC_PIN_GROUP(du_clk_out_1),
SH_PFC_PIN_GROUP(drif0_data1_c), SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(drif1_ctrl_a), SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(drif1_data0_a), SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(drif1_data1_a), SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(drif1_ctrl_b), SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(drif1_data0_b), SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(drif1_data1_b), SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(drif1_ctrl_c), SH_PFC_PIN_GROUP(hscif1_data_a),
SH_PFC_PIN_GROUP(drif1_data0_c), SH_PFC_PIN_GROUP(hscif1_clk_a),
SH_PFC_PIN_GROUP(drif1_data1_c), SH_PFC_PIN_GROUP(hscif1_ctrl_a),
SH_PFC_PIN_GROUP(drif2_ctrl_a), SH_PFC_PIN_GROUP(hscif1_data_b),
SH_PFC_PIN_GROUP(drif2_data0_a), SH_PFC_PIN_GROUP(hscif1_clk_b),
SH_PFC_PIN_GROUP(drif2_data1_a), SH_PFC_PIN_GROUP(hscif1_ctrl_b),
SH_PFC_PIN_GROUP(drif2_ctrl_b), SH_PFC_PIN_GROUP(hscif2_data_a),
SH_PFC_PIN_GROUP(drif2_data0_b), SH_PFC_PIN_GROUP(hscif2_clk_a),
SH_PFC_PIN_GROUP(drif2_data1_b), SH_PFC_PIN_GROUP(hscif2_ctrl_a),
SH_PFC_PIN_GROUP(drif3_ctrl_a), SH_PFC_PIN_GROUP(hscif2_data_b),
SH_PFC_PIN_GROUP(drif3_data0_a), SH_PFC_PIN_GROUP(hscif2_clk_b),
SH_PFC_PIN_GROUP(drif3_data1_a), SH_PFC_PIN_GROUP(hscif2_ctrl_b),
SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(hscif2_data_c),
SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(hscif2_clk_c),
SH_PFC_PIN_GROUP(drif3_data1_b), SH_PFC_PIN_GROUP(hscif2_ctrl_c),
SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(hscif3_data_a),
SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(hscif3_clk),
SH_PFC_PIN_GROUP(du_clk_out_0), SH_PFC_PIN_GROUP(hscif3_ctrl),
SH_PFC_PIN_GROUP(du_clk_out_1), SH_PFC_PIN_GROUP(hscif3_data_b),
SH_PFC_PIN_GROUP(du_sync), SH_PFC_PIN_GROUP(hscif3_data_c),
SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(hscif3_data_d),
SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(hscif4_data_a),
SH_PFC_PIN_GROUP(du_disp), SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(hscif0_ctrl), SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(hscif1_data_a), SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(hscif1_clk_a), SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(hscif1_ctrl_a), SH_PFC_PIN_GROUP(i2c2_a),
SH_PFC_PIN_GROUP(hscif1_data_b), SH_PFC_PIN_GROUP(i2c2_b),
SH_PFC_PIN_GROUP(hscif1_clk_b), SH_PFC_PIN_GROUP(i2c3),
SH_PFC_PIN_GROUP(hscif1_ctrl_b), SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(hscif2_data_a), SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(hscif2_clk_a), SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(hscif2_ctrl_a), SH_PFC_PIN_GROUP(i2c6_c),
SH_PFC_PIN_GROUP(hscif2_data_b), SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(hscif2_clk_b), SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(hscif2_ctrl_b), SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(hscif2_data_c), SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(hscif2_clk_c), SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(hscif2_ctrl_c), SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(hscif3_data_a), SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(hscif3_clk), SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(hscif3_ctrl), SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(hscif3_data_b), SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(hscif3_data_c), SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(hscif3_data_d), SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(hscif4_data_a), SH_PFC_PIN_GROUP(msiof1_clk_a),
SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(msiof1_sync_a),
SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(msiof1_ss1_a),
SH_PFC_PIN_GROUP(hscif4_data_b), SH_PFC_PIN_GROUP(msiof1_ss2_a),
SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(msiof1_txd_a),
SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(msiof1_rxd_a),
SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(msiof1_clk_b),
SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(msiof1_sync_b),
SH_PFC_PIN_GROUP(i2c2_b), SH_PFC_PIN_GROUP(msiof1_ss1_b),
SH_PFC_PIN_GROUP(i2c3), SH_PFC_PIN_GROUP(msiof1_ss2_b),
SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(msiof1_txd_b),
SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(msiof1_rxd_b),
SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(msiof1_clk_c),
SH_PFC_PIN_GROUP(i2c6_c), SH_PFC_PIN_GROUP(msiof1_sync_c),
SH_PFC_PIN_GROUP(intc_ex_irq0), SH_PFC_PIN_GROUP(msiof1_ss1_c),
SH_PFC_PIN_GROUP(intc_ex_irq1), SH_PFC_PIN_GROUP(msiof1_ss2_c),
SH_PFC_PIN_GROUP(intc_ex_irq2), SH_PFC_PIN_GROUP(msiof1_txd_c),
SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(msiof1_rxd_c),
SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(msiof1_clk_d),
SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof1_sync_d),
SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof1_ss1_d),
SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof1_ss2_d),
SH_PFC_PIN_GROUP(msiof0_ss1), SH_PFC_PIN_GROUP(msiof1_txd_d),
SH_PFC_PIN_GROUP(msiof0_ss2), SH_PFC_PIN_GROUP(msiof1_rxd_d),
SH_PFC_PIN_GROUP(msiof0_txd), SH_PFC_PIN_GROUP(msiof1_clk_e),
SH_PFC_PIN_GROUP(msiof0_rxd), SH_PFC_PIN_GROUP(msiof1_sync_e),
SH_PFC_PIN_GROUP(msiof1_clk_a), SH_PFC_PIN_GROUP(msiof1_ss1_e),
SH_PFC_PIN_GROUP(msiof1_sync_a), SH_PFC_PIN_GROUP(msiof1_ss2_e),
SH_PFC_PIN_GROUP(msiof1_ss1_a), SH_PFC_PIN_GROUP(msiof1_txd_e),
SH_PFC_PIN_GROUP(msiof1_ss2_a), SH_PFC_PIN_GROUP(msiof1_rxd_e),
SH_PFC_PIN_GROUP(msiof1_txd_a), SH_PFC_PIN_GROUP(msiof1_clk_f),
SH_PFC_PIN_GROUP(msiof1_rxd_a), SH_PFC_PIN_GROUP(msiof1_sync_f),
SH_PFC_PIN_GROUP(msiof1_clk_b), SH_PFC_PIN_GROUP(msiof1_ss1_f),
SH_PFC_PIN_GROUP(msiof1_sync_b), SH_PFC_PIN_GROUP(msiof1_ss2_f),
SH_PFC_PIN_GROUP(msiof1_ss1_b), SH_PFC_PIN_GROUP(msiof1_txd_f),
SH_PFC_PIN_GROUP(msiof1_ss2_b), SH_PFC_PIN_GROUP(msiof1_rxd_f),
SH_PFC_PIN_GROUP(msiof1_txd_b), SH_PFC_PIN_GROUP(msiof1_clk_g),
SH_PFC_PIN_GROUP(msiof1_rxd_b), SH_PFC_PIN_GROUP(msiof1_sync_g),
SH_PFC_PIN_GROUP(msiof1_clk_c), SH_PFC_PIN_GROUP(msiof1_ss1_g),
SH_PFC_PIN_GROUP(msiof1_sync_c), SH_PFC_PIN_GROUP(msiof1_ss2_g),
SH_PFC_PIN_GROUP(msiof1_ss1_c), SH_PFC_PIN_GROUP(msiof1_txd_g),
SH_PFC_PIN_GROUP(msiof1_ss2_c), SH_PFC_PIN_GROUP(msiof1_rxd_g),
SH_PFC_PIN_GROUP(msiof1_txd_c), SH_PFC_PIN_GROUP(msiof2_clk_a),
SH_PFC_PIN_GROUP(msiof1_rxd_c), SH_PFC_PIN_GROUP(msiof2_sync_a),
SH_PFC_PIN_GROUP(msiof1_clk_d), SH_PFC_PIN_GROUP(msiof2_ss1_a),
SH_PFC_PIN_GROUP(msiof1_sync_d), SH_PFC_PIN_GROUP(msiof2_ss2_a),
SH_PFC_PIN_GROUP(msiof1_ss1_d), SH_PFC_PIN_GROUP(msiof2_txd_a),
SH_PFC_PIN_GROUP(msiof1_ss2_d), SH_PFC_PIN_GROUP(msiof2_rxd_a),
SH_PFC_PIN_GROUP(msiof1_txd_d), SH_PFC_PIN_GROUP(msiof2_clk_b),
SH_PFC_PIN_GROUP(msiof1_rxd_d), SH_PFC_PIN_GROUP(msiof2_sync_b),
SH_PFC_PIN_GROUP(msiof1_clk_e), SH_PFC_PIN_GROUP(msiof2_ss1_b),
SH_PFC_PIN_GROUP(msiof1_sync_e), SH_PFC_PIN_GROUP(msiof2_ss2_b),
SH_PFC_PIN_GROUP(msiof1_ss1_e), SH_PFC_PIN_GROUP(msiof2_txd_b),
SH_PFC_PIN_GROUP(msiof1_ss2_e), SH_PFC_PIN_GROUP(msiof2_rxd_b),
SH_PFC_PIN_GROUP(msiof1_txd_e), SH_PFC_PIN_GROUP(msiof2_clk_c),
SH_PFC_PIN_GROUP(msiof1_rxd_e), SH_PFC_PIN_GROUP(msiof2_sync_c),
SH_PFC_PIN_GROUP(msiof1_clk_f), SH_PFC_PIN_GROUP(msiof2_ss1_c),
SH_PFC_PIN_GROUP(msiof1_sync_f), SH_PFC_PIN_GROUP(msiof2_ss2_c),
SH_PFC_PIN_GROUP(msiof1_ss1_f), SH_PFC_PIN_GROUP(msiof2_txd_c),
SH_PFC_PIN_GROUP(msiof1_ss2_f), SH_PFC_PIN_GROUP(msiof2_rxd_c),
SH_PFC_PIN_GROUP(msiof1_txd_f), SH_PFC_PIN_GROUP(msiof2_clk_d),
SH_PFC_PIN_GROUP(msiof1_rxd_f), SH_PFC_PIN_GROUP(msiof2_sync_d),
SH_PFC_PIN_GROUP(msiof1_clk_g), SH_PFC_PIN_GROUP(msiof2_ss1_d),
SH_PFC_PIN_GROUP(msiof1_sync_g), SH_PFC_PIN_GROUP(msiof2_ss2_d),
SH_PFC_PIN_GROUP(msiof1_ss1_g), SH_PFC_PIN_GROUP(msiof2_txd_d),
SH_PFC_PIN_GROUP(msiof1_ss2_g), SH_PFC_PIN_GROUP(msiof2_rxd_d),
SH_PFC_PIN_GROUP(msiof1_txd_g), SH_PFC_PIN_GROUP(msiof3_clk_a),
SH_PFC_PIN_GROUP(msiof1_rxd_g), SH_PFC_PIN_GROUP(msiof3_sync_a),
SH_PFC_PIN_GROUP(msiof2_clk_a), SH_PFC_PIN_GROUP(msiof3_ss1_a),
SH_PFC_PIN_GROUP(msiof2_sync_a), SH_PFC_PIN_GROUP(msiof3_ss2_a),
SH_PFC_PIN_GROUP(msiof2_ss1_a), SH_PFC_PIN_GROUP(msiof3_txd_a),
SH_PFC_PIN_GROUP(msiof2_ss2_a), SH_PFC_PIN_GROUP(msiof3_rxd_a),
SH_PFC_PIN_GROUP(msiof2_txd_a), SH_PFC_PIN_GROUP(msiof3_clk_b),
SH_PFC_PIN_GROUP(msiof2_rxd_a), SH_PFC_PIN_GROUP(msiof3_sync_b),
SH_PFC_PIN_GROUP(msiof2_clk_b), SH_PFC_PIN_GROUP(msiof3_ss1_b),
SH_PFC_PIN_GROUP(msiof2_sync_b), SH_PFC_PIN_GROUP(msiof3_ss2_b),
SH_PFC_PIN_GROUP(msiof2_ss1_b), SH_PFC_PIN_GROUP(msiof3_txd_b),
SH_PFC_PIN_GROUP(msiof2_ss2_b), SH_PFC_PIN_GROUP(msiof3_rxd_b),
SH_PFC_PIN_GROUP(msiof2_txd_b), SH_PFC_PIN_GROUP(msiof3_clk_c),
SH_PFC_PIN_GROUP(msiof2_rxd_b), SH_PFC_PIN_GROUP(msiof3_sync_c),
SH_PFC_PIN_GROUP(msiof2_clk_c), SH_PFC_PIN_GROUP(msiof3_txd_c),
SH_PFC_PIN_GROUP(msiof2_sync_c), SH_PFC_PIN_GROUP(msiof3_rxd_c),
SH_PFC_PIN_GROUP(msiof2_ss1_c), SH_PFC_PIN_GROUP(msiof3_clk_d),
SH_PFC_PIN_GROUP(msiof2_ss2_c), SH_PFC_PIN_GROUP(msiof3_sync_d),
SH_PFC_PIN_GROUP(msiof2_txd_c), SH_PFC_PIN_GROUP(msiof3_ss1_d),
SH_PFC_PIN_GROUP(msiof2_rxd_c), SH_PFC_PIN_GROUP(msiof3_txd_d),
SH_PFC_PIN_GROUP(msiof2_clk_d), SH_PFC_PIN_GROUP(msiof3_rxd_d),
SH_PFC_PIN_GROUP(msiof2_sync_d), SH_PFC_PIN_GROUP(msiof3_clk_e),
SH_PFC_PIN_GROUP(msiof2_ss1_d), SH_PFC_PIN_GROUP(msiof3_sync_e),
SH_PFC_PIN_GROUP(msiof2_ss2_d), SH_PFC_PIN_GROUP(msiof3_ss1_e),
SH_PFC_PIN_GROUP(msiof2_txd_d), SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof2_rxd_d), SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_clk_a), SH_PFC_PIN_GROUP(msiof3_rxd_e),
SH_PFC_PIN_GROUP(msiof3_sync_a), SH_PFC_PIN_GROUP(pwm0),
SH_PFC_PIN_GROUP(msiof3_ss1_a), SH_PFC_PIN_GROUP(pwm1_a),
SH_PFC_PIN_GROUP(msiof3_ss2_a), SH_PFC_PIN_GROUP(pwm1_b),
SH_PFC_PIN_GROUP(msiof3_txd_a), SH_PFC_PIN_GROUP(pwm2_a),
SH_PFC_PIN_GROUP(msiof3_rxd_a), SH_PFC_PIN_GROUP(pwm2_b),
SH_PFC_PIN_GROUP(msiof3_clk_b), SH_PFC_PIN_GROUP(pwm3_a),
SH_PFC_PIN_GROUP(msiof3_sync_b), SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(msiof3_ss1_b), SH_PFC_PIN_GROUP(pwm4_a),
SH_PFC_PIN_GROUP(msiof3_ss2_b), SH_PFC_PIN_GROUP(pwm4_b),
SH_PFC_PIN_GROUP(msiof3_txd_b), SH_PFC_PIN_GROUP(pwm5_a),
SH_PFC_PIN_GROUP(msiof3_rxd_b), SH_PFC_PIN_GROUP(pwm5_b),
SH_PFC_PIN_GROUP(msiof3_clk_c), SH_PFC_PIN_GROUP(pwm6_a),
SH_PFC_PIN_GROUP(msiof3_sync_c), SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(msiof3_txd_c), SH_PFC_PIN_GROUP(sata0_devslp_a),
SH_PFC_PIN_GROUP(msiof3_rxd_c), SH_PFC_PIN_GROUP(sata0_devslp_b),
SH_PFC_PIN_GROUP(msiof3_clk_d), SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(msiof3_sync_d), SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(msiof3_ss1_d), SH_PFC_PIN_GROUP(scif0_ctrl),
SH_PFC_PIN_GROUP(msiof3_txd_d), SH_PFC_PIN_GROUP(scif1_data_a),
SH_PFC_PIN_GROUP(msiof3_rxd_d), SH_PFC_PIN_GROUP(scif1_clk),
SH_PFC_PIN_GROUP(msiof3_clk_e), SH_PFC_PIN_GROUP(scif1_ctrl),
SH_PFC_PIN_GROUP(msiof3_sync_e), SH_PFC_PIN_GROUP(scif1_data_b),
SH_PFC_PIN_GROUP(msiof3_ss1_e), SH_PFC_PIN_GROUP(scif2_data_a),
SH_PFC_PIN_GROUP(msiof3_ss2_e), SH_PFC_PIN_GROUP(scif2_clk),
SH_PFC_PIN_GROUP(msiof3_txd_e), SH_PFC_PIN_GROUP(scif2_data_b),
SH_PFC_PIN_GROUP(msiof3_rxd_e), SH_PFC_PIN_GROUP(scif3_data_a),
SH_PFC_PIN_GROUP(pwm0), SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(pwm1_a), SH_PFC_PIN_GROUP(scif3_ctrl),
SH_PFC_PIN_GROUP(pwm1_b), SH_PFC_PIN_GROUP(scif3_data_b),
SH_PFC_PIN_GROUP(pwm2_a), SH_PFC_PIN_GROUP(scif4_data_a),
SH_PFC_PIN_GROUP(pwm2_b), SH_PFC_PIN_GROUP(scif4_clk_a),
SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(scif4_ctrl_a),
SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(scif4_data_b),
SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(scif4_clk_b),
SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(scif4_ctrl_b),
SH_PFC_PIN_GROUP(pwm5_a), SH_PFC_PIN_GROUP(scif4_data_c),
SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(scif4_clk_c),
SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(scif4_ctrl_c),
SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(scif5_data_a),
SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(scif5_clk_a),
SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif5_data_b),
SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif5_clk_b),
SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif0_ctrl), SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(scif1_data_a), SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(scif1_clk), SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(scif1_ctrl), SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(scif1_data_b), SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(scif2_data_a), SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(scif2_clk), SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(scif2_data_b), SH_PFC_PIN_GROUP(sdhi1_data4),
SH_PFC_PIN_GROUP(scif3_data_a), SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(scif3_clk), SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(scif3_ctrl), SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(scif3_data_b), SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(scif4_data_a), SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(scif4_clk_a), SH_PFC_PIN_GROUP(sdhi2_data8),
SH_PFC_PIN_GROUP(scif4_ctrl_a), SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(scif4_data_b), SH_PFC_PIN_GROUP(sdhi2_cd_a),
SH_PFC_PIN_GROUP(scif4_clk_b), SH_PFC_PIN_GROUP(sdhi2_wp_a),
SH_PFC_PIN_GROUP(scif4_ctrl_b), SH_PFC_PIN_GROUP(sdhi2_cd_b),
SH_PFC_PIN_GROUP(scif4_data_c), SH_PFC_PIN_GROUP(sdhi2_wp_b),
SH_PFC_PIN_GROUP(scif4_clk_c), SH_PFC_PIN_GROUP(sdhi2_ds),
SH_PFC_PIN_GROUP(scif4_ctrl_c), SH_PFC_PIN_GROUP(sdhi3_data1),
SH_PFC_PIN_GROUP(scif5_data_a), SH_PFC_PIN_GROUP(sdhi3_data4),
SH_PFC_PIN_GROUP(scif5_clk_a), SH_PFC_PIN_GROUP(sdhi3_data8),
SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(sdhi3_ctrl),
SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(sdhi3_cd),
SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(sdhi3_wp),
SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(sdhi3_ds),
SH_PFC_PIN_GROUP(sdhi0_data1), SH_PFC_PIN_GROUP(ssi0_data),
SH_PFC_PIN_GROUP(sdhi0_data4), SH_PFC_PIN_GROUP(ssi01239_ctrl),
SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(ssi1_data_a),
SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(ssi1_data_b),
SH_PFC_PIN_GROUP(sdhi0_wp), SH_PFC_PIN_GROUP(ssi1_ctrl_a),
SH_PFC_PIN_GROUP(sdhi1_data1), SH_PFC_PIN_GROUP(ssi1_ctrl_b),
SH_PFC_PIN_GROUP(sdhi1_data4), SH_PFC_PIN_GROUP(ssi2_data_a),
SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(ssi2_data_b),
SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(ssi2_ctrl_a),
SH_PFC_PIN_GROUP(sdhi1_wp), SH_PFC_PIN_GROUP(ssi2_ctrl_b),
SH_PFC_PIN_GROUP(sdhi2_data1), SH_PFC_PIN_GROUP(ssi3_data),
SH_PFC_PIN_GROUP(sdhi2_data4), SH_PFC_PIN_GROUP(ssi349_ctrl),
SH_PFC_PIN_GROUP(sdhi2_data8), SH_PFC_PIN_GROUP(ssi4_data),
SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(ssi4_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(ssi5_data),
SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(ssi5_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(ssi6_data),
SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(ssi6_ctrl),
SH_PFC_PIN_GROUP(sdhi2_ds), SH_PFC_PIN_GROUP(ssi7_data),
SH_PFC_PIN_GROUP(sdhi3_data1), SH_PFC_PIN_GROUP(ssi78_ctrl),
SH_PFC_PIN_GROUP(sdhi3_data4), SH_PFC_PIN_GROUP(ssi8_data),
SH_PFC_PIN_GROUP(sdhi3_data8), SH_PFC_PIN_GROUP(ssi9_data_a),
SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(sdhi3_ds), SH_PFC_PIN_GROUP(tmu_tclk1_a),
SH_PFC_PIN_GROUP(ssi0_data), SH_PFC_PIN_GROUP(tmu_tclk1_b),
SH_PFC_PIN_GROUP(ssi01239_ctrl), SH_PFC_PIN_GROUP(tmu_tclk2_a),
SH_PFC_PIN_GROUP(ssi1_data_a), SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(ssi1_data_b), SH_PFC_PIN_GROUP(tpu_to0),
SH_PFC_PIN_GROUP(ssi1_ctrl_a), SH_PFC_PIN_GROUP(tpu_to1),
SH_PFC_PIN_GROUP(ssi1_ctrl_b), SH_PFC_PIN_GROUP(tpu_to2),
SH_PFC_PIN_GROUP(ssi2_data_a), SH_PFC_PIN_GROUP(tpu_to3),
SH_PFC_PIN_GROUP(ssi2_data_b), SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(ssi2_ctrl_a), SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(ssi2_ctrl_b), SH_PFC_PIN_GROUP(usb30),
SH_PFC_PIN_GROUP(ssi3_data), VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
SH_PFC_PIN_GROUP(ssi349_ctrl), VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
SH_PFC_PIN_GROUP(ssi4_data), VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
SH_PFC_PIN_GROUP(ssi4_ctrl), VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
SH_PFC_PIN_GROUP(ssi5_data), SH_PFC_PIN_GROUP(vin4_data18_a),
SH_PFC_PIN_GROUP(ssi5_ctrl), VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
SH_PFC_PIN_GROUP(ssi6_data), VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
SH_PFC_PIN_GROUP(ssi6_ctrl), VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
SH_PFC_PIN_GROUP(ssi7_data), VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
SH_PFC_PIN_GROUP(ssi78_ctrl), VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
SH_PFC_PIN_GROUP(ssi8_data), VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
SH_PFC_PIN_GROUP(ssi9_data_a), SH_PFC_PIN_GROUP(vin4_data18_b),
SH_PFC_PIN_GROUP(ssi9_data_b), VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a), VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(ssi9_ctrl_b), SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(tmu_tclk1_a), SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(vin4_clkenb),
SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(vin4_clk),
SH_PFC_PIN_GROUP(tmu_tclk2_b), VIN_DATA_PIN_GROUP(vin5_data, 8),
SH_PFC_PIN_GROUP(tpu_to0), VIN_DATA_PIN_GROUP(vin5_data, 10),
SH_PFC_PIN_GROUP(tpu_to1), VIN_DATA_PIN_GROUP(vin5_data, 12),
SH_PFC_PIN_GROUP(tpu_to2), VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(vin5_clk),
VIN_DATA_PIN_GROUP(vin4_data, 8, _a), },
VIN_DATA_PIN_GROUP(vin4_data, 10, _a), .automotive = {
VIN_DATA_PIN_GROUP(vin4_data, 12, _a), SH_PFC_PIN_GROUP(drif0_ctrl_a),
VIN_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(drif0_data0_a),
SH_PFC_PIN_GROUP(vin4_data18_a), SH_PFC_PIN_GROUP(drif0_data1_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _a), SH_PFC_PIN_GROUP(drif0_ctrl_b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _a), SH_PFC_PIN_GROUP(drif0_data0_b),
VIN_DATA_PIN_GROUP(vin4_data, 8, _b), SH_PFC_PIN_GROUP(drif0_data1_b),
VIN_DATA_PIN_GROUP(vin4_data, 10, _b), SH_PFC_PIN_GROUP(drif0_ctrl_c),
VIN_DATA_PIN_GROUP(vin4_data, 12, _b), SH_PFC_PIN_GROUP(drif0_data0_c),
VIN_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(drif0_data1_c),
SH_PFC_PIN_GROUP(vin4_data18_b), SH_PFC_PIN_GROUP(drif1_ctrl_a),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b), SH_PFC_PIN_GROUP(drif1_data0_a),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b), SH_PFC_PIN_GROUP(drif1_data1_a),
SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(drif1_ctrl_b),
SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(drif1_data0_b),
SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(drif1_data1_b),
SH_PFC_PIN_GROUP(vin4_clk), SH_PFC_PIN_GROUP(drif1_ctrl_c),
VIN_DATA_PIN_GROUP(vin5_data, 8), SH_PFC_PIN_GROUP(drif1_data0_c),
VIN_DATA_PIN_GROUP(vin5_data, 10), SH_PFC_PIN_GROUP(drif1_data1_c),
VIN_DATA_PIN_GROUP(vin5_data, 12), SH_PFC_PIN_GROUP(drif2_ctrl_a),
VIN_DATA_PIN_GROUP(vin5_data, 16), SH_PFC_PIN_GROUP(drif2_data0_a),
SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(drif2_data1_a),
SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(drif2_ctrl_b),
SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(drif2_data0_b),
SH_PFC_PIN_GROUP(vin5_clk), SH_PFC_PIN_GROUP(drif2_data1_b),
SH_PFC_PIN_GROUP(drif3_ctrl_a),
SH_PFC_PIN_GROUP(drif3_data0_a),
SH_PFC_PIN_GROUP(drif3_data1_a),
SH_PFC_PIN_GROUP(drif3_ctrl_b),
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
}; };
static const char * const audio_clk_groups[] = { static const char * const audio_clk_groups[] = {
...@@ -5241,62 +5248,69 @@ static const char * const vin5_groups[] = { ...@@ -5241,62 +5248,69 @@ static const char * const vin5_groups[] = {
"vin5_clk", "vin5_clk",
}; };
static const struct sh_pfc_function pinmux_functions[] = { static const struct {
SH_PFC_FUNCTION(audio_clk), struct sh_pfc_function common[51];
SH_PFC_FUNCTION(avb), struct sh_pfc_function automotive[4];
SH_PFC_FUNCTION(can0), } pinmux_functions = {
SH_PFC_FUNCTION(can1), .common = {
SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(canfd0), SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(can0),
SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(can1),
SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4), SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c3),
SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(pwm0), SH_PFC_FUNCTION(pwm0),
SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm1),
SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5), SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(sata0), SH_PFC_FUNCTION(sata0),
SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2), SH_PFC_FUNCTION(scif2),
SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(tmu), SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(tpu), SH_PFC_FUNCTION(tpu),
SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30), SH_PFC_FUNCTION(usb30),
SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5), SH_PFC_FUNCTION(vin5),
},
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
}; };
static const struct pinmux_cfg_reg pinmux_config_regs[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = {
...@@ -6425,6 +6439,32 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { ...@@ -6425,6 +6439,32 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
.set_bias = r8a77965_pinmux_set_bias, .set_bias = r8a77965_pinmux_set_bias,
}; };
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
.name = "r8a774b1_pfc",
.ops = &r8a77965_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups.common),
.functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs,
.bias_regs = pinmux_bias_regs,
.ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
};
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
const struct sh_pfc_soc_info r8a77965_pinmux_info = { const struct sh_pfc_soc_info r8a77965_pinmux_info = {
.name = "r8a77965_pfc", .name = "r8a77965_pfc",
.ops = &r8a77965_pinmux_ops, .ops = &r8a77965_pinmux_ops,
...@@ -6434,10 +6474,12 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = { ...@@ -6434,10 +6474,12 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = {
.pins = pinmux_pins, .pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins), .nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups, .groups = pinmux_groups.common,
.nr_groups = ARRAY_SIZE(pinmux_groups), .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
.functions = pinmux_functions, ARRAY_SIZE(pinmux_groups.automotive),
.nr_functions = ARRAY_SIZE(pinmux_functions), .functions = pinmux_functions.common,
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs, .cfg_regs = pinmux_config_regs,
.drive_regs = pinmux_drive_regs, .drive_regs = pinmux_drive_regs,
...@@ -6447,3 +6489,4 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = { ...@@ -6447,3 +6489,4 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = {
.pinmux_data = pinmux_data, .pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data), .pinmux_data_size = ARRAY_SIZE(pinmux_data),
}; };
#endif
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
View file @ 66ee1973
...@@ -232,8 +232,8 @@ ...@@ -232,8 +232,8 @@
#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
...@@ -448,6 +448,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM ...@@ -448,6 +448,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
...@@ -468,7 +470,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM ...@@ -468,7 +470,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
#define PINMUX_MOD_SELS \ #define PINMUX_MOD_SELS \
\ \
MOD_SEL0_30_29 \ MOD_SEL1_31 \
MOD_SEL0_30_29 MOD_SEL1_30 \
MOD_SEL1_29 \ MOD_SEL1_29 \
MOD_SEL0_28 MOD_SEL1_28 \ MOD_SEL0_28 MOD_SEL1_28 \
MOD_SEL0_27_26 \ MOD_SEL0_27_26 \
...@@ -634,7 +637,7 @@ static const u16 pinmux_data[] = { ...@@ -634,7 +637,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N), PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0), PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A), PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N), PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
PINMUX_IPSR_GPSR(IP2_23_20, TX5_B), PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2), PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
...@@ -642,7 +645,7 @@ static const u16 pinmux_data[] = { ...@@ -642,7 +645,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0), PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0), PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A), PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N), PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1), PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0), PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
...@@ -1058,7 +1061,7 @@ static const u16 pinmux_data[] = { ...@@ -1058,7 +1061,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B), PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
...@@ -1067,7 +1070,7 @@ static const u16 pinmux_data[] = { ...@@ -1067,7 +1070,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B), PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
/* IPSR11 */ /* IPSR11 */
...@@ -1085,13 +1088,13 @@ static const u16 pinmux_data[] = { ...@@ -1085,13 +1088,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A), PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A), PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
...@@ -1196,7 +1199,7 @@ static const u16 pinmux_data[] = { ...@@ -1196,7 +1199,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A), PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
...@@ -1264,7 +1267,7 @@ static const u16 pinmux_data[] = { ...@@ -1264,7 +1267,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B), PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
...@@ -1524,22 +1527,22 @@ static const unsigned int avb_avtp_pps_mux[] = { ...@@ -1524,22 +1527,22 @@ static const unsigned int avb_avtp_pps_mux[] = {
AVB_AVTP_PPS_MARK, AVB_AVTP_PPS_MARK,
}; };
static const unsigned int avb_avtp_match_a_pins[] = { static const unsigned int avb_avtp_match_pins[] = {
/* AVB_AVTP_MATCH_A */ /* AVB_AVTP_MATCH */
RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 24),
}; };
static const unsigned int avb_avtp_match_a_mux[] = { static const unsigned int avb_avtp_match_mux[] = {
AVB_AVTP_MATCH_A_MARK, AVB_AVTP_MATCH_MARK,
}; };
static const unsigned int avb_avtp_capture_a_pins[] = { static const unsigned int avb_avtp_capture_pins[] = {
/* AVB_AVTP_CAPTURE_A */ /* AVB_AVTP_CAPTURE */
RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 25),
}; };
static const unsigned int avb_avtp_capture_a_mux[] = { static const unsigned int avb_avtp_capture_mux[] = {
AVB_AVTP_CAPTURE_A_MARK, AVB_AVTP_CAPTURE_MARK,
}; };
/* - CAN ------------------------------------------------------------------ */ /* - CAN ------------------------------------------------------------------ */
...@@ -3784,8 +3787,8 @@ static const struct { ...@@ -3784,8 +3787,8 @@ static const struct {
SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_phy_int),
SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_mii),
SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_pps),
SH_PFC_PIN_GROUP(avb_avtp_match_a), SH_PFC_PIN_GROUP(avb_avtp_match),
SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_capture),
SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can0_data),
SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can1_data),
SH_PFC_PIN_GROUP(can_clk), SH_PFC_PIN_GROUP(can_clk),
...@@ -4061,8 +4064,8 @@ static const char * const avb_groups[] = { ...@@ -4061,8 +4064,8 @@ static const char * const avb_groups[] = {
"avb_phy_int", "avb_phy_int",
"avb_mii", "avb_mii",
"avb_avtp_pps", "avb_avtp_pps",
"avb_avtp_match_a", "avb_avtp_match",
"avb_avtp_capture_a", "avb_avtp_capture",
}; };
static const char * const can0_groups[] = { static const char * const can0_groups[] = {
...@@ -4957,11 +4960,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { ...@@ -4957,11 +4960,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_1_0 )) MOD_SEL0_1_0 ))
}, },
{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
2, 2, 2, 1, 1, 2, 1, 4), 1, 2, 2, 2, 1, 1, 2, 1, 4),
GROUP( GROUP(
/* RESERVED 31, 30 */ MOD_SEL1_31
0, 0, 0, 0, MOD_SEL1_30
MOD_SEL1_29 MOD_SEL1_29
MOD_SEL1_28 MOD_SEL1_28
/* RESERVED 27 */ /* RESERVED 27 */
......
drivers/pinctrl/sh-pfc/sh_pfc.h
View file @ 66ee1973
...@@ -309,6 +309,7 @@ extern const struct sh_pfc_soc_info r8a7744_pinmux_info; ...@@ -309,6 +309,7 @@ extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
extern const struct sh_pfc_soc_info r8a7745_pinmux_info; extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
extern const struct sh_pfc_soc_info r8a77470_pinmux_info; extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
...@@ -422,12 +423,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; ...@@ -422,12 +423,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
/* /*
* Describe a pinmux configuration in which a pin is physically multiplexed * Describe a pinmux configuration in which a pin is physically multiplexed
* with other pins. * with other pins.
* - ipsr: IPSR field (unused, for documentation purposes only) * - ipsr: IPSR field
* - fn: Function name * - fn: Function name
* - psel: Physical multiplexing selector * - psel: Physical multiplexing selector
*/ */
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
PINMUX_DATA(fn##_MARK, FN_##psel) PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
/* /*
* Describe a pinmux configuration for a single-function pin with GPIO * Describe a pinmux configuration for a single-function pin with GPIO
......
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