Commit 675b0563 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Will Deacon

arm64: cpufeature: expose arm64_ftr_reg struct for CTR_EL0

Expose the arm64_ftr_reg struct covering CTR_EL0 outside of cpufeature.o
so that other code can refer to it directly (i.e., without performing the
binary search)
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 6f2b7eef
...@@ -78,6 +78,8 @@ struct arm64_ftr_reg { ...@@ -78,6 +78,8 @@ struct arm64_ftr_reg {
const struct arm64_ftr_bits *ftr_bits; const struct arm64_ftr_bits *ftr_bits;
}; };
extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
/* scope of capability check */ /* scope of capability check */
enum { enum {
SCOPE_SYSTEM, SCOPE_SYSTEM,
......
...@@ -155,6 +155,11 @@ static const struct arm64_ftr_bits ftr_ctr[] = { ...@@ -155,6 +155,11 @@ static const struct arm64_ftr_bits ftr_ctr[] = {
ARM64_FTR_END, ARM64_FTR_END,
}; };
struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
.name = "SYS_CTR_EL0",
.ftr_bits = ftr_ctr
};
static const struct arm64_ftr_bits ftr_id_mmfr0[] = { static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */ S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */ ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
...@@ -318,7 +323,7 @@ static const struct __ftr_reg_entry { ...@@ -318,7 +323,7 @@ static const struct __ftr_reg_entry {
ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
/* Op1 = 3, CRn = 0, CRm = 0 */ /* Op1 = 3, CRn = 0, CRm = 0 */
ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr), { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
/* Op1 = 3, CRn = 14, CRm = 0 */ /* Op1 = 3, CRn = 14, CRm = 0 */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment