Commit 6865f0ea authored by Ryusuke Sakato's avatar Ryusuke Sakato Committed by Paul Mundt

sh: Solution Engine 7722 board support.

This adds more full-featured support for the SH7722 Solution Engine.
Previously this was using the generic board, and lacked most of the
peripheral support.
Signed-off-by: default avatarRyusuke Sakato <sakato.ryusuke@renesas.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 6b817c03
...@@ -92,6 +92,14 @@ config SH_SOLUTION_ENGINE ...@@ -92,6 +92,14 @@ config SH_SOLUTION_ENGINE
Select SolutionEngine if configuring for a Hitachi SH7709 Select SolutionEngine if configuring for a Hitachi SH7709
or SH7750 evaluation board. or SH7750 evaluation board.
config SH_7722_SOLUTION_ENGINE
bool "SolutionEngine7722"
select SOLUTION_ENGINE
select CPU_SUBTYPE_SH7722
help
Select 7722 SolutionEngine if configuring for a Hitachi SH772
evaluation board.
config SH_7751_SOLUTION_ENGINE config SH_7751_SOLUTION_ENGINE
bool "SolutionEngine7751" bool "SolutionEngine7751"
select SOLUTION_ENGINE select SOLUTION_ENGINE
......
...@@ -88,6 +88,7 @@ core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/ ...@@ -88,6 +88,7 @@ core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
# Boards # Boards
machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x
machdir-$(CONFIG_SH_7722_SOLUTION_ENGINE) := se/7722
machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se/7751 machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se/7751
machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) := se/7780 machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) := se/7780
machdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se/7300 machdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se/7300
......
#
# Makefile for the HITACHI UL SolutionEngine 7722 specific parts of the kernel
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
#
obj-y := setup.o irq.o
/*
* linux/arch/sh/boards/se/7722/irq.c
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7722 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/se7722.h>
#define INTC_INTMSK0 0xFFD00044
#define INTC_INTMSKCLR0 0xFFD00064
static void disable_se7722_irq(unsigned int irq)
{
struct ipr_data *p = get_irq_chip_data(irq);
ctrl_outw( ctrl_inw( p->addr ) | p->priority , p->addr );
}
static void enable_se7722_irq(unsigned int irq)
{
struct ipr_data *p = get_irq_chip_data(irq);
ctrl_outw( ctrl_inw( p->addr ) & ~p->priority , p->addr );
}
static struct irq_chip se7722_irq_chip __read_mostly = {
.name = "SE7722",
.mask = disable_se7722_irq,
.unmask = enable_se7722_irq,
.mask_ack = disable_se7722_irq,
};
static struct ipr_data ipr_irq_table[] = {
/* irq ,idx,sft, priority , addr */
{ MRSHPC_IRQ0 , 0 , 0 , MRSHPC_BIT0 , IRQ01_MASK } ,
{ MRSHPC_IRQ1 , 0 , 0 , MRSHPC_BIT1 , IRQ01_MASK } ,
{ MRSHPC_IRQ2 , 0 , 0 , MRSHPC_BIT2 , IRQ01_MASK } ,
{ MRSHPC_IRQ3 , 0 , 0 , MRSHPC_BIT3 , IRQ01_MASK } ,
{ SMC_IRQ , 0 , 0 , SMC_BIT , IRQ01_MASK } ,
{ EXT_IRQ , 0 , 0 , EXT_BIT , IRQ01_MASK } ,
};
int se7722_irq_demux(int irq)
{
if ((irq == IRQ0_IRQ)||(irq == IRQ1_IRQ)) {
volatile unsigned short intv =
*(volatile unsigned short *)IRQ01_STS;
if (irq == IRQ0_IRQ){
if(intv & SMC_BIT ) {
return SMC_IRQ;
} else if(intv & USB_BIT) {
return USB_IRQ;
} else {
printk("intv =%04x\n", intv);
return SMC_IRQ;
}
} else if(irq == IRQ1_IRQ){
if(intv & MRSHPC_BIT0) {
return MRSHPC_IRQ0;
} else if(intv & MRSHPC_BIT1) {
return MRSHPC_IRQ1;
} else if(intv & MRSHPC_BIT2) {
return MRSHPC_IRQ2;
} else if(intv & MRSHPC_BIT3) {
return MRSHPC_IRQ3;
} else {
printk("BIT_EXTENTION =%04x\n", intv);
return EXT_IRQ;
}
}
}
return irq;
}
/*
* Initialize IRQ setting
*/
void __init init_se7722_IRQ(void)
{
int i = 0;
ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
ctrl_outl((3 << ((7 - 0) * 4))|(3 << ((7 - 1) * 4)), INTC_INTPRI0); /* irq0 pri=3,irq1,pri=3 */
ctrl_outw((2 << ((7 - 0) * 2))|(2 << ((7 - 1) * 2)), INTC_ICR1); /* irq0,1 low-level irq */
for (i = 0; i < ARRAY_SIZE(ipr_irq_table); i++) {
disable_irq_nosync(ipr_irq_table[i].irq);
set_irq_chip_and_handler_name( ipr_irq_table[i].irq, &se7722_irq_chip,
handle_level_irq, "level");
set_irq_chip_data( ipr_irq_table[i].irq, &ipr_irq_table[i] );
disable_se7722_irq(ipr_irq_table[i].irq);
}
}
/*
* linux/arch/sh/boards/se/7722/setup.c
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7722 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pata_platform.h>
#include <asm/machvec.h>
#include <asm/se7722.h>
#include <asm/io.h>
/* Heartbeat */
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
/* SMC91x */
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "smc91x-regs" ,
.start = PA_LAN + 0x300,
.end = PA_LAN + 0x300 + 0x10 ,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SMC_IRQ,
.end = SMC_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.id = 0,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
};
static struct resource cf_ide_resources[] = {
[0] = {
.start = PA_MRSHPC_IO + 0x1f0,
.end = PA_MRSHPC_IO + 0x1f0 + 8 ,
.flags = IORESOURCE_IO,
},
[1] = {
.start = PA_MRSHPC_IO + 0x1f0 + 0x206,
.end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8,
.flags = IORESOURCE_IO,
},
[2] = {
.start = MRSHPC_IRQ0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cf_ide_device = {
.name = "pata_platform",
.id = -1,
.num_resources = ARRAY_SIZE(cf_ide_resources),
.resource = cf_ide_resources,
};
static struct platform_device *se7722_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
&cf_ide_device,
};
static int __init se7722_devices_setup(void)
{
return platform_add_devices(se7722_devices,
ARRAY_SIZE(se7722_devices));
}
device_initcall(se7722_devices_setup);
static void __init se7722_setup(char **cmdline_p)
{
ctrl_outw(0x010D, FPGA_OUT); /* FPGA */
ctrl_outl(0x00051001, MSTPCR0);
ctrl_outl(0x00000000, MSTPCR1);
/* KEYSC, VOU, BEU, CEU, VEU, VPU, LCDC */
ctrl_outl(0xffffbfC0, MSTPCR2);
ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
/* LCDC I/O */
ctrl_outw(0x0020, PORT_PSELD);
/* SIOF1*/
ctrl_outw(0x0003, PORT_PSELB);
ctrl_outw(0xe000, PORT_PSELC);
ctrl_outw(0x0000, PORT_PKCR);
/* LCDC */
ctrl_outw(0x4020, PORT_PHCR);
ctrl_outw(0x0000, PORT_PLCR);
ctrl_outw(0x0000, PORT_PMCR);
ctrl_outw(0x0002, PORT_PRCR);
ctrl_outw(0x0000, PORT_PXCR); /* LCDC,CS6A */
/* KEYSC */
ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */
ctrl_outw(0x0000, PORT_PYCR);
ctrl_outw(0x0000, PORT_PZCR);
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_se7722 __initmv = {
.mv_name = "Solution Engine 7722" ,
.mv_setup = se7722_setup ,
.mv_nr_irqs = 109 ,
.mv_init_irq = init_se7722_IRQ,
.mv_irq_demux = se7722_irq_demux,
};
ALIAS_MV(se7722)
This diff is collapsed.
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
* 0xB8001000 : Common Memory * 0xB8001000 : Common Memory
* 0xBA000000 : I/O * 0xBA000000 : I/O
*/ */
#if defined(CONFIG_IDE) && defined(CONFIG_CPU_SH4) #if defined(CONFIG_CPU_SH4)
/* SH4 can't access PCMCIA interface through P2 area. /* SH4 can't access PCMCIA interface through P2 area.
* we must remap it with appropreate attribute bit of the page set. * we must remap it with appropreate attribute bit of the page set.
* this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */ * this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */
...@@ -71,7 +71,7 @@ static int __init cf_init_default(void) ...@@ -71,7 +71,7 @@ static int __init cf_init_default(void)
/* You must have enabled the card, and set the level interrupt /* You must have enabled the card, and set the level interrupt
* before reaching this point. Possibly in boot ROM or boot loader. * before reaching this point. Possibly in boot ROM or boot loader.
*/ */
#if defined(CONFIG_IDE) && defined(CONFIG_CPU_SH4) #if defined(CONFIG_CPU_SH4)
allocate_cf_area(); allocate_cf_area();
#endif #endif
#if defined(CONFIG_SH_UNKNOWN) #if defined(CONFIG_SH_UNKNOWN)
...@@ -84,15 +84,25 @@ static int __init cf_init_default(void) ...@@ -84,15 +84,25 @@ static int __init cf_init_default(void)
#if defined(CONFIG_SH_SOLUTION_ENGINE) #if defined(CONFIG_SH_SOLUTION_ENGINE)
#include <asm/se.h> #include <asm/se.h>
#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
#include <asm/se7722.h>
#endif
/* /*
* SolutionEngine * SolutionEngine Seriese
* *
* about MS770xSE
* 0xB8400000 : Common Memory * 0xB8400000 : Common Memory
* 0xB8500000 : Attribute * 0xB8500000 : Attribute
* 0xB8600000 : I/O * 0xB8600000 : I/O
*
* about MS7722SE
* 0xB0400000 : Common Memory
* 0xB0500000 : Attribute
* 0xB0600000 : I/O
*/ */
#if defined(CONFIG_SH_SOLUTION_ENGINE) || defined(CONFIG_SH_7722_SOLUTION_ENGINE)
static int __init cf_init_se(void) static int __init cf_init_se(void)
{ {
if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0) if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
...@@ -109,7 +119,7 @@ static int __init cf_init_se(void) ...@@ -109,7 +119,7 @@ static int __init cf_init_se(void)
* flag == COMMON/ATTRIBUTE/IO * flag == COMMON/ATTRIBUTE/IO
*/ */
/* common window open */ /* common window open */
ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */ ctrl_outw(0x8a84, MRSHPC_MW0CR1);
if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
/* common mode & bus width 16bit SWAP = 1*/ /* common mode & bus width 16bit SWAP = 1*/
ctrl_outw(0x0b00, MRSHPC_MW0CR2); ctrl_outw(0x0b00, MRSHPC_MW0CR2);
...@@ -118,7 +128,7 @@ static int __init cf_init_se(void) ...@@ -118,7 +128,7 @@ static int __init cf_init_se(void)
ctrl_outw(0x0300, MRSHPC_MW0CR2); ctrl_outw(0x0300, MRSHPC_MW0CR2);
/* attribute window open */ /* attribute window open */
ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */ ctrl_outw(0x8a85, MRSHPC_MW1CR1);
if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
/* attribute mode & bus width 16bit SWAP = 1*/ /* attribute mode & bus width 16bit SWAP = 1*/
ctrl_outw(0x0a00, MRSHPC_MW1CR2); ctrl_outw(0x0a00, MRSHPC_MW1CR2);
...@@ -127,7 +137,7 @@ static int __init cf_init_se(void) ...@@ -127,7 +137,7 @@ static int __init cf_init_se(void)
ctrl_outw(0x0200, MRSHPC_MW1CR2); ctrl_outw(0x0200, MRSHPC_MW1CR2);
/* I/O window open */ /* I/O window open */
ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */ ctrl_outw(0x8a86, MRSHPC_IOWCR1);
ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */ ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
...@@ -143,10 +153,10 @@ static int __init cf_init_se(void) ...@@ -143,10 +153,10 @@ static int __init cf_init_se(void)
int __init cf_init(void) int __init cf_init(void)
{ {
#if defined(CONFIG_SH_SOLUTION_ENGINE) if( mach_is_se() || mach_is_7722se() ){
if (MACH_SE)
return cf_init_se(); return cf_init_se();
#endif }
return cf_init_default(); return cf_init_default();
} }
......
#ifndef __ASM_SH_SE7722_H
#define __ASM_SH_SE7722_H
/*
* linux/include/asm-sh/se7722.h
*
* Copyright (C) 2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7722 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#include <asm/addrspace.h>
/* Box specific addresses. */
#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
#define PA_ROM 0xa0000000 /* EPROM */
#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
#define PA_FROM 0xa1000000 /* Flash-ROM */
#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
#define PA_EXT1 0xa4000000
#define PA_EXT1_SIZE 0x04000000
#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */
#define PA_SDRAM_SIZE 0x04000000
#define PA_EXT4 0xb0000000
#define PA_EXT4_SIZE 0x04000000
#define PA_PERIPHERAL 0xB0000000
#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */
#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */
#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */
#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */
#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */
#define MRSHPC_OPTION (PA_MRSHPC + 6)
#define MRSHPC_CSR (PA_MRSHPC + 8)
#define MRSHPC_ISR (PA_MRSHPC + 10)
#define MRSHPC_ICR (PA_MRSHPC + 12)
#define MRSHPC_CPWCR (PA_MRSHPC + 14)
#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
#define MRSHPC_CDCR (PA_MRSHPC + 28)
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */
#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */
#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */
/* GPIO */
#define MSTPCR0 0xA4150030UL
#define MSTPCR1 0xA4150034UL
#define MSTPCR2 0xA4150038UL
#define FPGA_IN 0xb1840000UL
#define FPGA_OUT 0xb1840004UL
#define PORT_PECR 0xA4050108UL
#define PORT_PJCR 0xA4050110UL
#define PORT_PSELD 0xA4050154UL
#define PORT_PSELB 0xA4050150UL
#define PORT_PSELC 0xA4050152UL
#define PORT_PKCR 0xA4050112UL
#define PORT_PHCR 0xA405010EUL
#define PORT_PLCR 0xA4050114UL
#define PORT_PMCR 0xA4050116UL
#define PORT_PRCR 0xA405011CUL
#define PORT_PXCR 0xA4050148UL
#define PORT_PSELA 0xA405014EUL
#define PORT_PYCR 0xA405014AUL
#define PORT_PZCR 0xA405014CUL
/* IRQ */
#define IRQ0_IRQ 32
#define IRQ1_IRQ 33
#define INTC_ICR0 0xA4140000UL
#define INTC_ICR1 0xA414001CUL
#define INTMSK0 0xa4140044
#define INTMSKCLR0 0xa4140064
#define INTC_INTPRI0 0xa4140010
#define IRQ01_MODE 0xb1800000
#define IRQ01_STS 0xb1800004
#define IRQ01_MASK 0xb1800008
#define EXT_BIT (0x3fc0) /* SH IRQ1 */
#define MRSHPC_BIT0 (0x0004) /* SH IRQ1 */
#define MRSHPC_BIT1 (0x0008) /* SH IRQ1 */
#define MRSHPC_BIT2 (0x0010) /* SH IRQ1 */
#define MRSHPC_BIT3 (0x0020) /* SH IRQ1 */
#define SMC_BIT (0x0002) /* SH IRQ0 */
#define USB_BIT (0x0001) /* SH IRQ0 */
#define MRSHPC_IRQ3 11
#define MRSHPC_IRQ2 12
#define MRSHPC_IRQ1 13
#define MRSHPC_IRQ0 14
#define SMC_IRQ 10
#define EXT_IRQ 5
#define USB_IRQ 6
/* arch/sh/boards/se/7722/irq.c */
void init_se7722_IRQ(void);
int se7722_irq_demux(int);
#define __IO_PREFIX se7722
#include <asm/io_generic.h>
#endif /* __ASM_SH_SE7722_H */
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