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Commit 6ba81e53 authored by Alex Deucher's avatar Alex Deucher
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drm/radeon: fix endian handling in rlc buffer setup 

The buffers needs to be in little endian format.
Noticed-by: default avatarSylvain BERTRAND <sylware@legeek.net>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 14ac88af
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Showing with 56 additions and 54 deletions
drivers/gpu/drm/radeon/cik.c
View file @ 6ba81e53
...@@ -5625,7 +5625,7 @@ void cik_init_cp_pg_table(struct radeon_device *rdev) ...@@ -5625,7 +5625,7 @@ void cik_init_cp_pg_table(struct radeon_device *rdev)
} }
for (i = 0; i < CP_ME_TABLE_SIZE; i ++) { for (i = 0; i < CP_ME_TABLE_SIZE; i ++) {
dst_ptr[bo_offset + i] = be32_to_cpu(fw_data[table_offset + i]); dst_ptr[bo_offset + i] = cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
} }
bo_offset += CP_ME_TABLE_SIZE; bo_offset += CP_ME_TABLE_SIZE;
} }
...@@ -5847,52 +5847,53 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer) ...@@ -5847,52 +5847,53 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
if (buffer == NULL) if (buffer == NULL)
return; return;
buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
buffer[count++] = PACKET3_PREAMBLE_BEGIN_CLEAR_STATE; buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
buffer[count++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
buffer[count++] = 0x80000000; buffer[count++] = cpu_to_le32(0x80000000);
buffer[count++] = 0x80000000; buffer[count++] = cpu_to_le32(0x80000000);
for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
for (ext = sect->section; ext->extent != NULL; ++ext) { for (ext = sect->section; ext->extent != NULL; ++ext) {
if (sect->id == SECT_CONTEXT) { if (sect->id == SECT_CONTEXT) {
buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count); buffer[count++] =
buffer[count++] = ext->reg_index - 0xa000; cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
for (i = 0; i < ext->reg_count; i++) for (i = 0; i < ext->reg_count; i++)
buffer[count++] = ext->extent[i]; buffer[count++] = cpu_to_le32(ext->extent[i]);
} else { } else {
return; return;
} }
} }
} }
buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
buffer[count++] = PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START; buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
switch (rdev->family) { switch (rdev->family) {
case CHIP_BONAIRE: case CHIP_BONAIRE:
buffer[count++] = 0x16000012; buffer[count++] = cpu_to_le32(0x16000012);
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
break; break;
case CHIP_KAVERI: case CHIP_KAVERI:
buffer[count++] = 0x00000000; /* XXX */ buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
break; break;
case CHIP_KABINI: case CHIP_KABINI:
buffer[count++] = 0x00000000; /* XXX */ buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
break; break;
default: default:
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
break; break;
} }
buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
buffer[count++] = PACKET3_PREAMBLE_END_CLEAR_STATE; buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
buffer[count++] = PACKET3(PACKET3_CLEAR_STATE, 0); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
buffer[count++] = 0; buffer[count++] = cpu_to_le32(0);
} }
static void cik_init_pg(struct radeon_device *rdev) static void cik_init_pg(struct radeon_device *rdev)
......
drivers/gpu/drm/radeon/evergreen.c
View file @ 6ba81e53
...@@ -4019,7 +4019,7 @@ int sumo_rlc_init(struct radeon_device *rdev) ...@@ -4019,7 +4019,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
if (rdev->family >= CHIP_TAHITI) { if (rdev->family >= CHIP_TAHITI) {
/* SI */ /* SI */
for (i = 0; i < rdev->rlc.reg_list_size; i++) for (i = 0; i < rdev->rlc.reg_list_size; i++)
dst_ptr[i] = src_ptr[i]; dst_ptr[i] = cpu_to_le32(src_ptr[i]);
} else { } else {
/* ON/LN/TN */ /* ON/LN/TN */
/* format: /* format:
...@@ -4033,10 +4033,10 @@ int sumo_rlc_init(struct radeon_device *rdev) ...@@ -4033,10 +4033,10 @@ int sumo_rlc_init(struct radeon_device *rdev)
if (i < dws) if (i < dws)
data |= (src_ptr[i] >> 2) << 16; data |= (src_ptr[i] >> 2) << 16;
j = (((i - 1) * 3) / 2); j = (((i - 1) * 3) / 2);
dst_ptr[j] = data; dst_ptr[j] = cpu_to_le32(data);
} }
j = ((i * 3) / 2); j = ((i * 3) / 2);
dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER; dst_ptr[j] = cpu_to_le32(RLC_SAVE_RESTORE_LIST_END_MARKER);
} }
radeon_bo_kunmap(rdev->rlc.save_restore_obj); radeon_bo_kunmap(rdev->rlc.save_restore_obj);
radeon_bo_unreserve(rdev->rlc.save_restore_obj); radeon_bo_unreserve(rdev->rlc.save_restore_obj);
...@@ -4098,40 +4098,40 @@ int sumo_rlc_init(struct radeon_device *rdev) ...@@ -4098,40 +4098,40 @@ int sumo_rlc_init(struct radeon_device *rdev)
cik_get_csb_buffer(rdev, dst_ptr); cik_get_csb_buffer(rdev, dst_ptr);
} else if (rdev->family >= CHIP_TAHITI) { } else if (rdev->family >= CHIP_TAHITI) {
reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
dst_ptr[0] = upper_32_bits(reg_list_mc_addr); dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
dst_ptr[1] = lower_32_bits(reg_list_mc_addr); dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
dst_ptr[2] = rdev->rlc.clear_state_size; dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
si_get_csb_buffer(rdev, &dst_ptr[(256/4)]); si_get_csb_buffer(rdev, &dst_ptr[(256/4)]);
} else { } else {
reg_list_hdr_blk_index = 0; reg_list_hdr_blk_index = 0;
reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
data = upper_32_bits(reg_list_mc_addr); data = upper_32_bits(reg_list_mc_addr);
dst_ptr[reg_list_hdr_blk_index] = data; dst_ptr[reg_list_hdr_blk_index] = cpu_to_le32(data);
reg_list_hdr_blk_index++; reg_list_hdr_blk_index++;
for (i = 0; cs_data[i].section != NULL; i++) { for (i = 0; cs_data[i].section != NULL; i++) {
for (j = 0; cs_data[i].section[j].extent != NULL; j++) { for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
reg_num = cs_data[i].section[j].reg_count; reg_num = cs_data[i].section[j].reg_count;
data = reg_list_mc_addr & 0xffffffff; data = reg_list_mc_addr & 0xffffffff;
dst_ptr[reg_list_hdr_blk_index] = data; dst_ptr[reg_list_hdr_blk_index] = cpu_to_le32(data);
reg_list_hdr_blk_index++; reg_list_hdr_blk_index++;
data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff; data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
dst_ptr[reg_list_hdr_blk_index] = data; dst_ptr[reg_list_hdr_blk_index] = cpu_to_le32(data);
reg_list_hdr_blk_index++; reg_list_hdr_blk_index++;
data = 0x08000000 | (reg_num * 4); data = 0x08000000 | (reg_num * 4);
dst_ptr[reg_list_hdr_blk_index] = data; dst_ptr[reg_list_hdr_blk_index] = cpu_to_le32(data);
reg_list_hdr_blk_index++; reg_list_hdr_blk_index++;
for (k = 0; k < reg_num; k++) { for (k = 0; k < reg_num; k++) {
data = cs_data[i].section[j].extent[k]; data = cs_data[i].section[j].extent[k];
dst_ptr[reg_list_blk_index + k] = data; dst_ptr[reg_list_blk_index + k] = cpu_to_le32(data);
} }
reg_list_mc_addr += reg_num * 4; reg_list_mc_addr += reg_num * 4;
reg_list_blk_index += reg_num; reg_list_blk_index += reg_num;
} }
} }
dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER; dst_ptr[reg_list_hdr_blk_index] = cpu_to_le32(RLC_CLEAR_STATE_END_MARKER);
} }
radeon_bo_kunmap(rdev->rlc.clear_state_obj); radeon_bo_kunmap(rdev->rlc.clear_state_obj);
radeon_bo_unreserve(rdev->rlc.clear_state_obj); radeon_bo_unreserve(rdev->rlc.clear_state_obj);
......
drivers/gpu/drm/radeon/si.c
View file @ 6ba81e53
...@@ -5361,52 +5361,53 @@ void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer) ...@@ -5361,52 +5361,53 @@ void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
if (buffer == NULL) if (buffer == NULL)
return; return;
buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
buffer[count++] = PACKET3_PREAMBLE_BEGIN_CLEAR_STATE; buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
buffer[count++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
buffer[count++] = 0x80000000; buffer[count++] = cpu_to_le32(0x80000000);
buffer[count++] = 0x80000000; buffer[count++] = cpu_to_le32(0x80000000);
for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
for (ext = sect->section; ext->extent != NULL; ++ext) { for (ext = sect->section; ext->extent != NULL; ++ext) {
if (sect->id == SECT_CONTEXT) { if (sect->id == SECT_CONTEXT) {
buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count); buffer[count++] =
buffer[count++] = ext->reg_index - 0xa000; cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
for (i = 0; i < ext->reg_count; i++) for (i = 0; i < ext->reg_count; i++)
buffer[count++] = ext->extent[i]; buffer[count++] = cpu_to_le32(ext->extent[i]);
} else { } else {
return; return;
} }
} }
} }
buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
buffer[count++] = PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START; buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
switch (rdev->family) { switch (rdev->family) {
case CHIP_TAHITI: case CHIP_TAHITI:
case CHIP_PITCAIRN: case CHIP_PITCAIRN:
buffer[count++] = 0x2a00126a; buffer[count++] = cpu_to_le32(0x2a00126a);
break; break;
case CHIP_VERDE: case CHIP_VERDE:
buffer[count++] = 0x0000124a; buffer[count++] = cpu_to_le32(0x0000124a);
break; break;
case CHIP_OLAND: case CHIP_OLAND:
buffer[count++] = 0x00000082; buffer[count++] = cpu_to_le32(0x00000082);
break; break;
case CHIP_HAINAN: case CHIP_HAINAN:
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
break; break;
default: default:
buffer[count++] = 0x00000000; buffer[count++] = cpu_to_le32(0x00000000);
break; break;
} }
buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
buffer[count++] = PACKET3_PREAMBLE_END_CLEAR_STATE; buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
buffer[count++] = PACKET3(PACKET3_CLEAR_STATE, 0); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
buffer[count++] = 0; buffer[count++] = cpu_to_le32(0);
} }
static void si_init_pg(struct radeon_device *rdev) static void si_init_pg(struct radeon_device *rdev)
......
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