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Commit 6c6dc56c authored by Jesper Nilsson's avatar Jesper Nilsson
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CRIS v32: Add support for ETRAX FS and ARTPEC-3 for arch-v32/hwregs/eth_defs.h 

- A couple of fields have changed name:
reg_eth_rw_ga_lo.table -> tbl
reg_eth_rw_ga_hi.table -> tbl
reg_eth_rw_gen_ctrl.flow_ctrl_dis -> flow_ctrl

- Add some new register fields.
reg_eth_rw_gen_ctrl.gtxclk_out
reg_eth_rw_gen_ctrl.phyrst_n
reg_eth_rw_tr_ctrl.carrier_ext

- max_size in reg_eth_rw_rec_ctrl had the wrong size.

- Registers reg_eth_rw_mgm_ctrl and reg_eth_r_stat was reworked completely.
parent 8d073287
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Showing with 98 additions and 104 deletions
include/asm-cris/arch-v32/hwregs/eth_defs.h
View file @ 6c6dc56c
...@@ -3,12 +3,12 @@ ...@@ -3,12 +3,12 @@
/* /*
* This file is autogenerated from * This file is autogenerated from
* file: ../../inst/eth/rtl/eth_regs.r * file: eth.r
* id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
* last modfied: Mon Apr 11 16:07:03 2005 * last modfied: Mon Jan 9 06:06:41 2006
* *
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r * by /n/asic/design/tools/rdesc/rdes2c eth.r
* id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
* Any changes here will be lost. * Any changes here will be lost.
* *
* -*- buffer-read-only: t -*- * -*- buffer-read-only: t -*-
...@@ -116,26 +116,28 @@ typedef struct { ...@@ -116,26 +116,28 @@ typedef struct {
/* Register rw_ga_lo, scope eth, type rw */ /* Register rw_ga_lo, scope eth, type rw */
typedef struct { typedef struct {
unsigned int table : 32; unsigned int tbl : 32;
} reg_eth_rw_ga_lo; } reg_eth_rw_ga_lo;
#define REG_RD_ADDR_eth_rw_ga_lo 16 #define REG_RD_ADDR_eth_rw_ga_lo 16
#define REG_WR_ADDR_eth_rw_ga_lo 16 #define REG_WR_ADDR_eth_rw_ga_lo 16
/* Register rw_ga_hi, scope eth, type rw */ /* Register rw_ga_hi, scope eth, type rw */
typedef struct { typedef struct {
unsigned int table : 32; unsigned int tbl : 32;
} reg_eth_rw_ga_hi; } reg_eth_rw_ga_hi;
#define REG_RD_ADDR_eth_rw_ga_hi 20 #define REG_RD_ADDR_eth_rw_ga_hi 20
#define REG_WR_ADDR_eth_rw_ga_hi 20 #define REG_WR_ADDR_eth_rw_ga_hi 20
/* Register rw_gen_ctrl, scope eth, type rw */ /* Register rw_gen_ctrl, scope eth, type rw */
typedef struct { typedef struct {
unsigned int en : 1; unsigned int en : 1;
unsigned int phy : 2; unsigned int phy : 2;
unsigned int protocol : 1; unsigned int protocol : 1;
unsigned int loopback : 1; unsigned int loopback : 1;
unsigned int flow_ctrl_dis : 1; unsigned int flow_ctrl : 1;
unsigned int dummy1 : 26; unsigned int gtxclk_out : 1;
unsigned int phyrst_n : 1;
unsigned int dummy1 : 24;
} reg_eth_rw_gen_ctrl; } reg_eth_rw_gen_ctrl;
#define REG_RD_ADDR_eth_rw_gen_ctrl 24 #define REG_RD_ADDR_eth_rw_gen_ctrl 24
#define REG_WR_ADDR_eth_rw_gen_ctrl 24 #define REG_WR_ADDR_eth_rw_gen_ctrl 24
...@@ -150,22 +152,23 @@ typedef struct { ...@@ -150,22 +152,23 @@ typedef struct {
unsigned int oversize : 1; unsigned int oversize : 1;
unsigned int bad_crc : 1; unsigned int bad_crc : 1;
unsigned int duplex : 1; unsigned int duplex : 1;
unsigned int max_size : 1; unsigned int max_size : 16;
unsigned int dummy1 : 23; unsigned int dummy1 : 8;
} reg_eth_rw_rec_ctrl; } reg_eth_rw_rec_ctrl;
#define REG_RD_ADDR_eth_rw_rec_ctrl 28 #define REG_RD_ADDR_eth_rw_rec_ctrl 28
#define REG_WR_ADDR_eth_rw_rec_ctrl 28 #define REG_WR_ADDR_eth_rw_rec_ctrl 28
/* Register rw_tr_ctrl, scope eth, type rw */ /* Register rw_tr_ctrl, scope eth, type rw */
typedef struct { typedef struct {
unsigned int crc : 1; unsigned int crc : 1;
unsigned int pad : 1; unsigned int pad : 1;
unsigned int retry : 1; unsigned int retry : 1;
unsigned int ignore_col : 1; unsigned int ignore_col : 1;
unsigned int cancel : 1; unsigned int cancel : 1;
unsigned int hsh_delay : 1; unsigned int hsh_delay : 1;
unsigned int ignore_crs : 1; unsigned int ignore_crs : 1;
unsigned int dummy1 : 25; unsigned int carrier_ext : 1;
unsigned int dummy1 : 24;
} reg_eth_rw_tr_ctrl; } reg_eth_rw_tr_ctrl;
#define REG_RD_ADDR_eth_rw_tr_ctrl 32 #define REG_RD_ADDR_eth_rw_tr_ctrl 32
#define REG_WR_ADDR_eth_rw_tr_ctrl 32 #define REG_WR_ADDR_eth_rw_tr_ctrl 32
...@@ -180,13 +183,10 @@ typedef struct { ...@@ -180,13 +183,10 @@ typedef struct {
/* Register rw_mgm_ctrl, scope eth, type rw */ /* Register rw_mgm_ctrl, scope eth, type rw */
typedef struct { typedef struct {
unsigned int mdio : 1; unsigned int mdio : 1;
unsigned int mdoe : 1; unsigned int mdoe : 1;
unsigned int mdc : 1; unsigned int mdc : 1;
unsigned int phyclk : 1; unsigned int dummy1 : 29;
unsigned int txdata : 4;
unsigned int txen : 1;
unsigned int dummy1 : 23;
} reg_eth_rw_mgm_ctrl; } reg_eth_rw_mgm_ctrl;
#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 #define REG_RD_ADDR_eth_rw_mgm_ctrl 40
#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 #define REG_WR_ADDR_eth_rw_mgm_ctrl 40
...@@ -196,17 +196,8 @@ typedef struct { ...@@ -196,17 +196,8 @@ typedef struct {
unsigned int mdio : 1; unsigned int mdio : 1;
unsigned int exc_col : 1; unsigned int exc_col : 1;
unsigned int urun : 1; unsigned int urun : 1;
unsigned int phyclk : 1; unsigned int clk_125 : 1;
unsigned int txdata : 4; unsigned int dummy1 : 28;
unsigned int txen : 1;
unsigned int col : 1;
unsigned int crs : 1;
unsigned int txclk : 1;
unsigned int rxdata : 4;
unsigned int rxer : 1;
unsigned int rxdv : 1;
unsigned int rxclk : 1;
unsigned int dummy1 : 13;
} reg_eth_r_stat; } reg_eth_r_stat;
#define REG_RD_ADDR_eth_r_stat 44 #define REG_RD_ADDR_eth_r_stat 44
...@@ -274,83 +265,83 @@ typedef struct { ...@@ -274,83 +265,83 @@ typedef struct {
/* Register rw_intr_mask, scope eth, type rw */ /* Register rw_intr_mask, scope eth, type rw */
typedef struct { typedef struct {
unsigned int crc : 1; unsigned int crc : 1;
unsigned int align : 1; unsigned int align : 1;
unsigned int oversize : 1; unsigned int oversize : 1;
unsigned int congestion : 1; unsigned int congestion : 1;
unsigned int single_col : 1; unsigned int single_col : 1;
unsigned int mult_col : 1; unsigned int mult_col : 1;
unsigned int late_col : 1; unsigned int late_col : 1;
unsigned int deferred : 1; unsigned int deferred : 1;
unsigned int carrier_loss : 1; unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1; unsigned int sqe_test_err : 1;
unsigned int orun : 1; unsigned int orun : 1;
unsigned int urun : 1; unsigned int urun : 1;
unsigned int excessive_col : 1; unsigned int exc_col : 1;
unsigned int mdio : 1; unsigned int mdio : 1;
unsigned int dummy1 : 18; unsigned int dummy1 : 18;
} reg_eth_rw_intr_mask; } reg_eth_rw_intr_mask;
#define REG_RD_ADDR_eth_rw_intr_mask 76 #define REG_RD_ADDR_eth_rw_intr_mask 76
#define REG_WR_ADDR_eth_rw_intr_mask 76 #define REG_WR_ADDR_eth_rw_intr_mask 76
/* Register rw_ack_intr, scope eth, type rw */ /* Register rw_ack_intr, scope eth, type rw */
typedef struct { typedef struct {
unsigned int crc : 1; unsigned int crc : 1;
unsigned int align : 1; unsigned int align : 1;
unsigned int oversize : 1; unsigned int oversize : 1;
unsigned int congestion : 1; unsigned int congestion : 1;
unsigned int single_col : 1; unsigned int single_col : 1;
unsigned int mult_col : 1; unsigned int mult_col : 1;
unsigned int late_col : 1; unsigned int late_col : 1;
unsigned int deferred : 1; unsigned int deferred : 1;
unsigned int carrier_loss : 1; unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1; unsigned int sqe_test_err : 1;
unsigned int orun : 1; unsigned int orun : 1;
unsigned int urun : 1; unsigned int urun : 1;
unsigned int excessive_col : 1; unsigned int exc_col : 1;
unsigned int mdio : 1; unsigned int mdio : 1;
unsigned int dummy1 : 18; unsigned int dummy1 : 18;
} reg_eth_rw_ack_intr; } reg_eth_rw_ack_intr;
#define REG_RD_ADDR_eth_rw_ack_intr 80 #define REG_RD_ADDR_eth_rw_ack_intr 80
#define REG_WR_ADDR_eth_rw_ack_intr 80 #define REG_WR_ADDR_eth_rw_ack_intr 80
/* Register r_intr, scope eth, type r */ /* Register r_intr, scope eth, type r */
typedef struct { typedef struct {
unsigned int crc : 1; unsigned int crc : 1;
unsigned int align : 1; unsigned int align : 1;
unsigned int oversize : 1; unsigned int oversize : 1;
unsigned int congestion : 1; unsigned int congestion : 1;
unsigned int single_col : 1; unsigned int single_col : 1;
unsigned int mult_col : 1; unsigned int mult_col : 1;
unsigned int late_col : 1; unsigned int late_col : 1;
unsigned int deferred : 1; unsigned int deferred : 1;
unsigned int carrier_loss : 1; unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1; unsigned int sqe_test_err : 1;
unsigned int orun : 1; unsigned int orun : 1;
unsigned int urun : 1; unsigned int urun : 1;
unsigned int excessive_col : 1; unsigned int exc_col : 1;
unsigned int mdio : 1; unsigned int mdio : 1;
unsigned int dummy1 : 18; unsigned int dummy1 : 18;
} reg_eth_r_intr; } reg_eth_r_intr;
#define REG_RD_ADDR_eth_r_intr 84 #define REG_RD_ADDR_eth_r_intr 84
/* Register r_masked_intr, scope eth, type r */ /* Register r_masked_intr, scope eth, type r */
typedef struct { typedef struct {
unsigned int crc : 1; unsigned int crc : 1;
unsigned int align : 1; unsigned int align : 1;
unsigned int oversize : 1; unsigned int oversize : 1;
unsigned int congestion : 1; unsigned int congestion : 1;
unsigned int single_col : 1; unsigned int single_col : 1;
unsigned int mult_col : 1; unsigned int mult_col : 1;
unsigned int late_col : 1; unsigned int late_col : 1;
unsigned int deferred : 1; unsigned int deferred : 1;
unsigned int carrier_loss : 1; unsigned int carrier_loss : 1;
unsigned int sqe_test_err : 1; unsigned int sqe_test_err : 1;
unsigned int orun : 1; unsigned int orun : 1;
unsigned int urun : 1; unsigned int urun : 1;
unsigned int excessive_col : 1; unsigned int exc_col : 1;
unsigned int mdio : 1; unsigned int mdio : 1;
unsigned int dummy1 : 18; unsigned int dummy1 : 18;
} reg_eth_r_masked_intr; } reg_eth_r_masked_intr;
#define REG_RD_ADDR_eth_r_masked_intr 88 #define REG_RD_ADDR_eth_r_masked_intr 88
...@@ -360,12 +351,15 @@ enum { ...@@ -360,12 +351,15 @@ enum {
regk_eth_discard = 0x00000000, regk_eth_discard = 0x00000000,
regk_eth_ether = 0x00000000, regk_eth_ether = 0x00000000,
regk_eth_full = 0x00000001, regk_eth_full = 0x00000001,
regk_eth_gmii = 0x00000003,
regk_eth_gtxclk = 0x00000001,
regk_eth_half = 0x00000000, regk_eth_half = 0x00000000,
regk_eth_hsh = 0x00000001, regk_eth_hsh = 0x00000001,
regk_eth_mii = 0x00000001, regk_eth_mii = 0x00000001,
regk_eth_mii_arec = 0x00000002,
regk_eth_mii_clk = 0x00000000, regk_eth_mii_clk = 0x00000000,
regk_eth_mii_rec = 0x00000002,
regk_eth_no = 0x00000000, regk_eth_no = 0x00000000,
regk_eth_phyrst = 0x00000000,
regk_eth_rec = 0x00000001, regk_eth_rec = 0x00000001,
regk_eth_rw_ga_hi_default = 0x00000000, regk_eth_rw_ga_hi_default = 0x00000000,
regk_eth_rw_ga_lo_default = 0x00000000, regk_eth_rw_ga_lo_default = 0x00000000,
...@@ -377,8 +371,8 @@ enum { ...@@ -377,8 +371,8 @@ enum {
regk_eth_rw_ma1_lo_default = 0x00000000, regk_eth_rw_ma1_lo_default = 0x00000000,
regk_eth_rw_mgm_ctrl_default = 0x00000000, regk_eth_rw_mgm_ctrl_default = 0x00000000,
regk_eth_rw_test_ctrl_default = 0x00000000, regk_eth_rw_test_ctrl_default = 0x00000000,
regk_eth_size1518 = 0x00000000, regk_eth_size1518 = 0x000005ee,
regk_eth_size1522 = 0x00000001, regk_eth_size1522 = 0x000005f2,
regk_eth_yes = 0x00000001 regk_eth_yes = 0x00000001
}; };
#endif /* __eth_defs_h */ #endif /* __eth_defs_h */
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