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Commit 6e9f06ee authored by Helge Deller's avatar Helge Deller
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Revert "parisc: Use ldcw instruction for SMP spinlock release barrier" 

This reverts commit 9e5c6021.
No need to use the ldcw instruction as SMP spinlock release barrier.
Revert it to gain back speed again.
Signed-off-by: default avatarHelge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # v5.2+
parent 462fb756
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Inline Side-by-side
Showing with 24 additions and 39 deletions
arch/parisc/include/asm/spinlock.h
View file @ 6e9f06ee
...@@ -37,11 +37,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *x) ...@@ -37,11 +37,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
volatile unsigned int *a; volatile unsigned int *a;
a = __ldcw_align(x); a = __ldcw_align(x);
#ifdef CONFIG_SMP
(void) __ldcw(a);
#else
mb(); mb();
#endif
*a = 1; *a = 1;
} }
......
arch/parisc/kernel/entry.S
View file @ 6e9f06ee
...@@ -454,9 +454,8 @@ ...@@ -454,9 +454,8 @@
nop nop
LDREG 0(\ptp),\pte LDREG 0(\ptp),\pte
bb,<,n \pte,_PAGE_PRESENT_BIT,3f bb,<,n \pte,_PAGE_PRESENT_BIT,3f
LDCW 0(\tmp),\tmp1
b \fault b \fault
stw \spc,0(\tmp) stw,ma \spc,0(\tmp)
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif #endif
2: LDREG 0(\ptp),\pte 2: LDREG 0(\ptp),\pte
...@@ -465,22 +464,20 @@ ...@@ -465,22 +464,20 @@
.endm .endm
/* Release pa_tlb_lock lock without reloading lock address. */ /* Release pa_tlb_lock lock without reloading lock address. */
.macro tlb_unlock0 spc,tmp,tmp1 .macro tlb_unlock0 spc,tmp
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
98: or,COND(=) %r0,\spc,%r0 98: or,COND(=) %r0,\spc,%r0
LDCW 0(\tmp),\tmp1 stw,ma \spc,0(\tmp)
or,COND(=) %r0,\spc,%r0
stw \spc,0(\tmp)
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif #endif
.endm .endm
/* Release pa_tlb_lock lock. */ /* Release pa_tlb_lock lock. */
.macro tlb_unlock1 spc,tmp,tmp1 .macro tlb_unlock1 spc,tmp
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
98: load_pa_tlb_lock \tmp 98: load_pa_tlb_lock \tmp
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
tlb_unlock0 \spc,\tmp,\tmp1 tlb_unlock0 \spc,\tmp
#endif #endif
.endm .endm
...@@ -1163,7 +1160,7 @@ dtlb_miss_20w: ...@@ -1163,7 +1160,7 @@ dtlb_miss_20w:
idtlbt pte,prot idtlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1189,7 +1186,7 @@ nadtlb_miss_20w: ...@@ -1189,7 +1186,7 @@ nadtlb_miss_20w:
idtlbt pte,prot idtlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1223,7 +1220,7 @@ dtlb_miss_11: ...@@ -1223,7 +1220,7 @@ dtlb_miss_11:
mtsp t1, %sr1 /* Restore sr1 */ mtsp t1, %sr1 /* Restore sr1 */
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1256,7 +1253,7 @@ nadtlb_miss_11: ...@@ -1256,7 +1253,7 @@ nadtlb_miss_11:
mtsp t1, %sr1 /* Restore sr1 */ mtsp t1, %sr1 /* Restore sr1 */
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1285,7 +1282,7 @@ dtlb_miss_20: ...@@ -1285,7 +1282,7 @@ dtlb_miss_20:
idtlbt pte,prot idtlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1313,7 +1310,7 @@ nadtlb_miss_20: ...@@ -1313,7 +1310,7 @@ nadtlb_miss_20:
idtlbt pte,prot idtlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1420,7 +1417,7 @@ itlb_miss_20w: ...@@ -1420,7 +1417,7 @@ itlb_miss_20w:
iitlbt pte,prot iitlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1444,7 +1441,7 @@ naitlb_miss_20w: ...@@ -1444,7 +1441,7 @@ naitlb_miss_20w:
iitlbt pte,prot iitlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1478,7 +1475,7 @@ itlb_miss_11: ...@@ -1478,7 +1475,7 @@ itlb_miss_11:
mtsp t1, %sr1 /* Restore sr1 */ mtsp t1, %sr1 /* Restore sr1 */
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1502,7 +1499,7 @@ naitlb_miss_11: ...@@ -1502,7 +1499,7 @@ naitlb_miss_11:
mtsp t1, %sr1 /* Restore sr1 */ mtsp t1, %sr1 /* Restore sr1 */
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1532,7 +1529,7 @@ itlb_miss_20: ...@@ -1532,7 +1529,7 @@ itlb_miss_20:
iitlbt pte,prot iitlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1552,7 +1549,7 @@ naitlb_miss_20: ...@@ -1552,7 +1549,7 @@ naitlb_miss_20:
iitlbt pte,prot iitlbt pte,prot
tlb_unlock1 spc,t0,t1 tlb_unlock1 spc,t0
rfir rfir
nop nop
...@@ -1582,7 +1579,7 @@ dbit_trap_20w: ...@@ -1582,7 +1579,7 @@ dbit_trap_20w:
idtlbt pte,prot idtlbt pte,prot
tlb_unlock0 spc,t0,t1 tlb_unlock0 spc,t0
rfir rfir
nop nop
#else #else
...@@ -1608,7 +1605,7 @@ dbit_trap_11: ...@@ -1608,7 +1605,7 @@ dbit_trap_11:
mtsp t1, %sr1 /* Restore sr1 */ mtsp t1, %sr1 /* Restore sr1 */
tlb_unlock0 spc,t0,t1 tlb_unlock0 spc,t0
rfir rfir
nop nop
...@@ -1628,7 +1625,7 @@ dbit_trap_20: ...@@ -1628,7 +1625,7 @@ dbit_trap_20:
idtlbt pte,prot idtlbt pte,prot
tlb_unlock0 spc,t0,t1 tlb_unlock0 spc,t0
rfir rfir
nop nop
#endif #endif
......
arch/parisc/kernel/syscall.S
View file @ 6e9f06ee
...@@ -640,9 +640,7 @@ cas_action: ...@@ -640,9 +640,7 @@ cas_action:
sub,<> %r28, %r25, %r0 sub,<> %r28, %r25, %r0
2: stw %r24, 0(%r26) 2: stw %r24, 0(%r26)
/* Free lock */ /* Free lock */
#ifdef CONFIG_SMP sync
LDCW 0(%sr2,%r20), %r1 /* Barrier */
#endif
stw %r20, 0(%sr2,%r20) stw %r20, 0(%sr2,%r20)
#if ENABLE_LWS_DEBUG #if ENABLE_LWS_DEBUG
/* Clear thread register indicator */ /* Clear thread register indicator */
...@@ -657,9 +655,7 @@ cas_action: ...@@ -657,9 +655,7 @@ cas_action:
3: 3:
/* Error occurred on load or store */ /* Error occurred on load or store */
/* Free lock */ /* Free lock */
#ifdef CONFIG_SMP sync
LDCW 0(%sr2,%r20), %r1 /* Barrier */
#endif
stw %r20, 0(%sr2,%r20) stw %r20, 0(%sr2,%r20)
#if ENABLE_LWS_DEBUG #if ENABLE_LWS_DEBUG
stw %r0, 4(%sr2,%r20) stw %r0, 4(%sr2,%r20)
...@@ -861,9 +857,7 @@ cas2_action: ...@@ -861,9 +857,7 @@ cas2_action:
cas2_end: cas2_end:
/* Free lock */ /* Free lock */
#ifdef CONFIG_SMP sync
LDCW 0(%sr2,%r20), %r1 /* Barrier */
#endif
stw %r20, 0(%sr2,%r20) stw %r20, 0(%sr2,%r20)
/* Enable interrupts */ /* Enable interrupts */
ssm PSW_SM_I, %r0 ssm PSW_SM_I, %r0
...@@ -874,9 +868,7 @@ cas2_end: ...@@ -874,9 +868,7 @@ cas2_end:
22: 22:
/* Error occurred on load or store */ /* Error occurred on load or store */
/* Free lock */ /* Free lock */
#ifdef CONFIG_SMP sync
LDCW 0(%sr2,%r20), %r1 /* Barrier */
#endif
stw %r20, 0(%sr2,%r20) stw %r20, 0(%sr2,%r20)
ssm PSW_SM_I, %r0 ssm PSW_SM_I, %r0
ldo 1(%r0),%r28 ldo 1(%r0),%r28
......
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