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Commit 6ef5fb2c authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
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sh: intc - add a clear register to struct intc_prio_reg 

We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent d6aee69c
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Showing with 105 additions and 97 deletions
arch/sh/kernel/cpu/irq/intc.c
View file @ 6ef5fb2c
...@@ -59,14 +59,14 @@ static inline unsigned int set_prio_field(struct intc_desc *desc, ...@@ -59,14 +59,14 @@ static inline unsigned int set_prio_field(struct intc_desc *desc,
static void disable_prio_16(struct intc_desc *desc, unsigned int data) static void disable_prio_16(struct intc_desc *desc, unsigned int data)
{ {
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr); ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
} }
static void enable_prio_16(struct intc_desc *desc, unsigned int data) static void enable_prio_16(struct intc_desc *desc, unsigned int data)
{ {
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
unsigned int prio = _INTC_VALUE(data); unsigned int prio = _INTC_VALUE(data);
ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr); ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
...@@ -74,14 +74,14 @@ static void enable_prio_16(struct intc_desc *desc, unsigned int data) ...@@ -74,14 +74,14 @@ static void enable_prio_16(struct intc_desc *desc, unsigned int data)
static void disable_prio_32(struct intc_desc *desc, unsigned int data) static void disable_prio_32(struct intc_desc *desc, unsigned int data)
{ {
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr); ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
} }
static void enable_prio_32(struct intc_desc *desc, unsigned int data) static void enable_prio_32(struct intc_desc *desc, unsigned int data)
{ {
unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg; unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg;
unsigned int prio = _INTC_VALUE(data); unsigned int prio = _INTC_VALUE(data);
ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr); ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
......
arch/sh/kernel/cpu/sh3/setup-sh7705.c
View file @ 6ef5fb2c
...@@ -73,14 +73,14 @@ static struct intc_prio priorities[] = { ...@@ -73,14 +73,14 @@ static struct intc_prio priorities[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } }, { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } }, { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
{ 0xa4080000, 16, 4, /* IPRF */ { 0, 0, USB } }, { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },
{ 0xa4080002, 16, 4, /* IPRG */ { TPU0, TPU1 } }, { 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },
{ 0xa4080004, 16, 4, /* IPRH */ { TPU2, TPU3 } }, { 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },
}; };
......
arch/sh/kernel/cpu/sh3/setup-sh770x.c
View file @ 6ef5fb2c
...@@ -89,22 +89,22 @@ static struct intc_prio priorities[] = { ...@@ -89,22 +89,22 @@ static struct intc_prio priorities[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709) defined(CONFIG_CPU_SUBTYPE_SH7709)
{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
{ 0xa400001a, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } }, { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
#endif #endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709) defined(CONFIG_CPU_SUBTYPE_SH7709)
{ 0xa4000018, 16, 4, /* IPRD */ { PINT07, PINT815, } }, { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
{ 0xa400001a, 16, 4, /* IPRE */ { 0, SCIF0 } }, { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
#endif #endif
#if defined(CONFIG_CPU_SUBTYPE_SH7707) #if defined(CONFIG_CPU_SUBTYPE_SH7707)
{ 0xa400001c, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } }, { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
#endif #endif
}; };
......
arch/sh/kernel/cpu/sh3/setup-sh7710.c
View file @ 6ef5fb2c
...@@ -86,18 +86,18 @@ static struct intc_prio priorities[] = { ...@@ -86,18 +86,18 @@ static struct intc_prio priorities[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
{ 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
{ 0xa4080000, 16, 4, /* IPRF */ { 0, DMAC2 } }, { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
#ifdef CONFIG_CPU_SUBTYPE_SH7710 #ifdef CONFIG_CPU_SUBTYPE_SH7710
{ 0xa4080000, 16, 4, /* IPRF */ { IPSEC } }, { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
#endif #endif
{ 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
{ 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
{ 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
}; };
static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
......
arch/sh/kernel/cpu/sh4/setup-sh7750.c
View file @ 6ef5fb2c
...@@ -133,11 +133,11 @@ static struct intc_prio priorities[] = { ...@@ -133,11 +133,11 @@ static struct intc_prio priorities[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
{ 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
{ 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
{ 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
TMU4, TMU3, TMU4, TMU3,
PCIC1, PCIC0_PCISERR } }, PCIC1, PCIC0_PCISERR } },
}; };
......
arch/sh/kernel/cpu/sh4/setup-sh7760.c
View file @ 6ef5fb2c
...@@ -118,16 +118,16 @@ static struct intc_mask_reg mask_registers[] = { ...@@ -118,16 +118,16 @@ static struct intc_mask_reg mask_registers[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
{ 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
{ 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
{ 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
{ 0xfe080000, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xfe080004, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1, { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
HAC0, HAC1, I2C0, I2C1 } }, HAC0, HAC1, I2C0, I2C1 } },
{ 0xfe080008, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0, { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
SCIF1, SCIF2, SIM, HSPI } }, SCIF1, SCIF2, SIM, HSPI } },
{ 0xfe08000c, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0, { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
MFI, 0, ADC, CMT } }, MFI, 0, ADC, CMT } },
}; };
......
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
View file @ 6ef5fb2c
...@@ -169,19 +169,19 @@ static struct intc_mask_reg mask_registers[] = { ...@@ -169,19 +169,19 @@ static struct intc_mask_reg mask_registers[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
{ 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
{ 0xa4080008, 16, 4, /* IPRC */ { } }, { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
{ 0xa408000c, 16, 4, /* IPRD */ { } }, { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
{ 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
{ 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
{ 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
{ 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
{ 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
{ 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } }, { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
{ 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
{ 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
{ 0xa4140010, 32, 4, /* INTPRI00 */ { 0xa4140010, 0, 32, 4, /* INTPRI00 */
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
}; };
......
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
View file @ 6ef5fb2c
...@@ -181,15 +181,17 @@ static struct intc_mask_reg mask_registers[] = { ...@@ -181,15 +181,17 @@ static struct intc_mask_reg mask_registers[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } }, { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
{ 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, TMU2, TMU2_TICPI } },
{ 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
{ 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } }, { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
{ 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } }, { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
{ 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
PCISERR, PCIINTA, } },
{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
PCIINTD, PCIC5 } }, PCIINTD, PCIC5 } },
{ 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } }, { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
{ 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } }, { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
}; };
static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities, static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
...@@ -210,7 +212,7 @@ static struct intc_mask_reg irq_mask_registers[] = { ...@@ -210,7 +212,7 @@ static struct intc_mask_reg irq_mask_registers[] = {
}; };
static struct intc_prio_reg irq_prio_registers[] = { static struct intc_prio_reg irq_prio_registers[] = {
{ 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } }, IRQ4, IRQ5, IRQ6, IRQ7 } },
}; };
......
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
View file @ 6ef5fb2c
...@@ -206,19 +206,22 @@ static struct intc_mask_reg mask_registers[] = { ...@@ -206,19 +206,22 @@ static struct intc_mask_reg mask_registers[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
IRQ4, IRQ5, IRQ6, IRQ7 } }, IRQ4, IRQ5, IRQ6, IRQ7 } },
{ 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } }, { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
{ 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } }, TMU2, TMU2_TICPI } },
{ 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
{ 0xffd4000c, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } }, { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
{ 0xffd40010, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } }, SCIF2, SCIF3 } },
{ 0xffd40014, 32, 8, /* INT2PRI5 */ { HAC0, HAC1, PCISERR, PCIINTA } }, { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
{ 0xffd40018, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC, { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
PCISERR, PCIINTA } },
{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
PCIINTD, PCIC5 } }, PCIINTD, PCIC5 } },
{ 0xffd4001c, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } }, { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
{ 0xffd40020, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } }, { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
{ 0xffd40024, 32, 8, /* INT2PRI9 */ { DU, GDTA, } }, { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
}; };
static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities, static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities,
......
arch/sh/kernel/cpu/sh4a/setup-shx3.c
View file @ 6ef5fb2c
...@@ -192,17 +192,20 @@ static struct intc_mask_reg mask_registers[] = { ...@@ -192,17 +192,20 @@ static struct intc_mask_reg mask_registers[] = {
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xfe410010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
{ 0xfe410800, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
TMU3, TMU2, TMU1, TMU0 } }, TMU3, TMU2, TMU1, TMU0 } },
{ 0xfe410804, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0, { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
SCIF3, SCIF2, SCIF1, SCIF0 } }, SCIF3, SCIF2,
{ 0xfe410808, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, PCII56789, PCII4, SCIF1, SCIF0 } },
PCII3, PCII2, PCII1, PCII0 } }, { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
{ 0xfe41080c, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0, PCII56789, PCII4,
PCII3, PCII2,
PCII1, PCII0 } },
{ 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
VIN1, VIN0, IIC, DU} }, VIN1, VIN0, IIC, DU} },
{ 0xfe410810, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3, { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
GPIO2, GPIO1, GPIO0, IRM } }, GPIO2, GPIO1, GPIO0, IRM } },
}; };
......
include/asm-sh/hw_irq.h
View file @ 6ef5fb2c
...@@ -53,7 +53,7 @@ struct intc_mask_reg { ...@@ -53,7 +53,7 @@ struct intc_mask_reg {
}; };
struct intc_prio_reg { struct intc_prio_reg {
unsigned long reg, reg_width, field_width; unsigned long set_reg, clr_reg, reg_width, field_width;
intc_enum enum_ids[16]; intc_enum enum_ids[16];
}; };
......
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