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Commit 6f79eed8 authored by Xander Huff's avatar Xander Huff Committed by David S. Miller
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net/macb: Fix comments to meet style guidelines 

Change comments to not exceed 80 characters per line.
Update block comments in macb.h to start on the line after /*.
Signed-off-by: default avatarXander Huff <xander.huff@ni.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 331b9ab8
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Showing with 284 additions and 450 deletions
drivers/net/ethernet/cadence/macb.h
View file @ 6f79eed8
...@@ -82,159 +82,52 @@ ...@@ -82,159 +82,52 @@
#define GEM_SA4B 0x00A0 /* Specific4 Bottom */ #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define GEM_SA4T 0x00A4 /* Specific4 Top */ #define GEM_SA4T 0x00A4 /* Specific4 Top */
#define GEM_OTX 0x0100 /* Octets transmitted */ #define GEM_OTX 0x0100 /* Octets transmitted */
#define GEM_OCTTXL 0x0100 /* Octets transmitted #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
* [31:0] #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
*/ #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
#define GEM_OCTTXH 0x0104 /* Octets transmitted #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
* [47:32] #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
*/ #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
#define GEM_TXCNT 0x0108 /* Error-free Frames #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
* Transmitted counter #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
*/ #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
#define GEM_TXBCCNT 0x010c /* Error-free Broadcast #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
* Frames counter #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
*/ #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
#define GEM_TXMCCNT 0x0110 /* Error-free Multicast #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
* Frames counter #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
*/ #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
#define GEM_TXPAUSECNT 0x0114 /* Pause Frames #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
* Transmitted Counter #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
*/ #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
#define GEM_TX64CNT 0x0118 /* Error-free 64 byte #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
* Frames Transmitted #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
* counter
*/
#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
* Frames Transmitted
* counter
*/
#define GEM_TX128CNT 0x0120 /* Error-free 128-255
* byte Frames
* Transmitted counter
*/
#define GEM_TX256CNT 0x0124 /* Error-free 256-511
* byte Frames
* transmitted counter
*/
#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
* byte Frames
* transmitted counter
*/
#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
* byte Frames
* transmitted counter
*/
#define GEM_TX1519CNT 0x0130 /* Error-free larger than
* 1519 byte Frames
* tranmitted counter
*/
#define GEM_TXURUNCNT 0x0134 /* TX under run error
* counter
*/
#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
* Counter
*/
#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
* Frame Counter
*/
#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
* Frame Counter
*/
#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
* Counter
*/
#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
* Frame Counter
*/
#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
* Counter
*/
#define GEM_ORX 0x0150 /* Octets received */ #define GEM_ORX 0x0150 /* Octets received */
#define GEM_OCTRXL 0x0150 /* Octets received #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
* [31:0] #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
*/ #define GEM_RXCNT 0x0158 /* Frames Received Counter */
#define GEM_OCTRXH 0x0154 /* Octets received #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
* [47:32] #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
*/ #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
#define GEM_RXCNT 0x0158 /* Error-free Frames #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
* Received Counter #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
*/ #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
* Frames Received #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
* Counter #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
*/ #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
* Frames Received #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
* Counter #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
*/ #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
* Frames Received #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
* Counter #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
*/ #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
#define GEM_RX64CNT 0x0168 /* Error-free 64 byte #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
* Frames Received #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
* Counter #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
*/ #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
* Frames Received
* Counter
*/
#define GEM_RX128CNT 0x0170 /* Error-free 128-255
* byte Frames Received
* Counter
*/
#define GEM_RX256CNT 0x0174 /* Error-free 256-511
* byte Frames Received
* Counter
*/
#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
* byte Frames Received
* Counter
*/
#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
* byte Frames Received
* Counter
*/
#define GEM_RX1519CNT 0x0180 /* Error-free larger than
* 1519 Frames Received
* Counter
*/
#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
* Received Counter
*/
#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
* Received Counter
*/
#define GEM_RXJABCNT 0x018c /* Jabbers Received
* Counter
*/
#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
* Error Counter
*/
#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
* Counter
*/
#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
* Counter
*/
#define GEM_RXALIGNCNT 0x019c /* Alignment Error
* Counter
*/
#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
* Counter
*/
#define GEM_RXORCNT 0x01a4 /* Receive Overrun
* Counter
*/
#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
* Error Counter
*/
#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
* Counter
*/
#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
* Counter
*/
#define GEM_DCFG1 0x0280 /* Design Config 1 */ #define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */ #define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */ #define GEM_DCFG3 0x0288 /* Design Config 3 */
...@@ -275,9 +168,7 @@ ...@@ -275,9 +168,7 @@
#define MACB_THALT_SIZE 1 #define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
#define MACB_NCR_TPF_SIZE 1 #define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
* pause frame
*/
#define MACB_TZQ_SIZE 1 #define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */ /* Bitfields in NCFGR */
...@@ -299,9 +190,7 @@ ...@@ -299,9 +190,7 @@
#define MACB_UNI_SIZE 1 #define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
#define MACB_BIG_SIZE 1 #define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9 /* External address match #define MACB_EAE_OFFSET 9 /* External address match enable */
* enable
*/
#define MACB_EAE_SIZE 1 #define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10 #define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2 #define MACB_CLK_SIZE 2
...@@ -313,9 +202,7 @@ ...@@ -313,9 +202,7 @@
#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
#define MACB_RBOF_SIZE 2 #define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16 /* Length field error frame #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
* discard
*/
#define MACB_RLCE_SIZE 1 #define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17 /* FCS remove */ #define MACB_DRFCS_OFFSET 17 /* FCS remove */
#define MACB_DRFCS_SIZE 1 #define MACB_DRFCS_SIZE 1
...@@ -335,41 +222,22 @@ ...@@ -335,41 +222,22 @@
#define GEM_RXCOEN_SIZE 1 #define GEM_RXCOEN_SIZE 1
/* Constants for data bus width. */ /* Constants for data bus width. */
#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
* width #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
*/ #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
* width
*/
#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
* width
*/
/* Bitfields in DMACFG. */ /* Bitfields in DMACFG. */
#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
* DMA data operations
*/
#define GEM_FBLDO_SIZE 5 #define GEM_FBLDO_SIZE 5
#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable #define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */
* for packet data accesses
*/
#define GEM_ENDIA_SIZE 1 #define GEM_ENDIA_SIZE 1
#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
* memory size select
*/
#define GEM_RXBMS_SIZE 2 #define GEM_RXBMS_SIZE 2
#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
* memory size select
*/
#define GEM_TXPBMS_SIZE 1 #define GEM_TXPBMS_SIZE 1
#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
* UDP checksum generation
* offload enable
*/
#define GEM_TXCOEN_SIZE 1 #define GEM_TXCOEN_SIZE 1
#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
* AHB system memory
*/
#define GEM_RXBS_SIZE 8 #define GEM_RXBS_SIZE 8
#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
#define GEM_DDRP_SIZE 1 #define GEM_DDRP_SIZE 1
...@@ -378,13 +246,9 @@ ...@@ -378,13 +246,9 @@
/* Bitfields in NSR */ /* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1 #define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1 /* status of the mdio_in #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
* pin
*/
#define MACB_MDIO_SIZE 1 #define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2 /* The PHY management logic is #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
* idle (i.e. has completed)
*/
#define MACB_IDLE_SIZE 1 #define MACB_IDLE_SIZE 1
/* Bitfields in TSR */ /* Bitfields in TSR */
...@@ -396,9 +260,7 @@ ...@@ -396,9 +260,7 @@
#define MACB_TSR_RLE_SIZE 1 #define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3 /* Transmit go */ #define MACB_TGO_OFFSET 3 /* Transmit go */
#define MACB_TGO_SIZE 1 #define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4 /* Transmit frame corruption #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
* due to AHB error
*/
#define MACB_BEX_SIZE 1 #define MACB_BEX_SIZE 1
#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
...@@ -424,43 +286,23 @@ ...@@ -424,43 +286,23 @@
#define MACB_RXUBR_SIZE 1 #define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3 /* TX used bit read */ #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
#define MACB_TXUBR_SIZE 1 #define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
* under run interrupt
*/
#define MACB_ISR_TUND_SIZE 1 #define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
* or late collision interrupt
*/
#define MACB_ISR_RLE_SIZE 1 #define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6 /* Enable transmit frame #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
* corruption due to AHB error
* interrupt
*/
#define MACB_TXERR_SIZE 1 #define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
* interrupt
*/
#define MACB_TCOMP_SIZE 1 #define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9 /* Enable link change #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
* interrupt
*/
#define MACB_ISR_LINK_SIZE 1 #define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
* interrupt
*/
#define MACB_ISR_ROVR_SIZE 1 #define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
* interrupt
*/
#define MACB_HRESP_SIZE 1 #define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12 /* Enable pause frame with #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
* non-zero pause quantum
* interrupt
*/
#define MACB_PFR_SIZE 1 #define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13 /* Enable pause time zero #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
* interrupt
*/
#define MACB_PTZ_SIZE 1 #define MACB_PTZ_SIZE 1
/* Bitfields in MAN */ /* Bitfields in MAN */
...@@ -472,13 +314,9 @@ ...@@ -472,13 +314,9 @@
#define MACB_REGA_SIZE 5 #define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23 /* PHY address */ #define MACB_PHYA_OFFSET 23 /* PHY address */
#define MACB_PHYA_SIZE 5 #define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
* is write.
*/
#define MACB_RW_SIZE 2 #define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30 /* Must be written to 1 for #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
* Clause 22 operation
*/
#define MACB_SOF_SIZE 2 #define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */ /* Bitfields in USRIO (AVR32) */
...@@ -597,8 +435,7 @@ ...@@ -597,8 +435,7 @@
#define queue_writel(queue, reg, value) \ #define queue_writel(queue, reg, value) \
__raw_writel((value), (queue)->bp->regs + (queue)->reg) __raw_writel((value), (queue)->bp->regs + (queue)->reg)
/* /* Conditional GEM/MACB macros. These perform the operation to the correct
* Conditional GEM/MACB macros. These perform the operation to the correct
* register dependent on whether the device is a GEM or a MACB. For registers * register dependent on whether the device is a GEM or a MACB. For registers
* and bitfields that are common across both devices, use macb_{read,write}l * and bitfields that are common across both devices, use macb_{read,write}l
* to avoid the cost of the conditional. * to avoid the cost of the conditional.
...@@ -621,8 +458,7 @@ ...@@ -621,8 +458,7 @@
__v; \ __v; \
}) })
/** /* struct macb_dma_desc - Hardware DMA descriptor
* struct macb_dma_desc - Hardware DMA descriptor
* @addr: DMA address of data buffer * @addr: DMA address of data buffer
* @ctrl: Control and status bits * @ctrl: Control and status bits
*/ */
...@@ -711,8 +547,7 @@ struct macb_dma_desc { ...@@ -711,8 +547,7 @@ struct macb_dma_desc {
/* limit RX checksum offload to TCP and UDP packets */ /* limit RX checksum offload to TCP and UDP packets */
#define GEM_RX_CSUM_CHECKED_MASK 2 #define GEM_RX_CSUM_CHECKED_MASK 2
/** /* struct macb_tx_skb - data about an skb which is being transmitted
* struct macb_tx_skb - data about an skb which is being transmitted
* @skb: skb currently being transmitted, only set for the last buffer * @skb: skb currently being transmitted, only set for the last buffer
* of the frame * of the frame
* @mapping: DMA address of the skb's fragment buffer * @mapping: DMA address of the skb's fragment buffer
...@@ -727,8 +562,7 @@ struct macb_tx_skb { ...@@ -727,8 +562,7 @@ struct macb_tx_skb {
bool mapped_as_page; bool mapped_as_page;
}; };
/* /* Hardware-collected statistics. Used when updating the network
* Hardware-collected statistics. Used when updating the network
* device stats by a periodic timer. * device stats by a periodic timer.
*/ */
struct macb_stats { struct macb_stats {
......
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