Commit 73184130 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 4.14 for MIPS; below a summary of
  the non-merge commits:

  CM:
   - Rename mips_cm_base to mips_gcr_base
   - Specify register size when generating accessors
   - Use BIT/GENMASK for register fields, order & drop shifts
   - Add cluster & block args to mips_cm_lock_other()

  CPC:
   - Use common CPS accessor generation macros
   - Use BIT/GENMASK for register fields, order & drop shifts
   - Introduce register modify (set/clear/change) accessors
   - Use change_*, set_* & clear_* where appropriate
   - Add CM/CPC 3.5 register definitions
   - Use GlobalNumber macros rather than magic numbers
   - Have asm/mips-cps.h include CM & CPC headers
   - Cluster support for topology functions
   - Detect CPUs in secondary clusters

  CPS:
   - Read GIC_VL_IDENT directly, not via irqchip driver

  DMA:
   - Consolidate coherent and non-coherent dma_alloc code
   - Don't use dma_cache_sync to implement fd_cacheflush

  FPU emulation / FP assist code:
   - Another series of 14 commits fixing corner cases such as NaN
     propgagation and other special input values.
   - Zero bits 32-63 of the result for a CLASS.D instruction.
   - Enhanced statics via debugfs
   - Do not use bools for arithmetic. GCC 7.1 moans about this.
   - Correct user fault_addr type

  Generic MIPS:
   - Enhancement of stack backtraces
   - Cleanup from non-existing options
   - Handle non word sized instructions when examining frame
   - Fix detection and decoding of ADDIUSP instruction
   - Fix decoding of SWSP16 instruction
   - Refactor handling of stack pointer in get_frame_info
   - Remove unreachable code from force_fcr31_sig()
   - Convert to using %pOF instead of full_name
   - Remove the R6000 support.
   - Move FP code from *_switch.S to *_fpu.S
   - Remove unused ST_OFF from r2300_switch.S
   - Allow platform to specify multiple its.S files
   - Add #includes to various files to ensure code builds reliable and
     without warning..
   - Remove __invalidate_kernel_vmap_range
   - Remove plat_timer_setup
   - Declare various variables & functions static
   - Abstract CPU core & VP(E) ID access through accessor functions
   - Store core & VP IDs in GlobalNumber-style variable
   - Unify checks for sibling CPUs
   - Add CPU cluster number accessors
   - Prevent direct use of generic_defconfig
   - Make CONFIG_MIPS_MT_SMP default y
   - Add __ioread64_copy
   - Remove unnecessary inclusions of linux/irqchip/mips-gic.h

  GIC:
   - Introduce asm/mips-gic.h with accessor functions
   - Use new GIC accessor functions in mips-gic-timer
   - Remove counter access functions from irq-mips-gic.c
   - Remove gic_read_local_vp_id() from irq-mips-gic.c
   - Simplify shared interrupt pending/mask reads in irq-mips-gic.c
   - Simplify gic_local_irq_domain_map() in irq-mips-gic.c
   - Drop gic_(re)set_mask() functions in irq-mips-gic.c
   - Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
     gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
   - Convert remaining shared reg access, local int mask access and
     remaining local reg access to new accessors
   - Move GIC_LOCAL_INT_* to asm/mips-gic.h
   - Remove GIC_CPU_INT* macros from irq-mips-gic.c
   - Move various definitions to the driver
   - Remove gic_get_usm_range()
   - Remove __gic_irq_dispatch() forward declaration
   - Remove gic_init()
   - Use mips_gic_present() in place of gic_present and remove
     gic_present
   - Move gic_get_c0_*_int() to asm/mips-gic.h
   - Remove linux/irqchip/mips-gic.h
   - Inline __gic_init()
   - Inline gic_basic_init()
   - Make pcpu_masks a per-cpu variable
   - Use pcpu_masks to avoid reading GIC_SH_MASK*
   - Clean up mti, reserved-cpu-vectors handling
   - Use cpumask_first_and() in gic_set_affinity()
   - Let the core set struct irq_common_data affinity

  microMIPS:
   - Fix microMIPS stack unwinding on big endian systems

  MIPS-GIC:
   - SYNC after enabling GIC region

  NUMA:
   - Remove the unused parent_node() macro

  R6:
   - Constify r2_decoder_tables
   - Add accessor & bit definitions for GlobalNumber

  SMP:
   - Constify smp ops
   - Allow boot_secondary SMP op to return errors

  VDSO:
   - Drop gic_get_usm_range() usage
   - Avoid use of linux/irqchip/mips-gic.h

  Platform changes:

  Alchemy:
   - Add devboard machine type to cpuinfo
   - update cpu feature overrides
   - Threaded carddetect irqs for devboards

  AR7:
   - allow NULL clock for clk_get_rate

  BCM63xx:
   - Fix ENETDMA_6345_MAXBURST_REG offset
   - Allow NULL clock for clk_get_rate

  CI20:
   - Enable GPIO and RTC drivers in defconfig
   - Add ethernet and fixed-regulator nodes to DTS

  Generic platform:
   - Move Boston and NI 169445 FIT image source to their own files
   - Include asm/bootinfo.h for plat_fdt_relocated()
   - Include asm/time.h for get_c0_*_int()
   - Include asm/bootinfo.h for plat_fdt_relocated()
   - Include asm/time.h for get_c0_*_int()
   - Allow filtering enabled boards by requirements
   - Don't explicitly disable CONFIG_USB_SUPPORT
   - Bump default NR_CPUS to 16

  JZ4700:
   - Probe the jz4740-rtc driver from devicetree

  Lantiq:
   - Drop check of boot select from the spi-falcon driver.
   - Drop check of boot select from the lantiq-flash MTD driver.
   - Access boot cause register in the watchdog driver through regmap
   - Add device tree binding documentation for the watchdog driver
   - Add docs for the RCU DT bindings.
   - Convert the fpi bus driver to a platform_driver
   - Remove ltq_reset_cause() and ltq_boot_select(
   - Switch to a proper reset driver
   - Switch to a new drivers/soc GPHY driver
   - Add an USB PHY driver for the Lantiq SoCs using the RCU module
   - Use of_platform_default_populate instead of __dt_register_buses
   - Enable MFD_SYSCON to be able to use it for the RCU MFD
   - Replace ltq_boot_select() with dummy implementation.

  Loongson 2F:
   - Allow NULL clock for clk_get_rate

  Malta:
   - Use new GIC accessor functions

  NI 169445:
   - Add support for NI 169445 board.
   - Only include in 32r2el kernels

  Octeon:
   - Add support for watchdog of 78XX SOCs.
   - Add support for watchdog of CN68XX SOCs.
   - Expose support for mips32r1, mips32r2 and mips64r1
   - Enable more drivers in config file
   - Add support for accessing the boot vector.
   - Remove old boot vector code from watchdog driver
   - Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
   - Make CSR functions node aware.
   - Allow access to CIU3 IRQ domains.
   - Misc cleanups in the watchdog driver

  Omega2+:
   - New board, add support and defconfig

  Pistachio:
   - Enable Root FS on NFS in defconfig

  Ralink:
   - Add Mediatek MT7628A SoC
   - Allow NULL clock for clk_get_rate
   - Explicitly request exclusive reset control in the pci-mt7620 PCI driver.

  SEAD3:
   - Only include in 32 bit kernels by default

  VoCore:
   - Add VoCore as a vendor t0 dt-bindings
   - Add defconfig file"

* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
  MIPS: Refactor handling of stack pointer in get_frame_info
  MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
  MIPS: microMIPS: Fix decoding of swsp16 instruction
  MIPS: microMIPS: Fix decoding of addiusp instruction
  MIPS: microMIPS: Fix detection of addiusp instruction
  MIPS: Handle non word sized instructions when examining frame
  MIPS: ralink: allow NULL clock for clk_get_rate
  MIPS: Loongson 2F: allow NULL clock for clk_get_rate
  MIPS: BCM63XX: allow NULL clock for clk_get_rate
  MIPS: AR7: allow NULL clock for clk_get_rate
  MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
  mips: Save all registers when saving the frame
  MIPS: Add DWARF unwinding to assembly
  MIPS: Make SAVE_SOME more standard
  MIPS: Fix issues in backtraces
  MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
  MIPS: Ci20: Enable RTC driver
  watchdog: octeon-wdt: Add support for 78XX SOCs.
  watchdog: octeon-wdt: Add support for cn68XX SOCs.
  watchdog: octeon-wdt: File cleaning.
  ...
parents 8d93c7a4 35eed7cb
Lantiq XWAY SoC FPI BUS binding
============================
-------------------------------------------------------------------------------
Required properties:
- compatible : Should be one of
"lantiq,xrx200-fpi"
- reg : The address and length of the XBAR
configuration register.
Address and length of the FPI bus itself.
- lantiq,rcu : A phandle to the RCU syscon
- lantiq,offset-endianness : Offset of the endianness configuration
register
-------------------------------------------------------------------------------
Example for the FPI on the xrx200 SoCs:
fpi@10000000 {
compatible = "lantiq,xrx200-fpi";
ranges = <0x0 0x10000000 0xf000000>;
reg = <0x1f400000 0x1000>,
<0x10000000 0xf000000>;
lantiq,rcu = <&rcu0>;
lantiq,offset-endianness = <0x4c>;
#address-cells = <1>;
#size-cells = <1>;
gptu@e100a00 {
......
};
};
Lantiq XWAY SoC GPHY binding
============================
This binding describes a software-defined ethernet PHY, provided by the RCU
module on newer Lantiq XWAY SoCs (xRX200 and newer).
-------------------------------------------------------------------------------
Required properties:
- compatible : Should be one of
"lantiq,xrx200a1x-gphy"
"lantiq,xrx200a2x-gphy"
"lantiq,xrx300-gphy"
"lantiq,xrx330-gphy"
- reg : Addrress of the GPHY FW load address register
- resets : Must reference the RCU GPHY reset bit
- reset-names : One entry, value must be "gphy" or optional "gphy2"
- clocks : A reference to the (PMU) GPHY clock gate
Optional properties:
- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
<dt-bindings/mips/lantiq_xway_gphy.h>
-------------------------------------------------------------------------------
Example for the GPHys on the xRX200 SoCs:
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
gphy0: gphy@20 {
compatible = "lantiq,xrx200a2x-gphy";
reg = <0x20 0x4>;
resets = <&reset0 31 30>, <&reset1 7 7>;
reset-names = "gphy", "gphy2";
clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
Lantiq XWAY SoC RCU binding
===========================
This binding describes the RCU (reset controller unit) multifunction device,
where each sub-device has it's own set of registers.
The RCU register range is used for multiple purposes. Mostly one device
uses one or multiple register exclusively, but for some registers some
bits are for one driver and some other bits are for a different driver.
With this patch all accesses to the RCU registers will go through
syscon.
-------------------------------------------------------------------------------
Required properties:
- compatible : The first and second values must be:
"lantiq,xrx200-rcu", "simple-mfd", "syscon"
- reg : The address and length of the system control registers
-------------------------------------------------------------------------------
Example of the RCU bindings on a xRX200 SoC:
rcu0: rcu@203000 {
compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
reg = <0x203000 0x100>;
ranges = <0x0 0x203000 0x100>;
big-endian;
gphy0: gphy@20 {
compatible = "lantiq,xrx200a2x-gphy";
reg = <0x20 0x4>;
resets = <&reset0 31 30>, <&reset1 7 7>;
reset-names = "gphy", "gphy2";
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
gphy1: gphy@68 {
compatible = "lantiq,xrx200a2x-gphy";
reg = <0x68 0x4>;
resets = <&reset0 29 28>, <&reset1 6 6>;
reset-names = "gphy", "gphy2";
lantiq,gphy-mode = <GPHY_MODE_GE>;
};
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg = <0x10 4>, <0x14 4>;
#reset-cells = <2>;
};
reset1: reset-controller@48 {
compatible = "lantiq,xrx200-reset";
reg = <0x48 4>, <0x24 4>;
#reset-cells = <2>;
};
usb_phy0: usb2-phy@18 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x18 4>, <0x38 4>;
status = "disabled";
resets = <&reset1 4 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
#phy-cells = <0>;
};
usb_phy1: usb2-phy@34 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x34 4>, <0x3C 4>;
status = "disabled";
resets = <&reset1 5 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
#phy-cells = <0>;
};
reboot@10 {
compatible = "syscon-reboot";
reg = <0x10 4>;
regmap = <&rcu0>;
offset = <0x10>;
mask = <0x40000000>;
};
};
National Instruments MIPS platforms
required root node properties:
- compatible: must be "ni,169445"
CPU Nodes
- compatible: must be "mti,mips14KEc"
......@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
ralink,mt7628a-soc
Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
===========================================
This binding describes the USB PHY hardware provided by the RCU module on the
Lantiq XWAY SoCs.
This node has to be a sub node of the Lantiq RCU block.
-------------------------------------------------------------------------------
Required properties (controller (parent) node):
- compatible : Should be one of
"lantiq,ase-usb2-phy"
"lantiq,danube-usb2-phy"
"lantiq,xrx100-usb2-phy"
"lantiq,xrx200-usb2-phy"
"lantiq,xrx300-usb2-phy"
- reg : Defines the following sets of registers in the parent
syscon device
- Offset of the USB PHY configuration register
- Offset of the USB Analog configuration
register (only for xrx200 and xrx200)
- clocks : References to the (PMU) "phy" clk gate.
- clock-names : Must be "phy"
- resets : References to the RCU USB configuration reset bits.
- reset-names : Must be one of the following:
"phy" (optional)
"ctrl" (shared)
-------------------------------------------------------------------------------
Example for the USB PHYs on an xRX200 SoC:
usb_phy0: usb2-phy@18 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x18 4>, <0x38 4>;
clocks = <&pmu PMU_GATE_USB0_PHY>;
clock-names = "phy";
resets = <&reset1 4 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
#phy-cells = <0>;
};
Lantiq XWAY SoC RCU reset controller binding
============================================
This binding describes a reset-controller found on the RCU module on Lantiq
XWAY SoCs.
This node has to be a sub node of the Lantiq RCU block.
-------------------------------------------------------------------------------
Required properties:
- compatible : Should be one of
"lantiq,danube-reset"
"lantiq,xrx200-reset"
- reg : Defines the following sets of registers in the parent
syscon device
- Offset of the reset set register
- Offset of the reset status register
- #reset-cells : Specifies the number of cells needed to encode the
reset line, should be 2.
The first cell takes the reset set bit and the
second cell takes the status bit.
-------------------------------------------------------------------------------
Example for the reset-controllers on the xRX200 SoCs:
reset0: reset-controller@10 {
compatible = "lantiq,xrx200-reset";
reg <0x10 0x04>, <0x14 0x04>;
#reset-cells = <2>;
};
......@@ -361,6 +361,7 @@ variscite Variscite Ltd.
via VIA Technologies, Inc.
virtio Virtual I/O Device Specification, developed by the OASIS consortium
vivante Vivante Corporation
vocore VoCore Studio
voipac Voipac Technologies s.r.o.
wd Western Digital Corp.
wetek WeTek Electronics, limited.
......
Lantiq WTD watchdog binding
============================
This describes the binding of the Lantiq watchdog driver.
-------------------------------------------------------------------------------
Required properties:
- compatible : Should be one of
"lantiq,wdt"
"lantiq,xrx100-wdt"
"lantiq,xrx200-wdt", "lantiq,xrx100-wdt"
"lantiq,falcon-wdt"
- reg : Address of the watchdog block
- lantiq,rcu : A phandle to the RCU syscon (required for
"lantiq,falcon-wdt" and "lantiq,xrx100-wdt")
-------------------------------------------------------------------------------
Example for the watchdog on the xRX200 SoCs:
watchdog@803f0 {
compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt";
reg = <0x803f0 0x10>;
lantiq,rcu = <&rcu0>;
};
......@@ -7717,6 +7717,7 @@ M: John Crispin <john@phrozen.org>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/lantiq
F: drivers/soc/lantiq
LAPB module
L: linux-x25@vger.kernel.org
......@@ -8982,6 +8983,7 @@ M: Paul Burton <paul.burton@imgtec.com>
L: linux-mips@linux-mips.org
S: Supported
F: arch/mips/generic/
F: arch/mips/tools/generic-board-config.sh
MIPS/LOONGSON1 ARCHITECTURE
M: Keguang Zhang <keguang.zhang@gmail.com>
......@@ -8992,6 +8994,13 @@ F: arch/mips/include/asm/mach-loongson32/
F: drivers/*/*loongson1*
F: drivers/*/*/*loongson1*
MIPS RINT INSTRUCTION EMULATION
M: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
L: linux-mips@linux-mips.org
S: Supported
F: arch/mips/math-emu/sp_rint.c
F: arch/mips/math-emu/dp_rint.c
MIROSOUND PCM20 FM RADIO RECEIVER DRIVER
M: Hans Verkuil <hverkuil@xs4all.nl>
L: linux-media@vger.kernel.org
......@@ -9869,6 +9878,12 @@ F: drivers/regulator/twl-regulator.c
F: drivers/regulator/twl6030-regulator.c
F: include/linux/i2c-omap.h
ONION OMEGA2+ BOARD
M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/boot/dts/ralink/omega2p.dts
OMFS FILESYSTEM
M: Bob Copeland <me@bobcopeland.com>
L: linux-karma-devel@lists.sourceforge.net
......@@ -14390,6 +14405,12 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/vmxnet3/
VOCORE VOCORE2 BOARD
M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/boot/dts/ralink/vocore2.dts
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
M: Liam Girdwood <lgirdwood@gmail.com>
M: Mark Brown <broonie@kernel.org>
......
......@@ -1627,14 +1627,6 @@ config CPU_R5500
NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
instruction set.
config CPU_R6000
bool "R6000"
depends on SYS_HAS_CPU_R6000
select CPU_SUPPORTS_32BIT_KERNEL
help
MIPS Technologies R6000 and R6000A series processors. Note these
processors are extremely rare and the support for them is incomplete.
config CPU_NEVADA
bool "RM52xx"
depends on SYS_HAS_CPU_NEVADA
......@@ -1950,9 +1942,6 @@ config SYS_HAS_CPU_R5432
config SYS_HAS_CPU_R5500
bool
config SYS_HAS_CPU_R6000
bool
config SYS_HAS_CPU_NEVADA
bool
......@@ -2180,7 +2169,7 @@ config PAGE_SIZE_32KB
config PAGE_SIZE_64KB
bool "64kB"
depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000
depends on !CPU_R3000 && !CPU_TX39XX
help
Using 64kB page size will result in higher performance kernel at
the price of higher memory consumption. This option is available on
......@@ -2248,11 +2237,11 @@ config CPU_HAS_PREFETCH
config CPU_GENERIC_DUMP_TLB
bool
default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
config CPU_R4K_FPU
bool
default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
default y if !(CPU_R3000 || CPU_TX39XX)
config CPU_R4K_CACHE_TLB
bool
......@@ -2260,6 +2249,7 @@ config CPU_R4K_CACHE_TLB
config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
default y
depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
......@@ -2376,7 +2366,6 @@ config MIPS_CPS
bool "MIPS Coherent Processing System support"
depends on SYS_SUPPORTS_MIPS_CPS
select MIPS_CM
select MIPS_CPC
select MIPS_CPS_PM if HOTPLUG_CPU
select SMP
select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
......@@ -2393,11 +2382,11 @@ config MIPS_CPS
config MIPS_CPS_PM
depends on MIPS_CPS
select MIPS_CPC
bool
config MIPS_CM
bool
select MIPS_CPC
config MIPS_CPC
bool
......
......@@ -151,7 +151,6 @@ cflags-y += -fno-stack-check
#
cflags-$(CONFIG_CPU_R3000) += -march=r3000
cflags-$(CONFIG_CPU_TX39XX) += -march=r3900
cflags-$(CONFIG_CPU_R6000) += -march=r6000 -Wa,--trap
cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
......@@ -291,7 +290,8 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
VMLINUX_ENTRY_ADDRESS=$(entry-y) \
PLATFORM="$(platform-y)"
PLATFORM="$(platform-y)" \
ITS_INPUTS="$(its-y)"
ifdef CONFIG_32BIT
bootvars-y += ADDR_BITS=32
endif
......@@ -299,6 +299,10 @@ ifdef CONFIG_64BIT
bootvars-y += ADDR_BITS=64
endif
# This is required to get dwarf unwinding tables into .debug_frame
# instead of .eh_frame so we don't discard them.
KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
LDFLAGS += -m $(ld-emul)
ifdef CONFIG_MIPS
......@@ -500,8 +504,14 @@ $(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
.PHONY: $(generic_defconfigs)
$(generic_defconfigs):
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
-m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/generic_defconfig $^ \
$(foreach board,$(BOARDS),$(generic_config_dir)/board-$(board).config)
-m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/generic_defconfig $^ | \
grep -Ev '^#'
$(Q)cp $(KCONFIG_CONFIG) $(objtree)/.config.$@
$(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig \
KCONFIG_CONFIG=$(objtree)/.config.$@ >/dev/null
$(Q)$(CONFIG_SHELL) $(srctree)/arch/$(ARCH)/tools/generic-board-config.sh \
$(srctree) $(objtree) $(objtree)/.config.$@ $(KCONFIG_CONFIG) \
"$(origin BOARDS)" $(BOARDS)
$(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig
#
......@@ -509,6 +519,19 @@ $(generic_defconfigs):
#
$(generic_config_dir)/%.config: ;
#
# Prevent direct use of generic_defconfig, which is intended to be used as the
# basis of the various ISA-specific targets generated above.
#
.PHONY: generic_defconfig
generic_defconfig:
$(Q)echo "generic_defconfig is not intended for direct use, but should instead be"
$(Q)echo "used via an ISA-specific target from the following list:"
$(Q)echo
$(Q)for cfg in $(generic_defconfigs); do echo " $${cfg}"; done
$(Q)echo
$(Q)false
#
# Legacy defconfig compatibility - these targets used to be real defconfigs but
# now that the boards have been converted to use the generic kernel they are
......
......@@ -344,28 +344,32 @@ static struct platform_device db1200_ide_dev = {
/* SD carddetects: they're supposed to be edge-triggered, but ack
* doesn't seem to work (CPLD Rev 2). Instead, the screaming one
* is disabled and its counterpart enabled. The 500ms timeout is
* because the carddetect isn't debounced in hardware.
* is disabled and its counterpart enabled. The 200ms timeout is
* because the carddetect usually triggers twice, after debounce.
*/
static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
{
void(*mmc_cd)(struct mmc_host *, unsigned long);
disable_irq_nosync(irq);
return IRQ_WAKE_THREAD;
}
if (irq == DB1200_SD0_INSERT_INT) {
disable_irq_nosync(DB1200_SD0_INSERT_INT);
enable_irq(DB1200_SD0_EJECT_INT);
} else {
disable_irq_nosync(DB1200_SD0_EJECT_INT);
enable_irq(DB1200_SD0_INSERT_INT);
}
static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
{
void (*mmc_cd)(struct mmc_host *, unsigned long);
/* link against CONFIG_MMC=m */
mmc_cd = symbol_get(mmc_detect_change);
if (mmc_cd) {
mmc_cd(ptr, msecs_to_jiffies(500));
mmc_cd(ptr, msecs_to_jiffies(200));
symbol_put(mmc_detect_change);
}
msleep(100); /* debounce */
if (irq == DB1200_SD0_INSERT_INT)
enable_irq(DB1200_SD0_EJECT_INT);
else
enable_irq(DB1200_SD0_INSERT_INT);
return IRQ_HANDLED;
}
......@@ -374,13 +378,13 @@ static int db1200_mmc_cd_setup(void *mmc_host, int en)
int ret;
if (en) {
ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
0, "sd_insert", mmc_host);
ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
if (ret)
goto out;
ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
0, "sd_eject", mmc_host);
ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
if (ret) {
free_irq(DB1200_SD0_INSERT_INT, mmc_host);
goto out;
......@@ -436,23 +440,27 @@ static struct led_classdev db1200_mmc_led = {
static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
{
void(*mmc_cd)(struct mmc_host *, unsigned long);
disable_irq_nosync(irq);
return IRQ_WAKE_THREAD;
}
if (irq == PB1200_SD1_INSERT_INT) {
disable_irq_nosync(PB1200_SD1_INSERT_INT);
enable_irq(PB1200_SD1_EJECT_INT);
} else {
disable_irq_nosync(PB1200_SD1_EJECT_INT);
enable_irq(PB1200_SD1_INSERT_INT);
}
static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
{
void (*mmc_cd)(struct mmc_host *, unsigned long);
/* link against CONFIG_MMC=m */
mmc_cd = symbol_get(mmc_detect_change);
if (mmc_cd) {
mmc_cd(ptr, msecs_to_jiffies(500));
mmc_cd(ptr, msecs_to_jiffies(200));
symbol_put(mmc_detect_change);
}
msleep(100); /* debounce */
if (irq == PB1200_SD1_INSERT_INT)
enable_irq(PB1200_SD1_EJECT_INT);
else
enable_irq(PB1200_SD1_INSERT_INT);
return IRQ_HANDLED;
}
......@@ -461,13 +469,13 @@ static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
int ret;
if (en) {
ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
"sd1_insert", mmc_host);
ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
if (ret)
goto out;
ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
"sd1_eject", mmc_host);
ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
if (ret) {
free_irq(PB1200_SD1_INSERT_INT, mmc_host);
goto out;
......
......@@ -450,24 +450,27 @@ static struct platform_device db1300_ide_dev = {
static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
{
void(*mmc_cd)(struct mmc_host *, unsigned long);
disable_irq_nosync(irq);
return IRQ_WAKE_THREAD;
}
/* disable the one currently screaming. No other way to shut it up */
if (irq == DB1300_SD1_INSERT_INT) {
disable_irq_nosync(DB1300_SD1_INSERT_INT);
enable_irq(DB1300_SD1_EJECT_INT);
} else {
disable_irq_nosync(DB1300_SD1_EJECT_INT);
enable_irq(DB1300_SD1_INSERT_INT);
}
static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr)
{
void (*mmc_cd)(struct mmc_host *, unsigned long);
/* link against CONFIG_MMC=m. We can only be called once MMC core has
* initialized the controller, so symbol_get() should always succeed.
*/
mmc_cd = symbol_get(mmc_detect_change);
mmc_cd(ptr, msecs_to_jiffies(500));
mmc_cd(ptr, msecs_to_jiffies(200));
symbol_put(mmc_detect_change);
msleep(100); /* debounce */
if (irq == DB1300_SD1_INSERT_INT)
enable_irq(DB1300_SD1_EJECT_INT);
else
enable_irq(DB1300_SD1_INSERT_INT);
return IRQ_HANDLED;
}
......@@ -487,13 +490,13 @@ static int db1300_mmc_cd_setup(void *mmc_host, int en)
int ret;
if (en) {
ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
"sd_insert", mmc_host);
ret = request_threaded_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd,
db1300_mmc_cdfn, 0, "sd_insert", mmc_host);
if (ret)
goto out;
ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
"sd_eject", mmc_host);
ret = request_threaded_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd,
db1300_mmc_cdfn, 0, "sd_eject", mmc_host);
if (ret) {
free_irq(DB1300_SD1_INSERT_INT, mmc_host);
goto out;
......
......@@ -2,6 +2,7 @@
* Alchemy DB/PB1xxx board support.
*/
#include <asm/prom.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
......@@ -97,6 +98,7 @@ arch_initcall(db1xxx_arch_init);
static int __init db1xxx_dev_init(void)
{
mips_set_machine_name(board_type_str());
switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
case BCSR_WHOAMI_DB1000:
case BCSR_WHOAMI_DB1500:
......
......@@ -430,6 +430,9 @@ EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
......
......@@ -487,17 +487,16 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
{
struct clk *ref_clk;
void __iomem *pll_base;
const char *dnfn = of_node_full_name(np);
ref_clk = of_clk_get(np, 0);
if (IS_ERR(ref_clk)) {
pr_err("%s: of_clk_get failed\n", dnfn);
pr_err("%pOF: of_clk_get failed\n", np);
goto err;
}
pll_base = of_iomap(np, 0);
if (!pll_base) {
pr_err("%s: can't map pll registers\n", dnfn);
pr_err("%pOF: can't map pll registers\n", np);
goto err_clk;
}
......@@ -506,12 +505,12 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
ar9330_clk_init(ref_clk, pll_base);
else {
pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
pr_err("%pOF: could not find any appropriate clk_init()\n", np);
goto err_iounmap;
}
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%s: could not register clk provider\n", dnfn);
pr_err("%pOF: could not register clk provider\n", np);
goto err_iounmap;
}
......
......@@ -339,6 +339,9 @@ EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
......
......@@ -118,6 +118,12 @@ ifeq ($(ADDR_BITS),64)
itb_addr_cells = 2
endif
quiet_cmd_its_cat = CAT $@
cmd_its_cat = cat $^ >$@
$(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS))
$(call if_changed,its_cat)
quiet_cmd_cpp_its_S = ITS $@
cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \
-DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
......@@ -128,19 +134,19 @@ quiet_cmd_cpp_its_S = ITS $@
-DADDR_BITS=$(ADDR_BITS) \
-DADDR_CELLS=$(itb_addr_cells)
$(obj)/vmlinux.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
$(obj)/vmlinux.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,none,vmlinux.bin)
$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
$(obj)/vmlinux.gz.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)
$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
$(obj)/vmlinux.bz2.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)
$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
$(obj)/vmlinux.lzma.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)
$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
$(obj)/vmlinux.lzo.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)
quiet_cmd_itb-image = ITB $@
......
......@@ -5,6 +5,7 @@ dts-dirs += ingenic
dts-dirs += lantiq
dts-dirs += mti
dts-dirs += netlogic
dts-dirs += ni
dts-dirs += pic32
dts-dirs += qca
dts-dirs += ralink
......
/dts-v1/;
#include "jz4780.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "img,ci20", "ingenic,jz4780";
......@@ -21,6 +22,13 @@ memory {
reg = <0x0 0x10000000
0x30000000 0x30000000>;
};
eth0_power: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "eth0_power";
gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
enable-active-high;
};
};
&ext {
......@@ -123,6 +131,29 @@ partition@0x8c00000 {
};
};
};
dm9000@6 {
compatible = "davicom,dm9000";
davicom,no-eeprom;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc_cs6>;
reg = <6 0 1 /* addr */
6 2 1>; /* data */
ingenic,nemc-tAS = <15>;
ingenic,nemc-tAH = <10>;
ingenic,nemc-tBP = <20>;
ingenic,nemc-tAW = <50>;
ingenic,nemc-tSTRV = <100>;
reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
vcc-supply = <&eth0_power>;
interrupt-parent = <&gpe>;
interrupts = <19 4>;
};
};
&bch {
......@@ -165,4 +196,10 @@ pins_nemc_cs1: nemc-cs1 {
groups = "nemc-cs1";
bias-disable;
};
pins_nemc_cs6: nemc-cs6 {
function = "nemc-cs6";
groups = "nemc-cs6";
bias-disable;
};
};
......@@ -44,6 +44,17 @@ cgu: jz4780-cgu@10000000 {
#clock-cells = <1>;
};
rtc_dev: rtc@10003000 {
compatible = "ingenic,jz4780-rtc";
reg = <0x10003000 0x4c>;
interrupt-parent = <&intc>;
interrupts = <32>;
clocks = <&cgu JZ4780_CLK_RTCLK>;
clock-names = "rtc";
};
pinctrl: pin-controller@10010000 {
compatible = "ingenic,jz4780-pinctrl";
reg = <0x10010000 0x600>;
......
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ni,169445";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mti,mips14KEc";
clocks = <&baseclk>;
reg = <0>;
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x10000000>;
};
baseclk: baseclock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
ahb@1f300000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1f300000 0x80FFF>;
gpio1: gpio@10 {
compatible = "ni,169445-nand-gpio";
reg = <0x10 0x4>;
reg-names = "dat";
gpio-controller;
#gpio-cells = <2>;
};
gpio2: gpio@14 {
compatible = "ni,169445-nand-gpio";
reg = <0x14 0x4>;
reg-names = "dat";
gpio-controller;
#gpio-cells = <2>;
no-output;
};
nand@0 {
compatible = "gpio-control-nand";
nand-on-flash-bbt;
nand-ecc-mode = "soft_bch";
nand-ecc-step-size = <512>;
nand-ecc-strength = <4>;
reg = <0x0 4>;
gpios = <&gpio2 0 0>, /* rdy */
<&gpio1 1 0>, /* nce */
<&gpio1 2 0>, /* ale */
<&gpio1 3 0>, /* cle */
<&gpio1 4 0>; /* nwp */
};
serial@80000 {
compatible = "ns16550a";
reg = <0x80000 0x1000>;
interrupt-parent = <&cpu_intc>;
interrupts = <6>;
clocks = <&baseclk>;
reg-shift = <0>;
};
ethernet@40000 {
compatible = "snps,dwmac-4.10a";
interrupt-parent = <&cpu_intc>;
interrupts = <5>;
interrupt-names = "macirq";
reg = <0x40000 0x2000>;
clock-names = "stmmaceth", "pclk";
clocks = <&baseclk>, <&baseclk>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
dtb-$(CONFIG_FIT_IMAGE_FDT_NI169445) += 169445.dtb
# Force kbuild to make empty built-in.o if necessary
obj- += dummy.o
always := $(dtb-y)
clean-files := *.dtb *.dtb.S
......@@ -2,6 +2,8 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb
dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb
dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb
dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb
dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb
dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
......
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,mt7628a-soc";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mti,mips24KEc";
device_type = "cpu";
reg = <0>;
};
};
resetc: reset-controller {
compatible = "ralink,rt2880-reset";
#reset-cells = <1>;
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
palmbus@10000000 {
compatible = "palmbus";
reg = <0x10000000 0x200000>;
ranges = <0x0 0x10000000 0x1FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
sysc: system-controller@0 {
compatible = "ralink,mt7620a-sysc", "syscon";
reg = <0x0 0x100>;
};
intc: interrupt-controller@200 {
compatible = "ralink,rt2880-intc";
reg = <0x200 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
resets = <&resetc 9>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
interrupts = <2>;
ralink,intc-registers = <0x9c 0xa0
0x6c 0xa4
0x80 0x78>;
};
memory-controller@300 {
compatible = "ralink,mt7620a-memc";
reg = <0x300 0x100>;
};
uart0: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
resets = <&resetc 12>;
reset-names = "uart0";
interrupt-parent = <&intc>;
interrupts = <20>;
reg-shift = <2>;
};
uart1: uart1@d00 {
compatible = "ns16550a";
reg = <0xd00 0x100>;
resets = <&resetc 19>;
reset-names = "uart1";
interrupt-parent = <&intc>;
interrupts = <21>;
reg-shift = <2>;
};
uart2: uart2@e00 {
compatible = "ns16550a";
reg = <0xe00 0x100>;
resets = <&resetc 20>;
reset-names = "uart2";
interrupt-parent = <&intc>;
interrupts = <22>;
reg-shift = <2>;
};
};
usb_phy: usb-phy@10120000 {
compatible = "mediatek,mt7628-usbphy";
reg = <0x10120000 0x1000>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
resets = <&resetc 22 &resetc 25>;
reset-names = "host", "device";
};
ehci@101c0000 {
compatible = "generic-ehci";
reg = <0x101c0000 0x1000>;
phys = <&usb_phy>;
phy-names = "usb";
interrupt-parent = <&intc>;
interrupts = <18>;
};
};
/dts-v1/;
/include/ "mt7628a.dtsi"
/ {
compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";
model = "Onion Omega2+";
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
};
};
/dts-v1/;
#include "mt7628a.dtsi"
/ {
compatible = "vocore,vocore2", "ralink,mt7628a-soc";
model = "VoCore2";
memory@0 {
device_type = "memory";
reg = <0x0 0x8000000>;
};
chosen {
bootargs = "console=ttyS2,115200";
stdout-path = &uart2;
};
};
......@@ -16,4 +16,4 @@ obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o cvmx-boot-vector.o
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004-2017 Cavium, Inc.
*/
/*
We install this program at the bootvector:
------------------------------------
.set noreorder
.set nomacro
.set noat
reset_vector:
dmtc0 $k0, $31, 0 # Save $k0 to DESAVE
dmtc0 $k1, $31, 3 # Save $k1 to KScratch2
mfc0 $k0, $12, 0 # Status
mfc0 $k1, $15, 1 # Ebase
ori $k0, 0x84 # Enable 64-bit addressing, set
# ERL (should already be set)
andi $k1, 0x3ff # mask out core ID
mtc0 $k0, $12, 0 # Status
sll $k1, 5
lui $k0, 0xbfc0
cache 17, 0($0) # Core-14345, clear L1 Dcache virtual
# tags if the core hit an NMI
ld $k0, 0x78($k0) # k0 <- (bfc00078) pointer to the reset vector
synci 0($0) # Invalidate ICache to get coherent
# view of target code.
daddu $k0, $k0, $k1
nop
ld $k0, 0($k0) # k0 <- core specific target address
dmfc0 $k1, $31, 3 # Restore $k1 from KScratch2
beqz $k0, wait_loop # Spin in wait loop
nop
jr $k0
nop
nop # NOPs needed here to fill delay slots
nop # on endian reversal of previous instructions
wait_loop:
wait
nop
b wait_loop
nop
nop
nop
------------------------------------
0000000000000000 <reset_vector>:
0: 40baf800 dmtc0 k0,c0_desave
4: 40bbf803 dmtc0 k1,c0_kscratch2
8: 401a6000 mfc0 k0,c0_status
c: 401b7801 mfc0 k1,c0_ebase
10: 375a0084 ori k0,k0,0x84
14: 337b03ff andi k1,k1,0x3ff
18: 409a6000 mtc0 k0,c0_status
1c: 001bd940 sll k1,k1,0x5
20: 3c1abfc0 lui k0,0xbfc0
24: bc110000 cache 0x11,0(zero)
28: df5a0078 ld k0,120(k0)
2c: 041f0000 synci 0(zero)
30: 035bd02d daddu k0,k0,k1
34: 00000000 nop
38: df5a0000 ld k0,0(k0)
3c: 403bf803 dmfc0 k1,c0_kscratch2
40: 13400005 beqz k0,58 <wait_loop>
44: 00000000 nop
48: 03400008 jr k0
4c: 00000000 nop
50: 00000000 nop
54: 00000000 nop
0000000000000058 <wait_loop>:
58: 42000020 wait
5c: 00000000 nop
60: 1000fffd b 58 <wait_loop>
64: 00000000 nop
68: 00000000 nop
6c: 00000000 nop
*/
#include <asm/octeon/cvmx-boot-vector.h>
static unsigned long long _cvmx_bootvector_data[16] = {
0x40baf80040bbf803ull, /* patch low order 8-bits if no KScratch*/
0x401a6000401b7801ull,
0x375a0084337b03ffull,
0x409a6000001bd940ull,
0x3c1abfc0bc110000ull,
0xdf5a0078041f0000ull,
0x035bd02d00000000ull,
0xdf5a0000403bf803ull, /* patch low order 8-bits if no KScratch*/
0x1340000500000000ull,
0x0340000800000000ull,
0x0000000000000000ull,
0x4200002000000000ull,
0x1000fffd00000000ull,
0x0000000000000000ull,
OCTEON_BOOT_MOVEABLE_MAGIC1,
0 /* To be filled in with address of vector block*/
};
/* 2^10 CPUs */
#define VECTOR_TABLE_SIZE (1024 * sizeof(struct cvmx_boot_vector_element))
static void cvmx_boot_vector_init(void *mem)
{
uint64_t kseg0_mem;
int i;
memset(mem, 0, VECTOR_TABLE_SIZE);
kseg0_mem = cvmx_ptr_to_phys(mem) | 0x8000000000000000ull;
for (i = 0; i < 15; i++) {
uint64_t v = _cvmx_bootvector_data[i];
if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
v &= 0xffffffff00000000ull; /* KScratch not availble. */
cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
}
cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8);
cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem);
cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
}
/**
* Get a pointer to the per-core table of reset vector pointers
*
*/
struct cvmx_boot_vector_element *cvmx_boot_vector_get(void)
{
struct cvmx_boot_vector_element *ret;
ret = cvmx_bootmem_alloc_named_range_once(VECTOR_TABLE_SIZE, 0,
(1ull << 32) - 1, 8, "__boot_vector1__", cvmx_boot_vector_init);
return ret;
}
EXPORT_SYMBOL(cvmx_boot_vector_get);
......@@ -44,6 +44,55 @@ static struct cvmx_bootmem_desc *cvmx_bootmem_desc;
/* See header file for descriptions of functions */
/**
* This macro returns the size of a member of a structure.
* Logically it is the same as "sizeof(s::field)" in C++, but
* C lacks the "::" operator.
*/
#define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field)
/**
* This macro returns a member of the
* cvmx_bootmem_named_block_desc_t structure. These members can't
* be directly addressed as they might be in memory not directly
* reachable. In the case where bootmem is compiled with
* LINUX_HOST, the structure itself might be located on a remote
* Octeon. The argument "field" is the member name of the
* cvmx_bootmem_named_block_desc_t to read. Regardless of the type
* of the field, the return type is always a uint64_t. The "addr"
* parameter is the physical address of the structure.
*/
#define CVMX_BOOTMEM_NAMED_GET_FIELD(addr, field) \
__cvmx_bootmem_desc_get(addr, \
offsetof(struct cvmx_bootmem_named_block_desc, field), \
SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field))
/**
* This function is the implementation of the get macros defined
* for individual structure members. The argument are generated
* by the macros inorder to read only the needed memory.
*
* @param base 64bit physical address of the complete structure
* @param offset Offset from the beginning of the structure to the member being
* accessed.
* @param size Size of the structure member.
*
* @return Value of the structure member promoted into a uint64_t.
*/
static inline uint64_t __cvmx_bootmem_desc_get(uint64_t base, int offset,
int size)
{
base = (1ull << 63) | (base + offset);
switch (size) {
case 4:
return cvmx_read64_uint32(base);
case 8:
return cvmx_read64_uint64(base);
default:
return 0;
}
}
/*
* Wrapper functions are provided for reading/writing the size and
* next block values as these may not be directly addressible (in 32
......@@ -98,6 +147,42 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
}
void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr,
uint64_t max_addr, uint64_t align,
char *name,
void (*init) (void *))
{
int64_t addr;
void *ptr;
uint64_t named_block_desc_addr;
named_block_desc_addr = (uint64_t)
cvmx_bootmem_phy_named_block_find(name,
(uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING);
if (named_block_desc_addr) {
addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_desc_addr,
base_addr);
return cvmx_phys_to_ptr(addr);
}
addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
align, name,
(uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING);
if (addr < 0)
return NULL;
ptr = cvmx_phys_to_ptr(addr);
if (init)
init(ptr);
else
memset(ptr, 0, size);
return ptr;
}
EXPORT_SYMBOL(cvmx_bootmem_alloc_named_range_once);
void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
uint64_t max_addr, uint64_t align,
char *name)
......
......@@ -2963,3 +2963,12 @@ void octeon_fixup_irqs(void)
}
#endif /* CONFIG_HOTPLUG_CPU */
struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block)
{
struct octeon_ciu3_info *ciu3_info;
ciu3_info = octeon_ciu3_info_per_node[node & CVMX_NODE_MASK];
return ciu3_info->domain[block];
}
EXPORT_SYMBOL(octeon_irq_get_block_domain);
......@@ -205,7 +205,7 @@ int plat_post_relocation(long offset)
* Firmware CPU startup hook
*
*/
static void octeon_boot_secondary(int cpu, struct task_struct *idle)
static int octeon_boot_secondary(int cpu, struct task_struct *idle)
{
int count;
......@@ -223,8 +223,12 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
udelay(1);
count--;
}
if (count == 0)
if (count == 0) {
pr_err("Secondary boot timeout\n");
return -ETIMEDOUT;
}
return 0;
}
/**
......@@ -408,7 +412,7 @@ late_initcall(register_cavium_notifier);
#endif /* CONFIG_HOTPLUG_CPU */
struct plat_smp_ops octeon_smp_ops = {
const struct plat_smp_ops octeon_smp_ops = {
.send_ipi_single = octeon_send_ipi_single,
.send_ipi_mask = octeon_send_ipi_mask,
.init_secondary = octeon_init_secondary,
......@@ -485,7 +489,7 @@ static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
octeon_78xx_send_ipi_single(cpu, action);
}
static struct plat_smp_ops octeon_78xx_smp_ops = {
static const struct plat_smp_ops octeon_78xx_smp_ops = {
.send_ipi_single = octeon_78xx_send_ipi_single,
.send_ipi_mask = octeon_78xx_send_ipi_mask,
.init_secondary = octeon_init_secondary,
......@@ -501,7 +505,7 @@ static struct plat_smp_ops octeon_78xx_smp_ops = {
void __init octeon_setup_smp(void)
{
struct plat_smp_ops *ops;
const struct plat_smp_ops *ops;
if (octeon_has_feature(OCTEON_FEATURE_CIU3))
ops = &octeon_78xx_smp_ops;
......
......@@ -60,11 +60,8 @@ CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_AHCI_OCTEON=y
CONFIG_PATA_OCTEON_CF=y
CONFIG_SATA_SIL=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_ALTEON is not set
......@@ -121,22 +118,30 @@ CONFIG_SPI=y
CONFIG_SPI_OCTEON=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_USB=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_EHCI_HCD_PLATFORM=m
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB=y
# CONFIG_USB_PCI is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_MMC=y
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_CAVIUM_OCTEON=y
CONFIG_EDAC=y
CONFIG_EDAC_OCTEON_PC=y
CONFIG_EDAC_OCTEON_L2C=y
CONFIG_EDAC_OCTEON_LMC=y
CONFIG_EDAC_OCTEON_PCI=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_STAGING=y
CONFIG_OCTEON_ETHERNET=y
CONFIG_OCTEON_USB=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RAS=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
......
......@@ -91,6 +91,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_INGENIC=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
......@@ -99,6 +100,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_JZ4740=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
# CONFIG_DNOTIFY is not set
......
# require CONFIG_CPU_MIPS32_R2=y
# require CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_FIT_IMAGE_FDT_NI169445=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_GPIO=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_DWMAC_GENERIC=y
# require CONFIG_32BIT=y
CONFIG_LEGACY_BOARD_SEAD3=y
CONFIG_AUXDISPLAY=y
......
......@@ -3,7 +3,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_MIPS_CPS=y
CONFIG_CPU_HAS_MSA=y
CONFIG_HIGHMEM=y
CONFIG_NR_CPUS=2
CONFIG_NR_CPUS=16
CONFIG_MIPS_O32_FP64_SUPPORT=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
......@@ -61,7 +61,6 @@ CONFIG_HID_KENSINGTON=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_MIPS_PLATFORM_DEVICES is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT4_FS=y
......
......@@ -111,12 +111,8 @@ CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_ECONET=m
CONFIG_ECONET_AUNUDP=y
CONFIG_ECONET_NATIVE=y
CONFIG_WAN_ROUTER=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
......
......@@ -37,7 +37,6 @@ CONFIG_PM=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION="/dev/hda3"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEBUG=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
......
......@@ -2,7 +2,6 @@ CONFIG_MIPS_MALTA=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_MIPS_MT_SMP=y
CONFIG_NR_CPUS=8
CONFIG_HZ_100=y
CONFIG_SYSVIPC=y
......
......@@ -2,7 +2,6 @@ CONFIG_MIPS_MALTA=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_MIPS_MT_SMP=y
CONFIG_NR_CPUS=8
CONFIG_HZ_100=y
CONFIG_SYSVIPC=y
......
......@@ -3,6 +3,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_KVM_GUEST=y
CONFIG_PAGE_SIZE_16KB=y
# CONFIG_MIPS_MT_SMP is not set
CONFIG_HZ_100=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
......
......@@ -2,7 +2,6 @@ CONFIG_MIPS_MALTA=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_MIPS_MT_SMP=y
CONFIG_SCHED_SMT=y
CONFIG_MIPS_CPS=y
CONFIG_NR_CPUS=8
......
......@@ -3,7 +3,6 @@ CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPS32_3_5_FEATURES=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_MIPS_MT_SMP=y
CONFIG_SCHED_SMT=y
CONFIG_MIPS_CPS=y
CONFIG_NR_CPUS=8
......
......@@ -146,12 +146,8 @@ CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_ECONET=m
CONFIG_ECONET_AUNUDP=y
CONFIG_ECONET_NATIVE=y
CONFIG_WAN_ROUTER=m
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_CBQ=m
......
......@@ -259,7 +259,6 @@ CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_WAN_ROUTER=m
......
......@@ -240,12 +240,8 @@ CONFIG_ATALK=m
CONFIG_DEV_APPLETALK=m
CONFIG_IPDDP=m
CONFIG_IPDDP_ENCAP=y
CONFIG_IPDDP_DECAP=y
CONFIG_X25=m
CONFIG_LAPB=m
CONFIG_ECONET=m
CONFIG_ECONET_AUNUDP=y
CONFIG_ECONET_NATIVE=y
CONFIG_WAN_ROUTER=m
CONFIG_PHONET=m
CONFIG_IEEE802154=m
......
CONFIG_RALINK=y
CONFIG_SOC_MT7620=y
CONFIG_DTB_OMEGA2P=y
CONFIG_CPU_MIPS32_R2=y
# CONFIG_COMPACTION is not set
CONFIG_HZ_100=y
CONFIG_PREEMPT=y
# CONFIG_SECCOMP is not set
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_SUSPEND is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_NETDEVICES=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_MMC=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_PHY_RALINK_USB=y
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRC16=y
CONFIG_XZ_DEC=y
......@@ -47,6 +47,8 @@ CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
......@@ -292,7 +294,8 @@ CONFIG_SQUASHFS_LZO=y
CONFIG_PSTORE=y
CONFIG_PSTORE_CONSOLE=y
CONFIG_PSTORE_RAM=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ASCII=m
......
CONFIG_RALINK=y
CONFIG_SOC_MT7620=y
CONFIG_DTB_VOCORE2=y
CONFIG_CPU_MIPS32_R2=y
# CONFIG_COMPACTION is not set
CONFIG_HZ_100=y
CONFIG_PREEMPT=y
# CONFIG_SECCOMP is not set
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_SUSPEND is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_NETDEVICES=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_LEGACY_PTY_COUNT=2
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_MMC=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_MEMORY=y
CONFIG_PHY_RALINK_USB=y
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
CONFIG_NLS_CODEPAGE_775=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=y
CONFIG_NLS_CODEPAGE_855=y
CONFIG_NLS_CODEPAGE_857=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=y
CONFIG_NLS_CODEPAGE_865=y
CONFIG_NLS_CODEPAGE_866=y
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
CONFIG_NLS_CODEPAGE_932=y
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=y
CONFIG_NLS_ISO8859_8=y
CONFIG_NLS_CODEPAGE_1250=y
CONFIG_NLS_CODEPAGE_1251=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=y
CONFIG_NLS_ISO8859_4=y
CONFIG_NLS_ISO8859_5=y
CONFIG_NLS_ISO8859_6=y
CONFIG_NLS_ISO8859_7=y
CONFIG_NLS_ISO8859_9=y
CONFIG_NLS_ISO8859_13=y
CONFIG_NLS_ISO8859_14=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
CONFIG_NLS_KOI8_U=y
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_PANIC_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_STACKTRACE=y
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRC16=y
CONFIG_XZ_DEC=y
......@@ -51,7 +51,7 @@ void __init prom_init(void)
#endif
#ifdef CONFIG_SGI_IP27
{
extern struct plat_smp_ops ip27_smp_ops;
extern const struct plat_smp_ops ip27_smp_ops;
register_smp_ops(&ip27_smp_ops);
}
......
......@@ -36,4 +36,10 @@ config FIT_IMAGE_FDT_BOSTON
enable this if you wish to boot on a MIPS Boston board, as it is
expected by the bootloader.
config FIT_IMAGE_FDT_NI169445
bool "Include FDT for NI 169445"
help
Enable this to include the FDT for the 169445 platform from
National Instruments in the FIT kernel image.
endif
......@@ -12,3 +12,7 @@ platform-$(CONFIG_MIPS_GENERIC) += generic/
cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic
load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
its-y := vmlinux.its.S
its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
/ {
images {
fdt@boston {
description = "img,boston Device Tree";
data = /incbin/("boot/dts/img/boston.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
conf@boston {
description = "Boston Linux kernel";
kernel = "kernel@0";
fdt = "fdt@boston";
};
};
};
{
images {
fdt@ni169445 {
description = "NI 169445 device tree";
data = /incbin/("boot/dts/ni/169445.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
conf@ni169445 {
description = "NI 169445 Linux Kernel";
kernel = "kernel@0";
fdt = "fdt@ni169445";
};
};
};
......@@ -16,6 +16,7 @@
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <asm/bootinfo.h>
#include <asm/fw/fw.h>
#include <asm/irq_cpu.h>
#include <asm/machine.h>
......@@ -88,6 +89,8 @@ void __init *plat_get_fdt(void)
return (void *)fdt;
}
#ifdef CONFIG_RELOCATABLE
void __init plat_fdt_relocated(void *new_location)
{
/*
......@@ -101,6 +104,8 @@ void __init plat_fdt_relocated(void *new_location)
fw_arg1 = (unsigned long)new_location;
}
#endif /* CONFIG_RELOCATABLE */
void __init plat_mem_setup(void)
{
if (mach && mach->fixup_fdt)
......
......@@ -12,10 +12,11 @@
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/types.h>
#include <asm/irq.h>
#include <asm/mips-cps.h>
#include <asm/time.h>
int get_c0_fdc_int(void)
{
......@@ -23,7 +24,7 @@ int get_c0_fdc_int(void)
if (cpu_has_veic)
panic("Unimplemented!");
else if (gic_present)
else if (mips_gic_present())
mips_cpu_fdc_irq = gic_get_c0_fdc_int();
else if (cp0_fdc_irq >= 0)
mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
......@@ -39,7 +40,7 @@ int get_c0_perfcount_int(void)
if (cpu_has_veic)
panic("Unimplemented!");
else if (gic_present)
else if (mips_gic_present())
mips_cpu_perf_irq = gic_get_c0_perfcount_int();
else if (cp0_perfcount_irq >= 0)
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
......@@ -55,7 +56,7 @@ unsigned int get_c0_compare_int(void)
if (cpu_has_veic)
panic("Unimplemented!");
else if (gic_present)
else if (mips_gic_present())
mips_cpu_timer_irq = gic_get_c0_compare_int();
else
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
......
......@@ -29,28 +29,3 @@
};
};
};
#ifdef CONFIG_FIT_IMAGE_FDT_BOSTON
/ {
images {
fdt@boston {
description = "img,boston Device Tree";
data = /incbin/("boot/dts/img/boston.dtb");
type = "flat_dt";
arch = "mips";
compression = "none";
hash@0 {
algo = "sha1";
};
};
};
configurations {
conf@boston {
description = "Boston Linux kernel";
kernel = "kernel@0";
fdt = "fdt@boston";
};
};
};
#endif /* CONFIG_FIT_IMAGE_FDT_BOSTON */
......@@ -55,6 +55,7 @@
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, 0, ra; \
.cfi_startproc; \
.insn
/*
......@@ -66,12 +67,14 @@ symbol: .frame sp, 0, ra; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, framesize, rpc; \
.cfi_startproc; \
.insn
/*
* END - mark end of function
*/
#define END(function) \
.cfi_endproc; \
.end function; \
.size function, .-function
......
......@@ -48,8 +48,8 @@
#include <asm/r4kcache.h>
#include <asm/smp-ops.h>
extern struct plat_smp_ops bmips43xx_smp_ops;
extern struct plat_smp_ops bmips5000_smp_ops;
extern const struct plat_smp_ops bmips43xx_smp_ops;
extern const struct plat_smp_ops bmips5000_smp_ops;
static inline int register_bmips_smp_ops(void)
{
......
......@@ -15,6 +15,8 @@
#include <linux/cache.h>
#include <linux/types.h>
#include <asm/mipsregs.h>
/*
* Descriptor for a cache
*/
......@@ -77,16 +79,9 @@ struct cpuinfo_mips {
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
int package;/* physical package number */
int core; /* physical core number */
unsigned int globalnumber;
#ifdef CONFIG_64BIT
int vmbits; /* Virtual memory size in bits */
#endif
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
/*
* There is not necessarily a 1:1 mapping of VPE num to CPU number
* in particular on multi-core systems.
*/
int vpe_id; /* Virtual Processor number */
#endif
void *data; /* Additional data */
unsigned int watch_reg_count; /* Number that exist */
......@@ -144,11 +139,52 @@ struct proc_cpuinfo_notifier_args {
unsigned long n;
};
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
#else
# define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
#endif
static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
{
/* Optimisation for systems where multiple clusters aren't used */
if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
return 0;
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
MIPS_GLOBALNUMBER_CLUSTER_SHF;
}
static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
{
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
MIPS_GLOBALNUMBER_CORE_SHF;
}
static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
{
/* Optimisation for systems where VP(E)s aren't used */
if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
return 0;
return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
MIPS_GLOBALNUMBER_VP_SHF;
}
extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
static inline bool cpus_are_siblings(int cpua, int cpub)
{
struct cpuinfo_mips *infoa = &cpu_data[cpua];
struct cpuinfo_mips *infob = &cpu_data[cpub];
unsigned int gnuma, gnumb;
if (infoa->package != infob->package)
return false;
gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
if (gnuma != gnumb)
return false;
return true;
}
static inline unsigned long cpu_asid_inc(void)
{
......
......@@ -151,11 +151,6 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_R5500:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R6000
case CPU_R6000:
case CPU_R6000A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_NEVADA
case CPU_NEVADA:
#endif
......
......@@ -285,11 +285,6 @@ enum cpu_type_enum {
CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
CPU_R3081, CPU_R3081E,
/*
* R6000 class processors
*/
CPU_R6000, CPU_R6000A,
/*
* R4000 class processors
*/
......
......@@ -10,11 +10,11 @@
#ifndef _ASM_FLOPPY_H
#define _ASM_FLOPPY_H
#include <linux/dma-mapping.h>
#include <asm/io.h>
static inline void fd_cacheflush(char * addr, long size)
{
dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL);
dma_cache_wback_inv((unsigned long)addr, size);
}
#define MAX_BUFFER_SECTORS 24
......
......@@ -36,6 +36,7 @@ struct mips_fpu_emulator_stats {
unsigned long emulated;
unsigned long loads;
unsigned long stores;
unsigned long branches;
unsigned long cp1ops;
unsigned long cp1xops;
unsigned long errors;
......@@ -45,6 +46,121 @@ struct mips_fpu_emulator_stats {
unsigned long ieee754_zerodiv;
unsigned long ieee754_invalidop;
unsigned long ds_emul;
unsigned long abs_s;
unsigned long abs_d;
unsigned long add_s;
unsigned long add_d;
unsigned long bc1eqz;
unsigned long bc1nez;
unsigned long ceil_w_s;
unsigned long ceil_w_d;
unsigned long ceil_l_s;
unsigned long ceil_l_d;
unsigned long class_s;
unsigned long class_d;
unsigned long cmp_af_s;
unsigned long cmp_af_d;
unsigned long cmp_eq_s;
unsigned long cmp_eq_d;
unsigned long cmp_le_s;
unsigned long cmp_le_d;
unsigned long cmp_lt_s;
unsigned long cmp_lt_d;
unsigned long cmp_ne_s;
unsigned long cmp_ne_d;
unsigned long cmp_or_s;
unsigned long cmp_or_d;
unsigned long cmp_ueq_s;
unsigned long cmp_ueq_d;
unsigned long cmp_ule_s;
unsigned long cmp_ule_d;
unsigned long cmp_ult_s;
unsigned long cmp_ult_d;
unsigned long cmp_un_s;
unsigned long cmp_un_d;
unsigned long cmp_une_s;
unsigned long cmp_une_d;
unsigned long cmp_saf_s;
unsigned long cmp_saf_d;
unsigned long cmp_seq_s;
unsigned long cmp_seq_d;
unsigned long cmp_sle_s;
unsigned long cmp_sle_d;
unsigned long cmp_slt_s;
unsigned long cmp_slt_d;
unsigned long cmp_sne_s;
unsigned long cmp_sne_d;
unsigned long cmp_sor_s;
unsigned long cmp_sor_d;
unsigned long cmp_sueq_s;
unsigned long cmp_sueq_d;
unsigned long cmp_sule_s;
unsigned long cmp_sule_d;
unsigned long cmp_sult_s;
unsigned long cmp_sult_d;
unsigned long cmp_sun_s;
unsigned long cmp_sun_d;
unsigned long cmp_sune_s;
unsigned long cmp_sune_d;
unsigned long cvt_d_l;
unsigned long cvt_d_s;
unsigned long cvt_d_w;
unsigned long cvt_l_s;
unsigned long cvt_l_d;
unsigned long cvt_s_d;
unsigned long cvt_s_l;
unsigned long cvt_s_w;
unsigned long cvt_w_s;
unsigned long cvt_w_d;
unsigned long div_s;
unsigned long div_d;
unsigned long floor_w_s;
unsigned long floor_w_d;
unsigned long floor_l_s;
unsigned long floor_l_d;
unsigned long maddf_s;
unsigned long maddf_d;
unsigned long max_s;
unsigned long max_d;
unsigned long maxa_s;
unsigned long maxa_d;
unsigned long min_s;
unsigned long min_d;
unsigned long mina_s;
unsigned long mina_d;
unsigned long mov_s;
unsigned long mov_d;
unsigned long msubf_s;
unsigned long msubf_d;
unsigned long mul_s;
unsigned long mul_d;
unsigned long neg_s;
unsigned long neg_d;
unsigned long recip_s;
unsigned long recip_d;
unsigned long rint_s;
unsigned long rint_d;
unsigned long round_w_s;
unsigned long round_w_d;
unsigned long round_l_s;
unsigned long round_l_d;
unsigned long rsqrt_s;
unsigned long rsqrt_d;
unsigned long sel_s;
unsigned long sel_d;
unsigned long seleqz_s;
unsigned long seleqz_d;
unsigned long selnez_s;
unsigned long selnez_d;
unsigned long sqrt_s;
unsigned long sqrt_d;
unsigned long sub_s;
unsigned long sub_d;
unsigned long trunc_w_s;
unsigned long trunc_w_d;
unsigned long trunc_l_s;
unsigned long trunc_l_d;
};
DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
......@@ -62,7 +178,7 @@ do { \
extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
struct mips_fpu_struct *ctx, int has_fpu,
void *__user *fault_addr);
void __user **fault_addr);
void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
struct task_struct *tsk);
int process_fpemu_return(int sig, void __user *fault_addr,
......
......@@ -632,4 +632,6 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
*/
#define xlate_dev_kmem_ptr(p) p
void __ioread64_copy(void *to, const void __iomem *from, size_t count);
#endif /* _ASM_IO_H */
......@@ -8,12 +8,16 @@
#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_ftlb 0
#define cpu_has_tlbinv 0
#define cpu_has_segments 0
#define cpu_has_eva 0
#define cpu_has_htw 0
#define cpu_has_ldpte 0
#define cpu_has_rixiex 0
#define cpu_has_maar 0
#define cpu_has_rw_llb 0
#define cpu_has_3kex 0
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
......@@ -30,6 +34,12 @@
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_guestctl0ext 0
#define cpu_has_guestctl1 0
#define cpu_has_guestctl2 0
#define cpu_has_guestid 0
#define cpu_has_drg 0
#define cpu_has_bp_ghist 0
#define cpu_has_mips16 0
#define cpu_has_mips16e2 0
#define cpu_has_mdmx 0
......@@ -37,17 +47,23 @@
#define cpu_has_smartmips 0
#define cpu_has_rixi 0
#define cpu_has_mmips 0
#define cpu_has_lpa 0
#define cpu_has_mhv 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_pindexed_dcache 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips32r6 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_mips64r6 0
#define cpu_has_dsp 0
#define cpu_has_dsp2 0
#define cpu_has_dsp3 0
#define cpu_has_mipsmt 0
#define cpu_has_vp 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
......@@ -58,9 +74,19 @@
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0
#define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0
#define cpu_has_msa 0
#define cpu_has_fre 0
#define cpu_has_cdmm 0
#define cpu_has_small_pages 0
#define cpu_has_nan_legacy 1
#define cpu_has_nan_2008 1
#define cpu_has_ebase_wg 0
#define cpu_has_badinstr 0
#define cpu_has_badinstrp 0
#define cpu_has_contextconfig 0
#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
......@@ -710,7 +710,7 @@
/* Broadcom 6345 ENET DMA definitions */
#define ENETDMA_6345_CHANCFG_REG (0x00)
#define ENETDMA_6345_MAXBURST_REG (0x40)
#define ENETDMA_6345_MAXBURST_REG (0x04)
#define ENETDMA_6345_RSTART_REG (0x08)
......
......@@ -46,9 +46,9 @@
#define cpu_has_64bits 1
#define cpu_has_octeon_cache 1
#define cpu_has_saa octeon_has_saa()
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 1
#define cpu_has_mips64r2 1
#define cpu_has_dsp 0
#define cpu_has_dsp2 0
......
......@@ -23,7 +23,6 @@ struct cpuinfo_ip27 {
extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
#define parent_node(node) (node)
#define cpumask_of_node(node) ((node) == -1 ? \
cpu_all_mask : \
&hub_data(node)->h_cpus)
......
......@@ -46,8 +46,6 @@ extern struct clk *clk_get_ppe(void);
/* find out what bootsource we have */
extern unsigned char ltq_boot_select(void);
/* find out what caused the last cpu reset */
extern int ltq_reset_cause(void);
/* find out the soc type */
extern int ltq_soc_type(void);
......
......@@ -26,7 +26,7 @@ extern void mach_prepare_shutdown(void);
/* environment arguments from bootloader */
extern u32 cpu_clock_freq;
extern u32 memsize, highmemsize;
extern struct plat_smp_ops loongson3_smp_ops;
extern const struct plat_smp_ops loongson3_smp_ops;
/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
......
......@@ -4,7 +4,6 @@
#ifdef CONFIG_NUMA
#define cpu_to_node(cpu) (cpu_logical_map(cpu) >> 2)
#define parent_node(node) (node)
#define cpumask_of_node(node) (&__node_data[(node)]->cpumask)
struct pci_bus;
......
......@@ -10,8 +10,6 @@
#ifndef _MIPS_MALTAINT_H
#define _MIPS_MALTAINT_H
#include <linux/irqchip/mips-gic.h>
/*
* Interrupts 0..15 are used for Malta ISA compatible interrupts
*/
......@@ -62,7 +60,4 @@
#define MSC01E_INT_PERFCTR 10
#define MSC01E_INT_CPUCTR 11
/* GIC external interrupts */
#define GIC_INT_I8259A GIC_SHARED_TO_HWIRQ(3)
#endif /* !(_MIPS_MALTAINT_H) */
This diff is collapsed.
......@@ -8,11 +8,15 @@
* option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_CPS_H__
# error Please include asm/mips-cps.h rather than asm/mips-cpc.h
#endif
#ifndef __MIPS_ASM_MIPS_CPC_H__
#define __MIPS_ASM_MIPS_CPC_H__
#include <linux/io.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/errno.h>
/* The base address of the CPC registers */
extern void __iomem *mips_cpc_base;
......@@ -61,89 +65,92 @@ static inline bool mips_cpc_present(void)
#define MIPS_CPC_CLCB_OFS 0x2000
#define MIPS_CPC_COCB_OFS 0x4000
/* Macros to ease the creation of register access functions */
#define BUILD_CPC_R_(name, off) \
static inline u32 *addr_cpc_##name(void) \
{ \
return (u32 *)(mips_cpc_base + (off)); \
} \
\
static inline u32 read_cpc_##name(void) \
{ \
return __raw_readl(mips_cpc_base + (off)); \
}
#define BUILD_CPC__W(name, off) \
static inline void write_cpc_##name(u32 value) \
{ \
__raw_writel(value, mips_cpc_base + (off)); \
}
#define BUILD_CPC_RW(name, off) \
BUILD_CPC_R_(name, off) \
BUILD_CPC__W(name, off)
#define BUILD_CPC_Cx_R_(name, off) \
BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \
BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
#define BUILD_CPC_Cx__W(name, off) \
BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \
BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
#define BUILD_CPC_Cx_RW(name, off) \
BUILD_CPC_Cx_R_(name, off) \
BUILD_CPC_Cx__W(name, off)
/* GCB register accessor functions */
BUILD_CPC_RW(access, MIPS_CPC_GCB_OFS + 0x00)
BUILD_CPC_RW(seqdel, MIPS_CPC_GCB_OFS + 0x08)
BUILD_CPC_RW(rail, MIPS_CPC_GCB_OFS + 0x10)
BUILD_CPC_RW(resetlen, MIPS_CPC_GCB_OFS + 0x18)
BUILD_CPC_R_(revision, MIPS_CPC_GCB_OFS + 0x20)
/* Core Local & Core Other accessor functions */
BUILD_CPC_Cx_RW(cmd, 0x00)
BUILD_CPC_Cx_RW(stat_conf, 0x08)
BUILD_CPC_Cx_RW(other, 0x10)
BUILD_CPC_Cx_RW(vp_stop, 0x20)
BUILD_CPC_Cx_RW(vp_run, 0x28)
BUILD_CPC_Cx_RW(vp_running, 0x30)
/* CPC_Cx_CMD register fields */
#define CPC_Cx_CMD_SHF 0
#define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0)
#define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0)
#define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0)
#define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0)
#define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0)
/* CPC_Cx_STAT_CONF register fields */
#define CPC_Cx_STAT_CONF_PWRUPE_SHF 23
#define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23)
#define CPC_Cx_STAT_CONF_SEQSTATE_SHF 19
#define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U2 (_ULCAST_(0x3) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U3 (_ULCAST_(0x4) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U4 (_ULCAST_(0x5) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U5 (_ULCAST_(0x6) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_U6 (_ULCAST_(0x7) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D1 (_ULCAST_(0x8) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D3 (_ULCAST_(0x9) << 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D2 (_ULCAST_(0xa) << 19)
#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF 17
#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK (_ULCAST_(0x1) << 17)
#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF 16
#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK (_ULCAST_(0x1) << 16)
#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF 15
#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK (_ULCAST_(0x1) << 15)
/* CPC_Cx_OTHER register fields */
#define CPC_Cx_OTHER_CORENUM_SHF 16
#define CPC_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xff) << 16)
#define CPC_ACCESSOR_RO(sz, off, name) \
CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
#define CPC_ACCESSOR_RW(sz, off, name) \
CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
#define CPC_CX_ACCESSOR_RO(sz, off, name) \
CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
#define CPC_CX_ACCESSOR_RW(sz, off, name) \
CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
CPC_ACCESSOR_RW(32, 0x000, access)
/* CPC_SEQDEL - Configure delays between command sequencer steps */
CPC_ACCESSOR_RW(32, 0x008, seqdel)
/* CPC_RAIL - Configure the delay from rail power-up to stability */
CPC_ACCESSOR_RW(32, 0x010, rail)
/* CPC_RESETLEN - Configure the length of reset sequences */
CPC_ACCESSOR_RW(32, 0x018, resetlen)
/* CPC_REVISION - Indicates the revisison of the CPC */
CPC_ACCESSOR_RO(32, 0x020, revision)
/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
#define CPC_PWRUP_CTL_CM_PWRUP BIT(0)
/* CPC_CONFIG - Mirrors GCR_CONFIG */
CPC_ACCESSOR_RW(64, 0x138, config)
/* CPC_SYS_CONFIG - Control cluster endianness */
CPC_ACCESSOR_RW(32, 0x140, sys_config)
#define CPC_SYS_CONFIG_BE_IMMEDIATE BIT(2)
#define CPC_SYS_CONFIG_BE_STATUS BIT(1)
#define CPC_SYS_CONFIG_BE BIT(0)
/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
#define CPC_Cx_CMD GENMASK(3, 0)
#define CPC_Cx_CMD_CLOCKOFF 0x1
#define CPC_Cx_CMD_PWRDOWN 0x2
#define CPC_Cx_CMD_PWRUP 0x3
#define CPC_Cx_CMD_RESET 0x4
/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
#define CPC_Cx_STAT_CONF_PWRUPE BIT(23)
#define CPC_Cx_STAT_CONF_SEQSTATE GENMASK(22, 19)
#define CPC_Cx_STAT_CONF_SEQSTATE_D0 0x0
#define CPC_Cx_STAT_CONF_SEQSTATE_U0 0x1
#define CPC_Cx_STAT_CONF_SEQSTATE_U1 0x2
#define CPC_Cx_STAT_CONF_SEQSTATE_U2 0x3
#define CPC_Cx_STAT_CONF_SEQSTATE_U3 0x4
#define CPC_Cx_STAT_CONF_SEQSTATE_U4 0x5
#define CPC_Cx_STAT_CONF_SEQSTATE_U5 0x6
#define CPC_Cx_STAT_CONF_SEQSTATE_U6 0x7
#define CPC_Cx_STAT_CONF_SEQSTATE_D1 0x8
#define CPC_Cx_STAT_CONF_SEQSTATE_D3 0x9
#define CPC_Cx_STAT_CONF_SEQSTATE_D2 0xa
#define CPC_Cx_STAT_CONF_CLKGAT_IMPL BIT(17)
#define CPC_Cx_STAT_CONF_PWRDN_IMPL BIT(16)
#define CPC_Cx_STAT_CONF_EJTAG_PROBE BIT(15)
/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
CPC_CX_ACCESSOR_RW(32, 0x010, other)
#define CPC_Cx_OTHER_CORENUM GENMASK(23, 16)
/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
CPC_CX_ACCESSOR_RW(32, 0x090, config)
#ifdef CONFIG_MIPS_CPC
......
/*
* Copyright (C) 2017 Imagination Technologies
* Author: Paul Burton <paul.burton@imgtec.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_CPS_H__
#define __MIPS_ASM_MIPS_CPS_H__
#include <linux/io.h>
#include <linux/types.h>
extern unsigned long __cps_access_bad_size(void)
__compiletime_error("Bad size for CPS accessor");
#define CPS_ACCESSOR_A(unit, off, name) \
static inline void *addr_##unit##_##name(void) \
{ \
return mips_##unit##_base + (off); \
}
#define CPS_ACCESSOR_R(unit, sz, name) \
static inline uint##sz##_t read_##unit##_##name(void) \
{ \
uint64_t val64; \
\
switch (sz) { \
case 32: \
return __raw_readl(addr_##unit##_##name()); \
\
case 64: \
if (mips_cm_is64) \
return __raw_readq(addr_##unit##_##name()); \
\
val64 = __raw_readl(addr_##unit##_##name() + 4); \
val64 <<= 32; \
val64 |= __raw_readl(addr_##unit##_##name()); \
return val64; \
\
default: \
return __cps_access_bad_size(); \
} \
}
#define CPS_ACCESSOR_W(unit, sz, name) \
static inline void write_##unit##_##name(uint##sz##_t val) \
{ \
switch (sz) { \
case 32: \
__raw_writel(val, addr_##unit##_##name()); \
break; \
\
case 64: \
if (mips_cm_is64) { \
__raw_writeq(val, addr_##unit##_##name()); \
break; \
} \
\
__raw_writel((uint64_t)val >> 32, \
addr_##unit##_##name() + 4); \
__raw_writel(val, addr_##unit##_##name()); \
break; \
\
default: \
__cps_access_bad_size(); \
break; \
} \
}
#define CPS_ACCESSOR_M(unit, sz, name) \
static inline void change_##unit##_##name(uint##sz##_t mask, \
uint##sz##_t val) \
{ \
uint##sz##_t reg_val = read_##unit##_##name(); \
reg_val &= ~mask; \
reg_val |= val; \
write_##unit##_##name(reg_val); \
} \
\
static inline void set_##unit##_##name(uint##sz##_t val) \
{ \
change_##unit##_##name(val, val); \
} \
\
static inline void clear_##unit##_##name(uint##sz##_t val) \
{ \
change_##unit##_##name(val, 0); \
}
#define CPS_ACCESSOR_RO(unit, sz, off, name) \
CPS_ACCESSOR_A(unit, off, name) \
CPS_ACCESSOR_R(unit, sz, name)
#define CPS_ACCESSOR_WO(unit, sz, off, name) \
CPS_ACCESSOR_A(unit, off, name) \
CPS_ACCESSOR_W(unit, sz, name)
#define CPS_ACCESSOR_RW(unit, sz, off, name) \
CPS_ACCESSOR_A(unit, off, name) \
CPS_ACCESSOR_R(unit, sz, name) \
CPS_ACCESSOR_W(unit, sz, name) \
CPS_ACCESSOR_M(unit, sz, name)
#include <asm/mips-cm.h>
#include <asm/mips-cpc.h>
#include <asm/mips-gic.h>
/**
* mips_cps_numclusters - return the number of clusters present in the system
*
* Returns the number of clusters in the system.
*/
static inline unsigned int mips_cps_numclusters(void)
{
unsigned int num_clusters;
if (mips_cm_revision() < CM_REV_CM3_5)
return 1;
num_clusters = read_gcr_config() & CM_GCR_CONFIG_NUM_CLUSTERS;
num_clusters >>= __ffs(CM_GCR_CONFIG_NUM_CLUSTERS);
return num_clusters;
}
/**
* mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
* @cluster: the ID of the cluster whose config we want
*
* Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
*
* Returns the value of GCR_CONFIG.
*/
static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
{
uint64_t config;
if (mips_cm_revision() < CM_REV_CM3_5) {
/*
* Prior to CM 3.5 we don't have the notion of multiple
* clusters so we can trivially read the GCR_CONFIG register
* within this cluster.
*/
WARN_ON(cluster != 0);
config = read_gcr_config();
} else {
/*
* From CM 3.5 onwards we read the CPC_CONFIG mirror of
* GCR_CONFIG via the redirect region, since the CPC is always
* powered up allowing us not to need to power up the CM.
*/
mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
config = read_cpc_redir_config();
mips_cm_unlock_other();
}
return config;
}
/**
* mips_cps_numcores - return the number of cores present in a cluster
* @cluster: the ID of the cluster whose core count we want
*
* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
* zero if no Coherence Manager is present.
*/
static inline unsigned int mips_cps_numcores(unsigned int cluster)
{
if (!mips_cm_present())
return 0;
/* Add one before masking to handle 0xff indicating no cores */
return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
}
/**
* mips_cps_numiocu - return the number of IOCUs present in a cluster
* @cluster: the ID of the cluster whose IOCU count we want
*
* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
* if no Coherence Manager is present.
*/
static inline unsigned int mips_cps_numiocu(unsigned int cluster)
{
unsigned int num_iocu;
if (!mips_cm_present())
return 0;
num_iocu = mips_cps_cluster_config(cluster) & CM_GCR_CONFIG_NUMIOCU;
num_iocu >>= __ffs(CM_GCR_CONFIG_NUMIOCU);
return num_iocu;
}
/**
* mips_cps_numvps - return the number of VPs (threads) supported by a core
* @cluster: the ID of the cluster containing the core we want to examine
* @core: the ID of the core whose VP count we want
*
* Returns the number of Virtual Processors (VPs, ie. hardware threads) that
* are supported by the given @core in the given @cluster. If the core or the
* kernel do not support hardware mutlti-threading this returns 1.
*/
static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
{
unsigned int cfg;
if (!mips_cm_present())
return 1;
if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
&& (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
return 1;
mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
if (mips_cm_revision() < CM_REV_CM3_5) {
/*
* Prior to CM 3.5 we can only have one cluster & don't have
* CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
*/
cfg = read_gcr_co_config();
} else {
/*
* From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
* always powered, which allows us to not worry about powering
* up the cluster's CM here.
*/
cfg = read_cpc_co_config();
}
mips_cm_unlock_other();
return (cfg + 1) & CM_GCR_Cx_CONFIG_PVPE;
}
#endif /* __MIPS_ASM_MIPS_CPS_H__ */
This diff is collapsed.
......@@ -48,6 +48,7 @@
#define CP0_ENTRYLO0 $2
#define CP0_ENTRYLO1 $3
#define CP0_CONF $3
#define CP0_GLOBALNUMBER $3, 1
#define CP0_CONTEXT $4
#define CP0_PAGEMASK $5
#define CP0_SEGCTL0 $5, 2
......@@ -147,6 +148,16 @@
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
/*
* MIPSr6+ GlobalNumber register definitions
*/
#define MIPS_GLOBALNUMBER_VP_SHF 0
#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
#define MIPS_GLOBALNUMBER_CORE_SHF 8
#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
/*
* Values for PageMask register
*/
......@@ -1446,6 +1457,8 @@ do { \
#define read_c0_conf() __read_32bit_c0_register($3, 0)
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
#define read_c0_context() __read_ulong_c0_register($4, 0)
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
......
......@@ -114,8 +114,6 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "R5432 "
#elif defined CONFIG_CPU_R5500
#define MODULE_PROC_FAMILY "R5500 "
#elif defined CONFIG_CPU_R6000
#define MODULE_PROC_FAMILY "R6000 "
#elif defined CONFIG_CPU_NEVADA
#define MODULE_PROC_FAMILY "NEVADA "
#elif defined CONFIG_CPU_R8000
......
......@@ -84,7 +84,7 @@ nlm_set_nmi_handler(void *handler)
*/
void nlm_init_boot_cpu(void);
unsigned int nlm_get_cpu_frequency(void);
extern struct plat_smp_ops nlm_smp_ops;
extern const struct plat_smp_ops nlm_smp_ops;
extern char nlm_reset_entry[], nlm_reset_entry_end[];
/* SWIOTLB */
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003-2017 Cavium, Inc.
*/
#ifndef __CVMX_BOOT_VECTOR_H__
#define __CVMX_BOOT_VECTOR_H__
#include <asm/octeon/octeon.h>
/*
* The boot vector table is made up of an array of 1024 elements of
* struct cvmx_boot_vector_element. There is one entry for each
* possible MIPS CPUNum, indexed by the CPUNum.
*
* Once cvmx_boot_vector_get() returns a non-NULL value (indicating
* success), NMI to a core will cause execution to transfer to the
* target_ptr location for that core's entry in the vector table.
*
* The struct cvmx_boot_vector_element fields app0, app1, and app2 can
* be used by the application that has set the target_ptr in any
* application specific manner, they are not touched by the vectoring
* code.
*
* The boot vector code clobbers the CP0_DESAVE register, and on
* OCTEON II and later CPUs also clobbers CP0_KScratch2. All GP
* registers are preserved, except on pre-OCTEON II CPUs, where k1 is
* clobbered.
*
*/
/*
* Applications install the boot bus code in cvmx-boot-vector.c, which
* uses this magic:
*/
#define OCTEON_BOOT_MOVEABLE_MAGIC1 0xdb00110ad358eacdull
struct cvmx_boot_vector_element {
/* kseg0 or xkphys address of target code. */
uint64_t target_ptr;
/* Three application specific arguments. */
uint64_t app0;
uint64_t app1;
uint64_t app2;
};
struct cvmx_boot_vector_element *cvmx_boot_vector_get(void);
#endif /* __CVMX_BOOT_VECTOR_H__ */
......@@ -255,6 +255,34 @@ extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
uint64_t max_addr, uint64_t align,
char *name);
/**
* Allocate if needed a block of memory from a specific range of the
* free list that was passed to the application by the bootloader, and
* assign it a name in the global named block table. (part of the
* cvmx_bootmem_descriptor_t structure) Named blocks can later be
* freed. If the requested name block is already allocated, return
* the pointer to block of memory. If request cannot be satisfied
* within the address range specified, NULL is returned
*
* @param size Size in bytes of block to allocate
* @param min_addr minimum address of range
* @param max_addr maximum address of range
* @param align Alignment of memory to be allocated. (must be a power of 2)
* @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
* @param init Initialization function
*
* The initialization function is optional, if omitted the named block
* is initialized to all zeros when it is created, i.e. once.
*
* @return pointer to block of memory, NULL on error
*/
void *cvmx_bootmem_alloc_named_range_once(uint64_t size,
uint64_t min_addr,
uint64_t max_addr,
uint64_t align,
char *name,
void (*init) (void *));
extern int cvmx_bootmem_free_named(char *name);
/**
......
......@@ -128,6 +128,7 @@ static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
......@@ -143,6 +144,10 @@ static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
}
......@@ -180,6 +185,7 @@ static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
......@@ -195,6 +201,10 @@ static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8;
}
return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
}
......
......@@ -357,6 +357,34 @@ static inline unsigned int cvmx_get_local_core_num(void)
return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
}
#define CVMX_NODE_BITS (2) /* Number of bits to define a node */
#define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
#define CVMX_NODE_IO_SHIFT (36)
#define CVMX_NODE_MEM_SHIFT (40)
#define CVMX_NODE_IO_MASK ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
uint64_t val)
{
uint64_t composite_csr_addr, node_addr;
node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
cvmx_write64_uint64(composite_csr_addr, val);
if (((csr_addr >> 40) & 0x7ffff) == (0x118))
cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
}
static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
{
uint64_t node_addr;
node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
(node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
return cvmx_read_csr(node_addr);
}
/**
* Returns the number of bits set in the provided value.
* Simple wrapper for POP instruction.
......
......@@ -362,4 +362,6 @@ extern void octeon_fixup_irqs(void);
extern struct semaphore octeon_bootbus_sem;
struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block);
#endif /* __ASM_OCTEON_OCTEON_H */
......@@ -13,7 +13,7 @@
#include <linux/errno.h>
#include <asm/mips-cm.h>
#include <asm/mips-cps.h>
#ifdef CONFIG_SMP
......@@ -26,7 +26,7 @@ struct plat_smp_ops {
void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action);
void (*init_secondary)(void);
void (*smp_finish)(void);
void (*boot_secondary)(int cpu, struct task_struct *idle);
int (*boot_secondary)(int cpu, struct task_struct *idle);
void (*smp_setup)(void);
void (*prepare_cpus)(unsigned int max_cpus);
#ifdef CONFIG_HOTPLUG_CPU
......@@ -35,11 +35,11 @@ struct plat_smp_ops {
#endif
};
extern void register_smp_ops(struct plat_smp_ops *ops);
extern void register_smp_ops(const struct plat_smp_ops *ops);
static inline void plat_smp_setup(void)
{
extern struct plat_smp_ops *mp_ops; /* private */
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->smp_setup();
}
......@@ -57,7 +57,7 @@ static inline void plat_smp_setup(void)
/* UP, nothing to do ... */
}
static inline void register_smp_ops(struct plat_smp_ops *ops)
static inline void register_smp_ops(const struct plat_smp_ops *ops)
{
}
......@@ -66,7 +66,7 @@ static inline void register_smp_ops(struct plat_smp_ops *ops)
static inline int register_up_smp_ops(void)
{
#ifdef CONFIG_SMP_UP
extern struct plat_smp_ops up_smp_ops;
extern const struct plat_smp_ops up_smp_ops;
register_smp_ops(&up_smp_ops);
......@@ -79,7 +79,7 @@ static inline int register_up_smp_ops(void)
static inline int register_cmp_smp_ops(void)
{
#ifdef CONFIG_MIPS_CMP
extern struct plat_smp_ops cmp_smp_ops;
extern const struct plat_smp_ops cmp_smp_ops;
if (!mips_cm_present())
return -ENODEV;
......@@ -95,7 +95,7 @@ static inline int register_cmp_smp_ops(void)
static inline int register_vsmp_smp_ops(void)
{
#ifdef CONFIG_MIPS_MT_SMP
extern struct plat_smp_ops vsmp_smp_ops;
extern const struct plat_smp_ops vsmp_smp_ops;
register_smp_ops(&vsmp_smp_ops);
......
......@@ -58,7 +58,7 @@ extern void calculate_cpu_foreign_map(void);
*/
static inline void smp_send_reschedule(int cpu)
{
extern struct plat_smp_ops *mp_ops; /* private */
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
}
......@@ -66,14 +66,14 @@ static inline void smp_send_reschedule(int cpu)
#ifdef CONFIG_HOTPLUG_CPU
static inline int __cpu_disable(void)
{
extern struct plat_smp_ops *mp_ops; /* private */
extern const struct plat_smp_ops *mp_ops; /* private */
return mp_ops->cpu_disable();
}
static inline void __cpu_die(unsigned int cpu)
{
extern struct plat_smp_ops *mp_ops; /* private */
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->cpu_die(cpu);
}
......@@ -97,14 +97,14 @@ int mips_smp_ipi_free(const struct cpumask *mask);
static inline void arch_send_call_function_single_ipi(int cpu)
{
extern struct plat_smp_ops *mp_ops; /* private */
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->send_ipi_mask(cpumask_of(cpu), SMP_CALL_FUNCTION);
}
static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
extern struct plat_smp_ops *mp_ops; /* private */
extern const struct plat_smp_ops *mp_ops; /* private */
mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
}
......
......@@ -19,20 +19,43 @@
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
/* Make the addition of cfi info a little easier. */
.macro cfi_rel_offset reg offset=0 docfi=0
.if \docfi
.cfi_rel_offset \reg, \offset
.endif
.endm
.macro cfi_st reg offset=0 docfi=0
LONG_S \reg, \offset(sp)
cfi_rel_offset \reg, \offset, \docfi
.endm
.macro cfi_restore reg offset=0 docfi=0
.if \docfi
.cfi_restore \reg
.endif
.endm
.macro cfi_ld reg offset=0 docfi=0
LONG_L \reg, \offset(sp)
cfi_restore \reg \offset \docfi
.endm
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
#define STATMASK 0x3f
#else
#define STATMASK 0x1f
#endif
.macro SAVE_AT
.macro SAVE_AT docfi=0
.set push
.set noat
LONG_S $1, PT_R1(sp)
cfi_st $1, PT_R1, \docfi
.set pop
.endm
.macro SAVE_TEMP
.macro SAVE_TEMP docfi=0
#ifdef CONFIG_CPU_HAS_SMARTMIPS
mflhxu v1
LONG_S v1, PT_LO(sp)
......@@ -44,20 +67,20 @@
mfhi v1
#endif
#ifdef CONFIG_32BIT
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
cfi_st $8, PT_R8, \docfi
cfi_st $9, PT_R9, \docfi
#endif
LONG_S $10, PT_R10(sp)
LONG_S $11, PT_R11(sp)
LONG_S $12, PT_R12(sp)
cfi_st $10, PT_R10, \docfi
cfi_st $11, PT_R11, \docfi
cfi_st $12, PT_R12, \docfi
#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
LONG_S v1, PT_HI(sp)
mflo v1
#endif
LONG_S $13, PT_R13(sp)
LONG_S $14, PT_R14(sp)
LONG_S $15, PT_R15(sp)
LONG_S $24, PT_R24(sp)
cfi_st $13, PT_R13, \docfi
cfi_st $14, PT_R14, \docfi
cfi_st $15, PT_R15, \docfi
cfi_st $24, PT_R24, \docfi
#if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
LONG_S v1, PT_LO(sp)
#endif
......@@ -71,20 +94,28 @@
#endif
.endm
.macro SAVE_STATIC
LONG_S $16, PT_R16(sp)
LONG_S $17, PT_R17(sp)
LONG_S $18, PT_R18(sp)
LONG_S $19, PT_R19(sp)
LONG_S $20, PT_R20(sp)
LONG_S $21, PT_R21(sp)
LONG_S $22, PT_R22(sp)
LONG_S $23, PT_R23(sp)
LONG_S $30, PT_R30(sp)
.macro SAVE_STATIC docfi=0
cfi_st $16, PT_R16, \docfi
cfi_st $17, PT_R17, \docfi
cfi_st $18, PT_R18, \docfi
cfi_st $19, PT_R19, \docfi
cfi_st $20, PT_R20, \docfi
cfi_st $21, PT_R21, \docfi
cfi_st $22, PT_R22, \docfi
cfi_st $23, PT_R23, \docfi
cfi_st $30, PT_R30, \docfi
.endm
/*
* get_saved_sp returns the SP for the current CPU by looking in the
* kernelsp array for it. If tosp is set, it stores the current sp in
* k0 and loads the new value in sp. If not, it clobbers k0 and
* stores the new value in k1, leaving sp unaffected.
*/
#ifdef CONFIG_SMP
.macro get_saved_sp /* SMP variation */
/* SMP variation */
.macro get_saved_sp docfi=0 tosp=0
ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
lui k1, %hi(kernelsp)
......@@ -97,7 +128,15 @@
#endif
LONG_SRL k0, SMP_CPUID_PTRSHIFT
LONG_ADDU k1, k0
.if \tosp
move k0, sp
.if \docfi
.cfi_register sp, k0
.endif
LONG_L sp, %lo(kernelsp)(k1)
.else
LONG_L k1, %lo(kernelsp)(k1)
.endif
.endm
.macro set_saved_sp stackp temp temp2
......@@ -106,7 +145,8 @@
LONG_S \stackp, kernelsp(\temp)
.endm
#else /* !CONFIG_SMP */
.macro get_saved_sp /* Uniprocessor variation */
/* Uniprocessor variation */
.macro get_saved_sp docfi=0 tosp=0
#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
/*
* Clear BTB (branch target buffer), forbid RAS (return address
......@@ -135,7 +175,15 @@
daddiu k1, %hi(kernelsp)
dsll k1, k1, 16
#endif
.if \tosp
move k0, sp
.if \docfi
.cfi_register sp, k0
.endif
LONG_L sp, %lo(kernelsp)(k1)
.else
LONG_L k1, %lo(kernelsp)(k1)
.endif
.endm
.macro set_saved_sp stackp temp temp2
......@@ -143,7 +191,7 @@
.endm
#endif
.macro SAVE_SOME
.macro SAVE_SOME docfi=0
.set push
.set noat
.set reorder
......@@ -151,7 +199,6 @@
sll k0, 3 /* extract cu0 bit */
.set noreorder
bltz k0, 8f
move k1, sp
#ifdef CONFIG_EVA
/*
* Flush interAptiv's Return Prediction Stack (RPS) by writing
......@@ -178,20 +225,26 @@
MTC0 k0, CP0_ENTRYHI
#endif
.set reorder
move k0, sp
.if \docfi
.cfi_register sp, k0
.endif
/* Called from user mode, new stack. */
get_saved_sp
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
8: move k0, sp
PTR_SUBU sp, k1, PT_SIZE
#else
.set at=k0
8: PTR_SUBU k1, PT_SIZE
get_saved_sp docfi=\docfi tosp=1
8:
#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
.set at=k1
#endif
PTR_SUBU sp, PT_SIZE
#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
.set noat
move k0, sp
move sp, k1
#endif
LONG_S k0, PT_R29(sp)
LONG_S $3, PT_R3(sp)
.if \docfi
.cfi_def_cfa sp,0
.endif
cfi_st k0, PT_R29, \docfi
cfi_rel_offset sp, PT_R29, \docfi
cfi_st v1, PT_R3, \docfi
/*
* You might think that you don't need to save $0,
* but the FPU emulator and gdb remote debug stub
......@@ -199,23 +252,26 @@
*/
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
cfi_st v0, PT_R2, \docfi
LONG_S v1, PT_STATUS(sp)
LONG_S $4, PT_R4(sp)
cfi_st $4, PT_R4, \docfi
mfc0 v1, CP0_CAUSE
LONG_S $5, PT_R5(sp)
cfi_st $5, PT_R5, \docfi
LONG_S v1, PT_CAUSE(sp)
LONG_S $6, PT_R6(sp)
MFC0 v1, CP0_EPC
LONG_S $7, PT_R7(sp)
cfi_st $6, PT_R6, \docfi
cfi_st ra, PT_R31, \docfi
MFC0 ra, CP0_EPC
cfi_st $7, PT_R7, \docfi
#ifdef CONFIG_64BIT
LONG_S $8, PT_R8(sp)
LONG_S $9, PT_R9(sp)
cfi_st $8, PT_R8, \docfi
cfi_st $9, PT_R9, \docfi
#endif
LONG_S v1, PT_EPC(sp)
LONG_S $25, PT_R25(sp)
LONG_S $28, PT_R28(sp)
LONG_S $31, PT_R31(sp)
LONG_S ra, PT_EPC(sp)
.if \docfi
.cfi_rel_offset ra, PT_EPC
.endif
cfi_st $25, PT_R25, \docfi
cfi_st $28, PT_R28, \docfi
/* Set thread_info if we're coming from user mode */
mfc0 k0, CP0_STATUS
......@@ -232,21 +288,21 @@
.set pop
.endm
.macro SAVE_ALL
SAVE_SOME
SAVE_AT
SAVE_TEMP
SAVE_STATIC
.macro SAVE_ALL docfi=0
SAVE_SOME \docfi
SAVE_AT \docfi
SAVE_TEMP \docfi
SAVE_STATIC \docfi
.endm
.macro RESTORE_AT
.macro RESTORE_AT docfi=0
.set push
.set noat
LONG_L $1, PT_R1(sp)
cfi_ld $1, PT_R1, \docfi
.set pop
.endm
.macro RESTORE_TEMP
.macro RESTORE_TEMP docfi=0
#ifdef CONFIG_CPU_CAVIUM_OCTEON
/* Restore the Octeon multiplier state */
jal octeon_mult_restore
......@@ -265,33 +321,37 @@
mthi $24
#endif
#ifdef CONFIG_32BIT
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
cfi_ld $8, PT_R8, \docfi
cfi_ld $9, PT_R9, \docfi
#endif
LONG_L $10, PT_R10(sp)
LONG_L $11, PT_R11(sp)
LONG_L $12, PT_R12(sp)
LONG_L $13, PT_R13(sp)
LONG_L $14, PT_R14(sp)
LONG_L $15, PT_R15(sp)
LONG_L $24, PT_R24(sp)
cfi_ld $10, PT_R10, \docfi
cfi_ld $11, PT_R11, \docfi
cfi_ld $12, PT_R12, \docfi
cfi_ld $13, PT_R13, \docfi
cfi_ld $14, PT_R14, \docfi
cfi_ld $15, PT_R15, \docfi
cfi_ld $24, PT_R24, \docfi
.endm
.macro RESTORE_STATIC docfi=0
cfi_ld $16, PT_R16, \docfi
cfi_ld $17, PT_R17, \docfi
cfi_ld $18, PT_R18, \docfi
cfi_ld $19, PT_R19, \docfi
cfi_ld $20, PT_R20, \docfi
cfi_ld $21, PT_R21, \docfi
cfi_ld $22, PT_R22, \docfi
cfi_ld $23, PT_R23, \docfi
cfi_ld $30, PT_R30, \docfi
.endm
.macro RESTORE_STATIC
LONG_L $16, PT_R16(sp)
LONG_L $17, PT_R17(sp)
LONG_L $18, PT_R18(sp)
LONG_L $19, PT_R19(sp)
LONG_L $20, PT_R20(sp)
LONG_L $21, PT_R21(sp)
LONG_L $22, PT_R22(sp)
LONG_L $23, PT_R23(sp)
LONG_L $30, PT_R30(sp)
.macro RESTORE_SP docfi=0
cfi_ld sp, PT_R29, \docfi
.endm
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
.macro RESTORE_SOME
.macro RESTORE_SOME docfi=0
.set push
.set reorder
.set noat
......@@ -306,30 +366,30 @@
and v0, v1
or v0, a0
mtc0 v0, CP0_STATUS
LONG_L $31, PT_R31(sp)
LONG_L $28, PT_R28(sp)
LONG_L $25, PT_R25(sp)
LONG_L $7, PT_R7(sp)
LONG_L $6, PT_R6(sp)
LONG_L $5, PT_R5(sp)
LONG_L $4, PT_R4(sp)
LONG_L $3, PT_R3(sp)
LONG_L $2, PT_R2(sp)
cfi_ld $31, PT_R31, \docfi
cfi_ld $28, PT_R28, \docfi
cfi_ld $25, PT_R25, \docfi
cfi_ld $7, PT_R7, \docfi
cfi_ld $6, PT_R6, \docfi
cfi_ld $5, PT_R5, \docfi
cfi_ld $4, PT_R4, \docfi
cfi_ld $3, PT_R3, \docfi
cfi_ld $2, PT_R2, \docfi
.set pop
.endm
.macro RESTORE_SP_AND_RET
.macro RESTORE_SP_AND_RET docfi=0
.set push
.set noreorder
LONG_L k0, PT_EPC(sp)
LONG_L sp, PT_R29(sp)
RESTORE_SP \docfi
jr k0
rfe
.set pop
.endm
#else
.macro RESTORE_SOME
.macro RESTORE_SOME docfi=0
.set push
.set reorder
.set noat
......@@ -346,24 +406,24 @@
mtc0 v0, CP0_STATUS
LONG_L v1, PT_EPC(sp)
MTC0 v1, CP0_EPC
LONG_L $31, PT_R31(sp)
LONG_L $28, PT_R28(sp)
LONG_L $25, PT_R25(sp)
cfi_ld $31, PT_R31, \docfi
cfi_ld $28, PT_R28, \docfi
cfi_ld $25, PT_R25, \docfi
#ifdef CONFIG_64BIT
LONG_L $8, PT_R8(sp)
LONG_L $9, PT_R9(sp)
cfi_ld $8, PT_R8, \docfi
cfi_ld $9, PT_R9, \docfi
#endif
LONG_L $7, PT_R7(sp)
LONG_L $6, PT_R6(sp)
LONG_L $5, PT_R5(sp)
LONG_L $4, PT_R4(sp)
LONG_L $3, PT_R3(sp)
LONG_L $2, PT_R2(sp)
cfi_ld $7, PT_R7, \docfi
cfi_ld $6, PT_R6, \docfi
cfi_ld $5, PT_R5, \docfi
cfi_ld $4, PT_R4, \docfi
cfi_ld $3, PT_R3, \docfi
cfi_ld $2, PT_R2, \docfi
.set pop
.endm
.macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp)
.macro RESTORE_SP_AND_RET docfi=0
RESTORE_SP \docfi
#ifdef CONFIG_CPU_MIPSR6
eretnc
#else
......@@ -375,16 +435,12 @@
#endif
.macro RESTORE_SP
LONG_L sp, PT_R29(sp)
.endm
.macro RESTORE_ALL
RESTORE_TEMP
RESTORE_STATIC
RESTORE_AT
RESTORE_SOME
RESTORE_SP
.macro RESTORE_ALL docfi=0
RESTORE_TEMP \docfi
RESTORE_STATIC \docfi
RESTORE_AT \docfi
RESTORE_SOME \docfi
RESTORE_SP \docfi
.endm
/*
......
......@@ -2,6 +2,8 @@
#define _ASM_STACKTRACE_H
#include <asm/ptrace.h>
#include <asm/asm.h>
#include <linux/stringify.h>
#ifdef CONFIG_KALLSYMS
extern int raw_show_trace;
......@@ -20,6 +22,14 @@ static inline unsigned long unwind_stack(struct task_struct *task,
}
#endif
#define STR_PTR_LA __stringify(PTR_LA)
#define STR_LONG_S __stringify(LONG_S)
#define STR_LONG_L __stringify(LONG_L)
#define STR_LONGSIZE __stringify(LONGSIZE)
#define STORE_ONE_REG(r) \
STR_LONG_S " $" __stringify(r)",("STR_LONGSIZE"*"__stringify(r)")(%1)\n\t"
static __always_inline void prepare_frametrace(struct pt_regs *regs)
{
#ifndef CONFIG_KALLSYMS
......@@ -32,21 +42,47 @@ static __always_inline void prepare_frametrace(struct pt_regs *regs)
__asm__ __volatile__(
".set push\n\t"
".set noat\n\t"
#ifdef CONFIG_64BIT
"1: dla $1, 1b\n\t"
"sd $1, %0\n\t"
"sd $29, %1\n\t"
"sd $31, %2\n\t"
#else
"1: la $1, 1b\n\t"
"sw $1, %0\n\t"
"sw $29, %1\n\t"
"sw $31, %2\n\t"
#endif
/* Store $1 so we can use it */
STR_LONG_S " $1,"STR_LONGSIZE"(%1)\n\t"
/* Store the PC */
"1: " STR_PTR_LA " $1, 1b\n\t"
STR_LONG_S " $1,%0\n\t"
STORE_ONE_REG(2)
STORE_ONE_REG(3)
STORE_ONE_REG(4)
STORE_ONE_REG(5)
STORE_ONE_REG(6)
STORE_ONE_REG(7)
STORE_ONE_REG(8)
STORE_ONE_REG(9)
STORE_ONE_REG(10)
STORE_ONE_REG(11)
STORE_ONE_REG(12)
STORE_ONE_REG(13)
STORE_ONE_REG(14)
STORE_ONE_REG(15)
STORE_ONE_REG(16)
STORE_ONE_REG(17)
STORE_ONE_REG(18)
STORE_ONE_REG(19)
STORE_ONE_REG(20)
STORE_ONE_REG(21)
STORE_ONE_REG(22)
STORE_ONE_REG(23)
STORE_ONE_REG(24)
STORE_ONE_REG(25)
STORE_ONE_REG(26)
STORE_ONE_REG(27)
STORE_ONE_REG(28)
STORE_ONE_REG(29)
STORE_ONE_REG(30)
STORE_ONE_REG(31)
/* Restore $1 */
STR_LONG_L " $1,"STR_LONGSIZE"(%1)\n\t"
".set pop\n\t"
: "=m" (regs->cp0_epc),
"=m" (regs->regs[29]), "=m" (regs->regs[31])
: : "memory");
: "=m" (regs->cp0_epc)
: "r" (regs->regs)
: "memory");
}
#endif /* _ASM_STACKTRACE_H */
......@@ -13,7 +13,7 @@
#ifdef CONFIG_SMP
#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
#define topology_core_id(cpu) (cpu_data[cpu].core)
#define topology_core_id(cpu) (cpu_core(&cpu_data[cpu]))
#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
#define topology_sibling_cpumask(cpu) (&cpu_sibling_map[cpu])
#endif
......
......@@ -981,7 +981,7 @@ struct mm16_r3_format { /* Load from global pointer format */
struct mm16_r5_format { /* Load/store from stack pointer format */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(signed int simmediate : 5,
__BITFIELD_FIELD(unsigned int imm : 5,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))))
};
......
......@@ -35,11 +35,15 @@ obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
sw-y := r4k_switch.o
sw-$(CONFIG_CPU_R3000) := r2300_switch.o
sw-$(CONFIG_CPU_TX39XX) := r2300_switch.o
sw-$(CONFIG_CPU_CAVIUM_OCTEON) := octeon_switch.o
obj-y += $(sw-y)
obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
......
......@@ -327,8 +327,8 @@ LEAF(mips_cps_get_bootcfg)
* to handle contiguous VP numbering, but no such systems yet
* exist.
*/
mfc0 t9, $3, 1
andi t9, t9, 0xff
mfc0 t9, CP0_GLOBALNUMBER
andi t9, t9, MIPS_GLOBALNUMBER_VP
#elif defined(CONFIG_MIPS_MT_SMP)
has_mt ta2, 1f
......
......@@ -326,7 +326,7 @@ static int __init fpu_disable(char *s)
__setup("nofpu", fpu_disable);
int mips_dsp_disabled;
static int mips_dsp_disabled;
static int __init dsp_disable(char *s)
{
......@@ -919,9 +919,12 @@ static void decode_configs(struct cpuinfo_mips *c)
#ifndef CONFIG_MIPS_CPS
if (cpu_has_mips_r2_r6) {
c->core = get_ebase_cpunum();
unsigned int core;
core = get_ebase_cpunum();
if (cpu_has_mipsmt)
c->core >>= fls(core_nvpes()) - 1;
core >>= fls(core_nvpes()) - 1;
cpu_set_core(c, core);
}
#endif
}
......@@ -1394,24 +1397,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
c->tlbsize = 48;
break;
case PRID_IMP_R6000:
c->cputype = CPU_R6000;
__cpu_name[cpu] = "R6000";
set_isa(c, MIPS_CPU_ISA_II);
c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
MIPS_CPU_LLSC;
c->tlbsize = 32;
break;
case PRID_IMP_R6000A:
c->cputype = CPU_R6000A;
__cpu_name[cpu] = "R6000A";
set_isa(c, MIPS_CPU_ISA_II);
c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
MIPS_CPU_LLSC;
c->tlbsize = 32;
break;
case PRID_IMP_RM7000:
c->cputype = CPU_RM7000;
__cpu_name[cpu] = "RM7000";
......@@ -2113,3 +2098,35 @@ void cpu_report(void)
if (cpu_has_msa)
pr_info("MSA revision is: %08x\n", c->msa_id);
}
void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
{
/* Ensure the core number fits in the field */
WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
MIPS_GLOBALNUMBER_CLUSTER_SHF));
cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
}
void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
{
/* Ensure the core number fits in the field */
WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
}
void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
{
/* Ensure the VP(E) ID fits in the field */
WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
/* Ensure we're not using VP(E)s without support */
WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
!IS_ENABLED(CONFIG_CPU_MIPSR6));
cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
}
......@@ -150,6 +150,7 @@ LEAF(__r4k_wait)
.align 5
BUILD_ROLLBACK_PROLOGUE handle_int
NESTED(handle_int, PT_SIZE, sp)
.cfi_signal_frame
#ifdef CONFIG_TRACE_IRQFLAGS
/*
* Check to see if the interrupted code has just disabled
......@@ -181,7 +182,7 @@ NESTED(handle_int, PT_SIZE, sp)
1:
.set pop
#endif
SAVE_ALL
SAVE_ALL docfi=1
CLI
TRACE_IRQS_OFF
......@@ -269,8 +270,8 @@ NESTED(except_vec_ejtag_debug, 0, sp)
*/
BUILD_ROLLBACK_PROLOGUE except_vec_vi
NESTED(except_vec_vi, 0, sp)
SAVE_SOME
SAVE_AT
SAVE_SOME docfi=1
SAVE_AT docfi=1
.set push
.set noreorder
PTR_LA v1, except_vec_vi_handler
......@@ -396,6 +397,7 @@ NESTED(except_vec_nmi, 0, sp)
__FINIT
NESTED(nmi_handler, PT_SIZE, sp)
.cfi_signal_frame
.set push
.set noat
/*
......@@ -478,6 +480,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
.macro __BUILD_HANDLER exception handler clear verbose ext
.align 5
NESTED(handle_\exception, PT_SIZE, sp)
.cfi_signal_frame
.set noat
SAVE_ALL
FEXPORT(handle_\exception\ext)
......@@ -485,8 +488,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
.set at
__BUILD_\verbose \exception
move a0, sp
PTR_LA ra, ret_from_exception
j do_\handler
jal do_\handler
j ret_from_exception
END(handle_\exception)
.endm
......
......@@ -11,6 +11,7 @@
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/cpu.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irqflags.h>
......
This diff is collapsed.
......@@ -12,8 +12,7 @@
#include <linux/percpu.h>
#include <linux/spinlock.h>
#include <asm/mips-cm.h>
#include <asm/mips-cpc.h>
#include <asm/mips-cps.h>
void __iomem *mips_cpc_base;
......@@ -40,13 +39,13 @@ static phys_addr_t mips_cpc_phys_base(void)
if (!mips_cm_present())
return 0;
if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX))
return 0;
/* If the CPC is already enabled, leave it so */
cpc_base = read_gcr_cpc_base();
if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
if (cpc_base & CM_GCR_CPC_BASE_CPCEN)
return cpc_base & CM_GCR_CPC_BASE_CPCBASE;
/* Otherwise, use the default address */
cpc_base = mips_cpc_default_phys_base();
......@@ -54,7 +53,7 @@ static phys_addr_t mips_cpc_phys_base(void)
return cpc_base;
/* Enable the CPC, mapped at the default address */
write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN);
return cpc_base;
}
......@@ -86,10 +85,10 @@ void mips_cpc_lock_other(unsigned int core)
return;
preempt_disable();
curr_core = current_cpu_data.core;
curr_core = cpu_core(&current_cpu_data);
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
/*
* Ensure the core-other region reflects the appropriate core &
......@@ -106,7 +105,7 @@ void mips_cpc_unlock_other(void)
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
return;
curr_core = current_cpu_data.core;
curr_core = cpu_core(&current_cpu_data);
spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
preempt_enable();
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment