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Commit 7379d96b authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'versatile/multiplatform' into next/multiplatform 

Merge "ARM Versatile multi-platform support" from Rob Herring:

Arnd lit a fire under me to dust this off and get it merged. So here it
is. The main change from prior version is I merged all the code to a
single file. It's a bigger patch than I'd like, but I don't think trying
to do it in multiple steps is worth it.

This is dependent on some solution for the default platform choice on
!MMU builds (allnoconfig) as it can't be Versatile after this series.
Arnd has some ideas on how to address that.

This is tested under QEMU. Linus previously tested this on actual h/w
and had a problem with the display identification which needs
investigation or agreement to worry about it if and when someone
actually cares.

* versatile/multiplatform:
  ARM: versatile: convert to multi-platform
  ARM: versatile: merge mach code into a single file
  ARM: versatile: switch to DT only booting and remove legacy code
  ARM: versatile: add DT based PCI detection
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parents ee5d8742 a29da136
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arch/arm/Kconfig
View file @ 7379d96b
...@@ -362,23 +362,6 @@ config ARCH_REALVIEW ...@@ -362,23 +362,6 @@ config ARCH_REALVIEW
help help
This enables support for ARM Ltd RealView boards. This enables support for ARM Ltd RealView boards.
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA
select ARM_TIMER_SP804
select ARM_VIC
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_MACH_CLKDEV
select ICST
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_SCHED_CLOCK
select VERSATILE_FPGA_IRQ
help
This enables support for ARM Ltd Versatile board.
config ARCH_CLPS711X config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
......
arch/arm/configs/versatile_defconfig
View file @ 7379d96b
...@@ -6,8 +6,8 @@ CONFIG_SLAB=y ...@@ -6,8 +6,8 @@ CONFIG_SLAB=y
CONFIG_MODULES=y CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y CONFIG_PARTITION_ADVANCED=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_VERSATILE=y CONFIG_ARCH_VERSATILE=y
CONFIG_MACH_VERSATILE_AB=y
CONFIG_AEABI=y CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y CONFIG_OABI_COMPAT=y
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
......
arch/arm/mach-versatile/Kconfig
View file @ 7379d96b
menu "Versatile platform type" config ARCH_VERSATILE
depends on ARCH_VERSATILE bool "ARM Ltd. Versatile family"
depends on ARCH_MULTI_V5
config ARCH_VERSATILE_PB select ARM_AMBA
bool "Support Versatile Platform Baseboard for ARM926EJ-S" select ARM_TIMER_SP804
default y select ARM_VIC
select CLKSRC_VERSATILE
select COMMON_CLK_VERSATILE
select CPU_ARM926T select CPU_ARM926T
select ICST
select MIGHT_HAVE_PCI select MIGHT_HAVE_PCI
select PLAT_VERSATILE
select VERSATILE_FPGA_IRQ
help help
Include support for the ARM(R) Versatile Platform Baseboard This enables support for ARM Ltd Versatile board.
for the ARM926EJ-S.
config MACH_VERSATILE_AB
bool "Support Versatile Application Baseboard for ARM926EJ-S"
select CPU_ARM926T
help
Include support for the ARM(R) Versatile Application Baseboard
for the ARM926EJ-S.
config MACH_VERSATILE_DT
bool "Support Versatile platform from device tree"
select CPU_ARM926T
select USE_OF
help
Include support for the ARM(R) Versatile/PB platform,
using the device tree for discovery
config MACH_VERSATILE_AUTO
def_bool y
depends on !ARCH_VERSATILE_PB && !MACH_VERSATILE_AB
select MACH_VERSATILE_DT
endmenu
arch/arm/mach-versatile/Makefile
View file @ 7379d96b
...@@ -2,8 +2,4 @@ ...@@ -2,8 +2,4 @@
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
obj-y := core.o obj-y := versatile_dt.o
obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o
obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o
obj-$(CONFIG_MACH_VERSATILE_DT) += versatile_dt.o
obj-$(CONFIG_PCI) += pci.o
arch/arm/mach-versatile/Makefile.boot deleted 100644 → 0
View file @ ee5d8742
zreladdr-y += 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
arch/arm/mach-versatile/core.c deleted 100644 → 0
View file @ ee5d8742
This diff is collapsed.
arch/arm/mach-versatile/core.h deleted 100644 → 0
View file @ ee5d8742
/*
* linux/arch/arm/mach-versatile/core.h
*
* Copyright (C) 2004 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_VERSATILE_H
#define __ASM_ARCH_VERSATILE_H
#include <linux/amba/bus.h>
#include <linux/of_platform.h>
#include <linux/reboot.h>
extern void __init versatile_init(void);
extern void __init versatile_init_early(void);
extern void __init versatile_init_irq(void);
extern void __init versatile_map_io(void);
extern void versatile_timer_init(void);
extern void versatile_restart(enum reboot_mode, const char *);
extern unsigned int mmc_status(struct device *dev);
#ifdef CONFIG_OF
extern struct of_dev_auxdata versatile_auxdata_lookup[];
#endif
#define APB_DEVICE(name, busid, base, plat) \
static AMBA_APB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
#define AHB_DEVICE(name, busid, base, plat) \
static AMBA_AHB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
#endif
arch/arm/mach-versatile/include/mach/clkdev.h deleted 100644 → 0
View file @ ee5d8742
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#include <plat/clock.h>
struct clk {
unsigned long rate;
const struct clk_ops *ops;
const struct icst_params *params;
void __iomem *vcoreg;
};
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
arch/arm/mach-versatile/include/mach/hardware.h deleted 100644 → 0
View file @ ee5d8742
/*
* arch/arm/mach-versatile/include/mach/hardware.h
*
* This file contains the hardware definitions of the Versatile boards.
*
* Copyright (C) 2003 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
/*
* PCI space virtual addresses
*/
#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
/* macro to get at MMIO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n))
#endif
arch/arm/mach-versatile/include/mach/irqs.h deleted 100644 → 0
View file @ ee5d8742
/*
* arch/arm/mach-versatile/include/mach/irqs.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <mach/platform.h>
/*
* IRQ interrupts definitions are the same as the INT definitions
* held within platform.h
*/
#define IRQ_VIC_START 32
#define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT)
#define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT)
#define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx)
#define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx)
#define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1)
#define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3)
#define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0)
#define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1)
#define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2)
#define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3)
#define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT)
#define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT)
#define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0)
#define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1)
#define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2)
#define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT)
#define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT)
#define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT)
#define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT)
#define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT)
#define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT)
#define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21)
#define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22)
#define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23)
#define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24)
#define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25)
#define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26)
#define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27)
#define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28)
#define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29)
#define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30)
#define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31)
#define IRQ_VIC_END (IRQ_VIC_START + 31)
/*
* FIQ interrupts definitions are the same as the INT definitions.
*/
#define FIQ_WDOGINT INT_WDOGINT
#define FIQ_SOFTINT INT_SOFTINT
#define FIQ_COMMRx INT_COMMRx
#define FIQ_COMMTx INT_COMMTx
#define FIQ_TIMERINT0_1 INT_TIMERINT0_1
#define FIQ_TIMERINT2_3 INT_TIMERINT2_3
#define FIQ_GPIOINT0 INT_GPIOINT0
#define FIQ_GPIOINT1 INT_GPIOINT1
#define FIQ_GPIOINT2 INT_GPIOINT2
#define FIQ_GPIOINT3 INT_GPIOINT3
#define FIQ_RTCINT INT_RTCINT
#define FIQ_SSPINT INT_SSPINT
#define FIQ_UARTINT0 INT_UARTINT0
#define FIQ_UARTINT1 INT_UARTINT1
#define FIQ_UARTINT2 INT_UARTINT2
#define FIQ_SCIINT INT_SCIINT
#define FIQ_CLCDINT INT_CLCDINT
#define FIQ_DMAINT INT_DMAINT
#define FIQ_PWRFAILINT INT_PWRFAILINT
#define FIQ_MBXINT INT_MBXINT
#define FIQ_GNDINT INT_GNDINT
#define FIQ_VICSOURCE21 INT_VICSOURCE21
#define FIQ_VICSOURCE22 INT_VICSOURCE22
#define FIQ_VICSOURCE23 INT_VICSOURCE23
#define FIQ_VICSOURCE24 INT_VICSOURCE24
#define FIQ_VICSOURCE25 INT_VICSOURCE25
#define FIQ_VICSOURCE26 INT_VICSOURCE26
#define FIQ_VICSOURCE27 INT_VICSOURCE27
#define FIQ_VICSOURCE28 INT_VICSOURCE28
#define FIQ_VICSOURCE29 INT_VICSOURCE29
#define FIQ_VICSOURCE30 INT_VICSOURCE30
#define FIQ_VICSOURCE31 INT_VICSOURCE31
/*
* Secondary interrupt controller
*/
#define IRQ_SIC_START 64
#define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B)
#define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B)
#define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0)
#define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1)
#define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3)
#define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3)
#define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD)
#define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH)
#define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD)
#define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC)
#define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A)
#define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A)
#define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI)
#define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH)
#define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB)
#define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0)
#define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1)
#define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2)
#define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3)
#define IRQ_SIC_END 95
#define IRQ_GPIO0_START (IRQ_SIC_END + 1)
#define IRQ_GPIO0_END (IRQ_GPIO0_START + 31)
#define IRQ_GPIO1_START (IRQ_GPIO0_END + 1)
#define IRQ_GPIO1_END (IRQ_GPIO1_START + 31)
#define IRQ_GPIO2_START (IRQ_GPIO1_END + 1)
#define IRQ_GPIO2_END (IRQ_GPIO2_START + 31)
#define IRQ_GPIO3_START (IRQ_GPIO2_END + 1)
#define IRQ_GPIO3_END (IRQ_GPIO3_START + 31)
#define NR_IRQS (IRQ_GPIO3_END + 1)
arch/arm/mach-versatile/include/mach/platform.h deleted 100644 → 0
View file @ ee5d8742
This diff is collapsed.
arch/arm/mach-versatile/include/mach/uncompress.h deleted 100644 → 0
View file @ ee5d8742
/*
* arch/arm/mach-versatile/include/mach/uncompress.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define AMBA_UART_DR (*(volatile unsigned char *)0x101F1000)
#define AMBA_UART_LCRH (*(volatile unsigned char *)0x101F102C)
#define AMBA_UART_CR (*(volatile unsigned char *)0x101F1030)
#define AMBA_UART_FR (*(volatile unsigned char *)0x101F1018)
/*
* This does not append a newline
*/
static inline void putc(int c)
{
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = c;
}
static inline void flush(void)
{
while (AMBA_UART_FR & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
arch/arm/mach-versatile/pci.c deleted 100644 → 0
View file @ ee5d8742
/*
* linux/arch/arm/mach-versatile/pci.c
*
* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
* You can redistribute and/or modify this software under the terms of version 2
* of the GNU General Public License as published by the Free Software Foundation.
* THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
*
* ARM Versatile PCI driver.
*
* 14/04/2005 Initial version, colin.king@philips.com
*
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
/*
* these spaces are mapped using the following base registers:
*
* Usage Local Bus Memory Base/Map registers used
*
* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
* Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
* IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
* Cfg 42000000 - 42FFFFFF PCI config
*
*/
#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x1c)
#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
#define DEVICE_ID_OFFSET 0x00
#define CSR_OFFSET 0x04
#define CLASS_ID_OFFSET 0x08
#define VP_PCI_DEVICE_ID 0x030010ee
#define VP_PCI_CLASS_ID 0x0b400000
static unsigned long pci_slot_ignore = 0;
static int __init versatile_pci_slot_ignore(char *str)
{
int retval;
int slot;
while ((retval = get_option(&str,&slot))) {
if ((slot < 0) || (slot > 31)) {
printk("Illegal slot value: %d\n",slot);
} else {
pci_slot_ignore |= (1 << slot);
}
}
return 1;
}
__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
static void __iomem *__pci_addr(struct pci_bus *bus,
unsigned int devfn, int offset)
{
unsigned int busnr = bus->number;
/*
* Trap out illegal values
*/
if (offset > 255)
BUG();
if (busnr > 255)
BUG();
if (devfn > 255)
BUG();
return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
}
static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *val)
{
void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
u32 v;
int slot = PCI_SLOT(devfn);
if (pci_slot_ignore & (1 << slot)) {
/* Ignore this slot */
switch (size) {
case 1:
v = 0xff;
break;
case 2:
v = 0xffff;
break;
default:
v = 0xffffffff;
}
} else {
switch (size) {
case 1:
v = __raw_readl(addr);
if (where & 2) v >>= 16;
if (where & 1) v >>= 8;
v &= 0xff;
break;
case 2:
v = __raw_readl(addr);
if (where & 2) v >>= 16;
v &= 0xffff;
break;
default:
v = __raw_readl(addr);
break;
}
}
*val = v;
return PCIBIOS_SUCCESSFUL;
}
static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
void __iomem *addr = __pci_addr(bus, devfn, where);
int slot = PCI_SLOT(devfn);
if (pci_slot_ignore & (1 << slot)) {
return PCIBIOS_SUCCESSFUL;
}
switch (size) {
case 1:
__raw_writeb((u8)val, addr);
break;
case 2:
__raw_writew((u16)val, addr);
break;
case 4:
__raw_writel(val, addr);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops pci_versatile_ops = {
.read = versatile_read_config,
.write = versatile_write_config,
};
static struct resource unused_mem = {
.name = "PCI unused",
.start = VERSATILE_PCI_MEM_BASE0,
.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
.flags = IORESOURCE_MEM,
};
static struct resource non_mem = {
.name = "PCI non-prefetchable",
.start = VERSATILE_PCI_MEM_BASE1,
.end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
.flags = IORESOURCE_MEM,
};
static struct resource pre_mem = {
.name = "PCI prefetchable",
.start = VERSATILE_PCI_MEM_BASE2,
.end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
};
static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
{
int ret = 0;
ret = request_resource(&iomem_resource, &unused_mem);
if (ret) {
printk(KERN_ERR "PCI: unable to allocate unused "
"memory region (%d)\n", ret);
goto out;
}
ret = request_resource(&iomem_resource, &non_mem);
if (ret) {
printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
"memory region (%d)\n", ret);
goto release_unused_mem;
}
ret = request_resource(&iomem_resource, &pre_mem);
if (ret) {
printk(KERN_ERR "PCI: unable to allocate prefetchable "
"memory region (%d)\n", ret);
goto release_non_mem;
}
/*
* the mem resource for this bus
* the prefetch mem resource for this bus
*/
pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
goto out;
release_non_mem:
release_resource(&non_mem);
release_unused_mem:
release_resource(&unused_mem);
out:
return ret;
}
int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
int i;
int myslot = -1;
unsigned long val;
void __iomem *local_pci_cfg_base;
val = __raw_readl(SYS_PCICTL);
if (!(val & 1)) {
printk("Not plugged into PCI backplane!\n");
ret = -EIO;
goto out;
}
ret = pci_ioremap_io(0, VERSATILE_PCI_IO_BASE);
if (ret)
goto out;
if (nr == 0) {
ret = pci_versatile_setup_resources(sys);
if (ret < 0) {
printk("pci_versatile_setup: resources... oops?\n");
goto out;
}
} else {
printk("pci_versatile_setup: resources... nr == 0??\n");
goto out;
}
/*
* We need to discover the PCI core first to configure itself
* before the main PCI probing is performed
*/
for (i=0; i<32; i++)
if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
(__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
myslot = i;
break;
}
if (myslot == -1) {
printk("Cannot find PCI core!\n");
ret = -EIO;
goto out;
}
printk("PCI core found (slot %d)\n",myslot);
__raw_writel(myslot, PCI_SELFID);
local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
/*
* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
*/
__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
/*
* For many years the kernel and QEMU were symbiotically buggy
* in that they both assumed the same broken IRQ mapping.
* QEMU therefore attempts to auto-detect old broken kernels
* so that they still work on newer QEMU as they did on old
* QEMU. Since we now use the correct (ie matching-hardware)
* IRQ mapping we write a definitely different value to a
* PCI_INTERRUPT_LINE register to tell QEMU that we expect
* real hardware behaviour and it need not be backwards
* compatible for us. This write is harmless on real hardware.
*/
__raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE);
/*
* Do not to map Versatile FPGA PCI device into memory space
*/
pci_slot_ignore |= (1 << myslot);
ret = 1;
out:
return ret;
}
void __init pci_versatile_preinit(void)
{
pcibios_min_mem = 0x50000000;
__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
__raw_writel(1, SYS_PCICTL);
}
/*
* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
*/
static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
/*
* Slot INTA INTB INTC INTD
* 31 PCI1 PCI2 PCI3 PCI0
* 30 PCI0 PCI1 PCI2 PCI3
* 29 PCI3 PCI0 PCI1 PCI2
*/
irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);
return irq;
}
static struct hw_pci versatile_pci __initdata = {
.map_irq = versatile_map_irq,
.nr_controllers = 1,
.ops = &pci_versatile_ops,
.setup = pci_versatile_setup,
.preinit = pci_versatile_preinit,
};
static int __init versatile_pci_init(void)
{
pci_common_init(&versatile_pci);
return 0;
}
subsys_initcall(versatile_pci_init);
arch/arm/mach-versatile/versatile_ab.c deleted 100644 → 0
View file @ ee5d8742
/*
* linux/arch/arm/mach-versatile/versatile_ab.c
*
* Copyright (C) 2004 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "core.h"
MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.atag_offset = 0x100,
.map_io = versatile_map_io,
.init_early = versatile_init_early,
.init_irq = versatile_init_irq,
.init_time = versatile_timer_init,
.init_machine = versatile_init,
.restart = versatile_restart,
MACHINE_END
arch/arm/mach-versatile/versatile_dt.c
View file @ 7379d96b
This diff is collapsed.
arch/arm/mach-versatile/versatile_pb.c deleted 100644 → 0
View file @ ee5d8742
/*
* linux/arch/arm/mach-versatile/versatile_pb.c
*
* Copyright (C) 2004 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "core.h"
#if 1
#define IRQ_MMCI1A IRQ_VICSOURCE23
#else
#define IRQ_MMCI1A IRQ_SIC_MMCI1A
#endif
static struct mmci_platform_data mmc1_plat_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.status = mmc_status,
.gpio_wp = -1,
.gpio_cd = -1,
};
#define UART3_IRQ { IRQ_SIC_UART3 }
#define SCI1_IRQ { IRQ_SIC_SCI3 }
#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
/*
* These devices are connected via the DMA APB bridge
*/
/* FPGA Primecells */
APB_DEVICE(uart3, "fpga:09", UART3, NULL);
APB_DEVICE(sci1, "fpga:0a", SCI1, NULL);
APB_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data);
static struct amba_device *amba_devs[] __initdata = {
&uart3_device,
&sci1_device,
&mmc1_device,
};
static void __init versatile_pb_init(void)
{
int i;
versatile_init();
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
}
MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
.atag_offset = 0x100,
.map_io = versatile_map_io,
.init_early = versatile_init_early,
.init_irq = versatile_init_irq,
.init_time = versatile_timer_init,
.init_machine = versatile_pb_init,
.restart = versatile_restart,
MACHINE_END
drivers/clk/versatile/Kconfig
View file @ 7379d96b
config COMMON_CLK_VERSATILE config COMMON_CLK_VERSATILE
bool "Clock driver for ARM Reference designs" bool "Clock driver for ARM Reference designs"
depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS || ARM64 || COMPILE_TEST depends on ARCH_INTEGRATOR || ARCH_REALVIEW || \
ARCH_VERSATILE || ARCH_VEXPRESS || ARM64 || \
COMPILE_TEST
---help--- ---help---
Supports clocking on ARM Reference designs: Supports clocking on ARM Reference designs:
- Integrator/AP and Integrator/CP - Integrator/AP and Integrator/CP
......
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