Skip to content

L
linux
Commit 73852b2b authored by David S. Miller's avatar David S. Miller
Browse files
Options

tulip: dmfe: Fix global namespace pollution of phy accessors. 

The dmfe driver has "phy_read()" and "phy_write()" functions, which
we need to rename because the generic phy layer is about to export
generic interfaces with the same name.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c2c0e8b2
Show whitespace changes
Inline Side-by-side
Showing with 76 additions and 76 deletions
drivers/net/ethernet/dec/tulip/dmfe.c
View file @ 73852b2b
...@@ -328,10 +328,10 @@ static void allocate_rx_buffer(struct net_device *); ...@@ -328,10 +328,10 @@ static void allocate_rx_buffer(struct net_device *);
static void update_cr6(u32, void __iomem *); static void update_cr6(u32, void __iomem *);
static void send_filter_frame(struct DEVICE *); static void send_filter_frame(struct DEVICE *);
static void dm9132_id_table(struct DEVICE *); static void dm9132_id_table(struct DEVICE *);
static u16 phy_read(void __iomem *, u8, u8, u32); static u16 dmfe_phy_read(void __iomem *, u8, u8, u32);
static void phy_write(void __iomem *, u8, u8, u16, u32); static void dmfe_phy_write(void __iomem *, u8, u8, u16, u32);
static void phy_write_1bit(void __iomem *, u32); static void dmfe_phy_write_1bit(void __iomem *, u32);
static u16 phy_read_1bit(void __iomem *); static u16 dmfe_phy_read_1bit(void __iomem *);
static u8 dmfe_sense_speed(struct dmfe_board_info *); static u8 dmfe_sense_speed(struct dmfe_board_info *);
static void dmfe_process_mode(struct dmfe_board_info *); static void dmfe_process_mode(struct dmfe_board_info *);
static void dmfe_timer(unsigned long); static void dmfe_timer(unsigned long);
...@@ -770,7 +770,7 @@ static int dmfe_stop(struct DEVICE *dev) ...@@ -770,7 +770,7 @@ static int dmfe_stop(struct DEVICE *dev)
/* Reset & stop DM910X board */ /* Reset & stop DM910X board */
dw32(DCR0, DM910X_RESET); dw32(DCR0, DM910X_RESET);
udelay(100); udelay(100);
phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
/* free interrupt */ /* free interrupt */
free_irq(db->pdev->irq, dev); free_irq(db->pdev->irq, dev);
...@@ -1154,7 +1154,7 @@ static void dmfe_timer(unsigned long data) ...@@ -1154,7 +1154,7 @@ static void dmfe_timer(unsigned long data)
if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) { if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
db->cr6_data &= ~0x40000; db->cr6_data &= ~0x40000;
update_cr6(db->cr6_data, ioaddr); update_cr6(db->cr6_data, ioaddr);
phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
db->cr6_data |= 0x40000; db->cr6_data |= 0x40000;
update_cr6(db->cr6_data, ioaddr); update_cr6(db->cr6_data, ioaddr);
db->timer.expires = DMFE_TIMER_WUT + HZ * 2; db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
...@@ -1230,8 +1230,8 @@ static void dmfe_timer(unsigned long data) ...@@ -1230,8 +1230,8 @@ static void dmfe_timer(unsigned long data)
*/ */
/* need a dummy read because of PHY's register latch*/ /* need a dummy read because of PHY's register latch*/
phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id); dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
link_ok_phy = (phy_read (db->ioaddr, link_ok_phy = (dmfe_phy_read (db->ioaddr,
db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0; db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
if (link_ok_phy != link_ok) { if (link_ok_phy != link_ok) {
...@@ -1247,7 +1247,7 @@ static void dmfe_timer(unsigned long data) ...@@ -1247,7 +1247,7 @@ static void dmfe_timer(unsigned long data)
/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
/* AUTO or force 1M Homerun/Longrun don't need */ /* AUTO or force 1M Homerun/Longrun don't need */
if ( !(db->media_mode & 0x38) ) if ( !(db->media_mode & 0x38) )
phy_write(db->ioaddr, db->phy_addr, dmfe_phy_write(db->ioaddr, db->phy_addr,
0, 0x1000, db->chip_id); 0, 0x1000, db->chip_id);
/* AUTO mode, if INT phyxcer link failed, select EXT device */ /* AUTO mode, if INT phyxcer link failed, select EXT device */
...@@ -1649,15 +1649,15 @@ static u8 dmfe_sense_speed(struct dmfe_board_info *db) ...@@ -1649,15 +1649,15 @@ static u8 dmfe_sense_speed(struct dmfe_board_info *db)
/* CR6 bit18=0, select 10/100M */ /* CR6 bit18=0, select 10/100M */
update_cr6(db->cr6_data & ~0x40000, ioaddr); update_cr6(db->cr6_data & ~0x40000, ioaddr);
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
if ( (phy_mode & 0x24) == 0x24 ) { if ( (phy_mode & 0x24) == 0x24 ) {
if (db->chip_id == PCI_DM9132_ID) /* DM9132 */ if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
phy_mode = phy_read(db->ioaddr, phy_mode = dmfe_phy_read(db->ioaddr,
db->phy_addr, 7, db->chip_id) & 0xf000; db->phy_addr, 7, db->chip_id) & 0xf000;
else /* DM9102/DM9102A */ else /* DM9102/DM9102A */
phy_mode = phy_read(db->ioaddr, phy_mode = dmfe_phy_read(db->ioaddr,
db->phy_addr, 17, db->chip_id) & 0xf000; db->phy_addr, 17, db->chip_id) & 0xf000;
switch (phy_mode) { switch (phy_mode) {
case 0x1000: db->op_mode = DMFE_10MHF; break; case 0x1000: db->op_mode = DMFE_10MHF; break;
...@@ -1695,15 +1695,15 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db) ...@@ -1695,15 +1695,15 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
/* DM9009 Chip: Phyxcer reg18 bit12=0 */ /* DM9009 Chip: Phyxcer reg18 bit12=0 */
if (db->chip_id == PCI_DM9009_ID) { if (db->chip_id == PCI_DM9009_ID) {
phy_reg = phy_read(db->ioaddr, phy_reg = dmfe_phy_read(db->ioaddr,
db->phy_addr, 18, db->chip_id) & ~0x1000; db->phy_addr, 18, db->chip_id) & ~0x1000;
phy_write(db->ioaddr, dmfe_phy_write(db->ioaddr,
db->phy_addr, 18, phy_reg, db->chip_id); db->phy_addr, 18, phy_reg, db->chip_id);
} }
/* Phyxcer capability setting */ /* Phyxcer capability setting */
phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
if (db->media_mode & DMFE_AUTO) { if (db->media_mode & DMFE_AUTO) {
/* AUTO Mode */ /* AUTO Mode */
...@@ -1724,13 +1724,13 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db) ...@@ -1724,13 +1724,13 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
phy_reg|=db->PHY_reg4; phy_reg|=db->PHY_reg4;
db->media_mode|=DMFE_AUTO; db->media_mode|=DMFE_AUTO;
} }
phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
/* Restart Auto-Negotiation */ /* Restart Auto-Negotiation */
if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
if ( !db->chip_type ) if ( !db->chip_type )
phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
} }
...@@ -1762,7 +1762,7 @@ static void dmfe_process_mode(struct dmfe_board_info *db) ...@@ -1762,7 +1762,7 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
/* 10/100M phyxcer force mode need */ /* 10/100M phyxcer force mode need */
if ( !(db->media_mode & 0x18)) { if ( !(db->media_mode & 0x18)) {
/* Forece Mode */ /* Forece Mode */
phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
if ( !(phy_reg & 0x1) ) { if ( !(phy_reg & 0x1) ) {
/* parter without N-Way capability */ /* parter without N-Way capability */
phy_reg = 0x0; phy_reg = 0x0;
...@@ -1772,11 +1772,11 @@ static void dmfe_process_mode(struct dmfe_board_info *db) ...@@ -1772,11 +1772,11 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
case DMFE_100MHF: phy_reg = 0x2000; break; case DMFE_100MHF: phy_reg = 0x2000; break;
case DMFE_100MFD: phy_reg = 0x2100; break; case DMFE_100MFD: phy_reg = 0x2100; break;
} }
phy_write(db->ioaddr, dmfe_phy_write(db->ioaddr,
db->phy_addr, 0, phy_reg, db->chip_id); db->phy_addr, 0, phy_reg, db->chip_id);
if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
mdelay(20); mdelay(20);
phy_write(db->ioaddr, dmfe_phy_write(db->ioaddr,
db->phy_addr, 0, phy_reg, db->chip_id); db->phy_addr, 0, phy_reg, db->chip_id);
} }
} }
...@@ -1787,7 +1787,7 @@ static void dmfe_process_mode(struct dmfe_board_info *db) ...@@ -1787,7 +1787,7 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
* Write a word to Phy register * Write a word to Phy register
*/ */
static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset, static void dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
u16 phy_data, u32 chip_id) u16 phy_data, u32 chip_id)
{ {
u16 i; u16 i;
...@@ -1799,33 +1799,33 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset, ...@@ -1799,33 +1799,33 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
/* Send 33 synchronization clock to Phy controller */ /* Send 33 synchronization clock to Phy controller */
for (i = 0; i < 35; i++) for (i = 0; i < 35; i++)
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
/* Send start command(01) to Phy */ /* Send start command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0); dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
/* Send write command(01) to Phy */ /* Send write command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0); dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
/* Send Phy address */ /* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1) for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, dmfe_phy_write_1bit(ioaddr,
phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
/* Send register address */ /* Send register address */
for (i = 0x10; i > 0; i = i >> 1) for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, dmfe_phy_write_1bit(ioaddr,
offset & i ? PHY_DATA_1 : PHY_DATA_0); offset & i ? PHY_DATA_1 : PHY_DATA_0);
/* written trasnition */ /* written trasnition */
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
phy_write_1bit(ioaddr, PHY_DATA_0); dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
/* Write a word data to PHY controller */ /* Write a word data to PHY controller */
for ( i = 0x8000; i > 0; i >>= 1) for ( i = 0x8000; i > 0; i >>= 1)
phy_write_1bit(ioaddr, dmfe_phy_write_1bit(ioaddr,
phy_data & i ? PHY_DATA_1 : PHY_DATA_0); phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
} }
} }
...@@ -1835,7 +1835,7 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset, ...@@ -1835,7 +1835,7 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
* Read a word data from phy register * Read a word data from phy register
*/ */
static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id) static u16 dmfe_phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
{ {
int i; int i;
u16 phy_data; u16 phy_data;
...@@ -1848,33 +1848,33 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id) ...@@ -1848,33 +1848,33 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
/* Send 33 synchronization clock to Phy controller */ /* Send 33 synchronization clock to Phy controller */
for (i = 0; i < 35; i++) for (i = 0; i < 35; i++)
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
/* Send start command(01) to Phy */ /* Send start command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0); dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
/* Send read command(10) to Phy */ /* Send read command(10) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_1); dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
phy_write_1bit(ioaddr, PHY_DATA_0); dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
/* Send Phy address */ /* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1) for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, dmfe_phy_write_1bit(ioaddr,
phy_addr & i ? PHY_DATA_1 : PHY_DATA_0); phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
/* Send register address */ /* Send register address */
for (i = 0x10; i > 0; i = i >> 1) for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, dmfe_phy_write_1bit(ioaddr,
offset & i ? PHY_DATA_1 : PHY_DATA_0); offset & i ? PHY_DATA_1 : PHY_DATA_0);
/* Skip transition state */ /* Skip transition state */
phy_read_1bit(ioaddr); dmfe_phy_read_1bit(ioaddr);
/* read 16bit data */ /* read 16bit data */
for (phy_data = 0, i = 0; i < 16; i++) { for (phy_data = 0, i = 0; i < 16; i++) {
phy_data <<= 1; phy_data <<= 1;
phy_data |= phy_read_1bit(ioaddr); phy_data |= dmfe_phy_read_1bit(ioaddr);
} }
} }
...@@ -1886,7 +1886,7 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id) ...@@ -1886,7 +1886,7 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
* Write one bit data to Phy Controller * Write one bit data to Phy Controller
*/ */
static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data) static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
{ {
dw32(DCR9, phy_data); /* MII Clock Low */ dw32(DCR9, phy_data); /* MII Clock Low */
udelay(1); udelay(1);
...@@ -1901,7 +1901,7 @@ static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data) ...@@ -1901,7 +1901,7 @@ static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
* Read one bit phy data from PHY controller * Read one bit phy data from PHY controller
*/ */
static u16 phy_read_1bit(void __iomem *ioaddr) static u16 dmfe_phy_read_1bit(void __iomem *ioaddr)
{ {
u16 phy_data; u16 phy_data;
...@@ -1995,11 +1995,11 @@ static void dmfe_parse_srom(struct dmfe_board_info * db) ...@@ -1995,11 +1995,11 @@ static void dmfe_parse_srom(struct dmfe_board_info * db)
/* Check DM9801 or DM9802 present or not */ /* Check DM9801 or DM9802 present or not */
db->HPNA_present = 0; db->HPNA_present = 0;
update_cr6(db->cr6_data | 0x40000, db->ioaddr); update_cr6(db->cr6_data | 0x40000, db->ioaddr);
tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id); tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) { if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
/* DM9801 or DM9802 present */ /* DM9801 or DM9802 present */
db->HPNA_timer = 8; db->HPNA_timer = 8;
if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) { if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
/* DM9801 HomeRun */ /* DM9801 HomeRun */
db->HPNA_present = 1; db->HPNA_present = 1;
dmfe_program_DM9801(db, tmp_reg); dmfe_program_DM9801(db, tmp_reg);
...@@ -2025,29 +2025,29 @@ static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev) ...@@ -2025,29 +2025,29 @@ static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
switch(HPNA_rev) { switch(HPNA_rev) {
case 0xb900: /* DM9801 E3 */ case 0xb900: /* DM9801 E3 */
db->HPNA_command |= 0x1000; db->HPNA_command |= 0x1000;
reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id); reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000; reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
break; break;
case 0xb901: /* DM9801 E4 */ case 0xb901: /* DM9801 E4 */
reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor; reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3; reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
break; break;
case 0xb902: /* DM9801 E5 */ case 0xb902: /* DM9801 E5 */
case 0xb903: /* DM9801 E6 */ case 0xb903: /* DM9801 E6 */
default: default:
db->HPNA_command |= 0x1000; db->HPNA_command |= 0x1000;
reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5; reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor; reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
break; break;
} }
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
} }
...@@ -2060,10 +2060,10 @@ static void dmfe_program_DM9802(struct dmfe_board_info * db) ...@@ -2060,10 +2060,10 @@ static void dmfe_program_DM9802(struct dmfe_board_info * db)
uint phy_reg; uint phy_reg;
if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR; if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor; phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id); dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
} }
...@@ -2077,7 +2077,7 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db) ...@@ -2077,7 +2077,7 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
uint phy_reg; uint phy_reg;
/* Got remote device status */ /* Got remote device status */
phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60; phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
switch(phy_reg) { switch(phy_reg) {
case 0x00: phy_reg = 0x0a00;break; /* LP/LS */ case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
case 0x20: phy_reg = 0x0900;break; /* LP/HS */ case 0x20: phy_reg = 0x0900;break; /* LP/HS */
...@@ -2087,7 +2087,7 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db) ...@@ -2087,7 +2087,7 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
/* Check remote device status match our setting ot not */ /* Check remote device status match our setting ot not */
if ( phy_reg != (db->HPNA_command & 0x0f00) ) { if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
db->chip_id); db->chip_id);
db->HPNA_timer=8; db->HPNA_timer=8;
} else } else
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7