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nexedi
linux
Commits
75b368dc
Commit
75b368dc
authored
Jan 09, 2003
by
Anton Blanchard
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ppc64: remove flush_icache_page, based on same work in ppc32
parent
380ddbbd
Changes
2
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2 changed files
with
35 additions
and
31 deletions
+35
-31
arch/ppc64/mm/init.c
arch/ppc64/mm/init.c
+34
-30
include/asm-ppc64/cacheflush.h
include/asm-ppc64/cacheflush.h
+1
-1
No files found.
arch/ppc64/mm/init.c
View file @
75b368dc
...
...
@@ -592,36 +592,24 @@ void __init mem_init(void)
*/
void
flush_dcache_page
(
struct
page
*
page
)
{
/* avoid an atomic op if possible */
if
(
test_bit
(
PG_arch_1
,
&
page
->
flags
))
clear_bit
(
PG_arch_1
,
&
page
->
flags
);
}
void
flush_icache_page
(
struct
vm_area_struct
*
vma
,
struct
page
*
page
)
{
if
(
cpu_has_noexecute
())
return
;
if
((
vma
->
vm_flags
&
VM_EXEC
)
==
0
)
return
;
if
(
page
->
mapping
&&
!
PageReserved
(
page
)
&&
!
test_bit
(
PG_arch_1
,
&
page
->
flags
))
{
__flush_dcache_icache
(
page_address
(
page
));
set_bit
(
PG_arch_1
,
&
page
->
flags
);
}
}
void
clear_user_page
(
void
*
page
,
unsigned
long
vaddr
,
struct
page
*
pg
)
{
clear_page
(
page
);
/* XXX we shouldnt have to do this, but glibc requires it */
if
(
cpu_has_noexecute
())
{
/*
* We shouldnt have to do this, but some versions of glibc
* require it (ld.so assumes zero filled pages are icache clean)
* - Anton
*/
/* avoid an atomic op if possible */
if
(
test_bit
(
PG_arch_1
,
&
pg
->
flags
))
clear_bit
(
PG_arch_1
,
&
pg
->
flags
);
}
else
{
__flush_dcache_icache
(
page
);
}
}
void
copy_user_page
(
void
*
vto
,
void
*
vfrom
,
unsigned
long
vaddr
,
...
...
@@ -630,20 +618,23 @@ void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
copy_page
(
vto
,
vfrom
);
/*
* Unfortunately we havent always marked our GOT and PLT sections
* as executable, so we need to flush all file regions - Anton
* We should be able to use the following optimisation, however
* there are two problems.
* Firstly a bug in some versions of binutils meant PLT sections
* were not marked executable.
* Secondly the first word in the GOT section is blrl, used
* to establish the GOT address. Until recently the GOT was
* not marked executable.
* - Anton
*/
#if 0
if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
return;
#endif
if
(
cpu_has_noexecute
())
{
/* avoid an atomic op if possible */
if
(
test_bit
(
PG_arch_1
,
&
pg
->
flags
))
clear_bit
(
PG_arch_1
,
&
pg
->
flags
);
}
else
{
__flush_dcache_icache
(
vto
);
}
}
void
flush_icache_user_range
(
struct
vm_area_struct
*
vma
,
struct
page
*
page
,
...
...
@@ -675,6 +666,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long ea,
pte_t
*
ptep
;
int
local
=
0
;
/* handle i-cache coherency */
if
(
!
cpu_has_noexecute
())
{
unsigned
long
pfn
=
pte_pfn
(
pte
);
if
(
pfn_valid
(
pfn
))
{
struct
page
*
page
=
pfn_to_page
(
pfn
);
if
(
!
PageReserved
(
page
)
&&
!
test_bit
(
PG_arch_1
,
&
page
->
flags
))
{
__flush_dcache_icache
(
page_address
(
page
));
set_bit
(
PG_arch_1
,
&
page
->
flags
);
}
}
}
/* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
if
(
!
pte_young
(
pte
))
return
;
...
...
include/asm-ppc64/cacheflush.h
View file @
75b368dc
...
...
@@ -14,10 +14,10 @@
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr) do { } while (0)
#define flush_page_to_ram(page) do { } while (0)
#define flush_icache_page(vma, page) do { } while (0)
extern
void
flush_dcache_page
(
struct
page
*
page
);
extern
void
flush_icache_range
(
unsigned
long
,
unsigned
long
);
extern
void
flush_icache_page
(
struct
vm_area_struct
*
vma
,
struct
page
*
page
);
extern
void
flush_icache_user_range
(
struct
vm_area_struct
*
vma
,
struct
page
*
page
,
unsigned
long
addr
,
int
len
);
...
...
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