Commit 76305b1a authored by Matt Roper's avatar Matt Roper Committed by Daniel Vetter

drm/i915: Calculate watermark configuration during atomic check (v2)

v2: Don't forget to actually check the cstate->active value when
    tallying up the number of active CRTC's.  (Ander)
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a4611e44
...@@ -1692,6 +1692,13 @@ struct i915_execbuffer_params { ...@@ -1692,6 +1692,13 @@ struct i915_execbuffer_params {
struct drm_i915_gem_request *request; struct drm_i915_gem_request *request;
}; };
/* used in computing the new watermarks state */
struct intel_wm_config {
unsigned int num_pipes_active;
bool sprites_enabled;
bool sprites_scaled;
};
struct drm_i915_private { struct drm_i915_private {
struct drm_device *dev; struct drm_device *dev;
struct kmem_cache *objects; struct kmem_cache *objects;
...@@ -1912,6 +1919,9 @@ struct drm_i915_private { ...@@ -1912,6 +1919,9 @@ struct drm_i915_private {
*/ */
uint16_t skl_latency[8]; uint16_t skl_latency[8];
/* Committed wm config */
struct intel_wm_config config;
/* /*
* The skl_wm_values structure is a bit too big for stack * The skl_wm_values structure is a bit too big for stack
* allocation, so we keep the staging struct where we store * allocation, so we keep the staging struct where we store
......
...@@ -13039,6 +13039,45 @@ static int intel_modeset_checks(struct drm_atomic_state *state) ...@@ -13039,6 +13039,45 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return 0; return 0;
} }
/*
* Handle calculation of various watermark data at the end of the atomic check
* phase. The code here should be run after the per-crtc and per-plane 'check'
* handlers to ensure that all derived state has been updated.
*/
static void calc_watermark_data(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct drm_plane *plane;
struct drm_plane_state *pstate;
/*
* Calculate watermark configuration details now that derived
* plane/crtc state is all properly updated.
*/
drm_for_each_crtc(crtc, dev) {
cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
crtc->state;
if (cstate->active)
intel_state->wm_config.num_pipes_active++;
}
drm_for_each_legacy_plane(plane, dev) {
pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
plane->state;
if (!to_intel_plane_state(pstate)->visible)
continue;
intel_state->wm_config.sprites_enabled = true;
if (pstate->crtc_w != pstate->src_w >> 16 ||
pstate->crtc_h != pstate->src_h >> 16)
intel_state->wm_config.sprites_scaled = true;
}
}
/** /**
* intel_atomic_check - validate state object * intel_atomic_check - validate state object
* @dev: drm device * @dev: drm device
...@@ -13047,6 +13086,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state) ...@@ -13047,6 +13086,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
static int intel_atomic_check(struct drm_device *dev, static int intel_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state) struct drm_atomic_state *state)
{ {
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_crtc *crtc; struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state; struct drm_crtc_state *crtc_state;
int ret, i; int ret, i;
...@@ -13110,10 +13150,15 @@ static int intel_atomic_check(struct drm_device *dev, ...@@ -13110,10 +13150,15 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret) if (ret)
return ret; return ret;
} else } else
to_intel_atomic_state(state)->cdclk = intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
to_i915(state->dev)->cdclk_freq;
return drm_atomic_helper_check_planes(state->dev, state); ret = drm_atomic_helper_check_planes(state->dev, state);
if (ret)
return ret;
calc_watermark_data(state);
return 0;
} }
/** /**
...@@ -13153,6 +13198,7 @@ static int intel_atomic_commit(struct drm_device *dev, ...@@ -13153,6 +13198,7 @@ static int intel_atomic_commit(struct drm_device *dev,
return ret; return ret;
drm_atomic_helper_swap_state(dev, state); drm_atomic_helper_swap_state(dev, state);
dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
for_each_crtc_in_state(state, crtc, crtc_state, i) { for_each_crtc_in_state(state, crtc, crtc_state, i) {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
......
...@@ -248,6 +248,7 @@ struct intel_atomic_state { ...@@ -248,6 +248,7 @@ struct intel_atomic_state {
unsigned int cdclk; unsigned int cdclk;
bool dpll_set; bool dpll_set;
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
}; };
struct intel_plane_state { struct intel_plane_state {
......
...@@ -1772,13 +1772,6 @@ struct ilk_wm_maximums { ...@@ -1772,13 +1772,6 @@ struct ilk_wm_maximums {
uint16_t fbc; uint16_t fbc;
}; };
/* used in computing the new watermarks state */
struct intel_wm_config {
unsigned int num_pipes_active;
bool sprites_enabled;
bool sprites_scaled;
};
/* /*
* For both WM_PIPE and WM_LP. * For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units. * mem_value must be in 0.1us units.
...@@ -2308,24 +2301,6 @@ static void skl_setup_wm_latency(struct drm_device *dev) ...@@ -2308,24 +2301,6 @@ static void skl_setup_wm_latency(struct drm_device *dev)
intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
} }
static void ilk_compute_wm_config(struct drm_device *dev,
struct intel_wm_config *config)
{
struct intel_crtc *intel_crtc;
/* Compute the currently _active_ config */
for_each_intel_crtc(dev, intel_crtc) {
const struct intel_pipe_wm *wm = &intel_crtc->wm.active.ilk;
if (!wm->pipe_enabled)
continue;
config->sprites_enabled |= wm->sprites_enabled;
config->sprites_scaled |= wm->sprites_scaled;
config->num_pipes_active++;
}
}
/* Compute new watermarks for the pipe */ /* Compute new watermarks for the pipe */
static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc, static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
struct drm_atomic_state *state) struct drm_atomic_state *state)
...@@ -2971,11 +2946,12 @@ skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate) ...@@ -2971,11 +2946,12 @@ skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
static void static void
skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
const struct intel_wm_config *config,
struct skl_ddb_allocation *ddb /* out */) struct skl_ddb_allocation *ddb /* out */)
{ {
struct drm_crtc *crtc = cstate->base.crtc; struct drm_crtc *crtc = cstate->base.crtc;
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_wm_config *config = &dev_priv->wm.config;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane; struct intel_plane *intel_plane;
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
...@@ -3150,15 +3126,6 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, ...@@ -3150,15 +3126,6 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
return false; return false;
} }
static void skl_compute_wm_global_parameters(struct drm_device *dev,
struct intel_wm_config *config)
{
struct drm_crtc *crtc;
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
config->num_pipes_active += to_intel_crtc(crtc)->active;
}
static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate, struct intel_crtc_state *cstate,
struct intel_plane *intel_plane, struct intel_plane *intel_plane,
...@@ -3563,14 +3530,13 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv, ...@@ -3563,14 +3530,13 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
} }
static bool skl_update_pipe_wm(struct drm_crtc *crtc, static bool skl_update_pipe_wm(struct drm_crtc *crtc,
struct intel_wm_config *config,
struct skl_ddb_allocation *ddb, /* out */ struct skl_ddb_allocation *ddb, /* out */
struct skl_pipe_wm *pipe_wm /* out */) struct skl_pipe_wm *pipe_wm /* out */)
{ {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
skl_allocate_pipe_ddb(cstate, config, ddb); skl_allocate_pipe_ddb(cstate, ddb);
skl_compute_pipe_wm(cstate, ddb, pipe_wm); skl_compute_pipe_wm(cstate, ddb, pipe_wm);
if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm))) if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
...@@ -3583,7 +3549,6 @@ static bool skl_update_pipe_wm(struct drm_crtc *crtc, ...@@ -3583,7 +3549,6 @@ static bool skl_update_pipe_wm(struct drm_crtc *crtc,
static void skl_update_other_pipe_wm(struct drm_device *dev, static void skl_update_other_pipe_wm(struct drm_device *dev,
struct drm_crtc *crtc, struct drm_crtc *crtc,
struct intel_wm_config *config,
struct skl_wm_values *r) struct skl_wm_values *r)
{ {
struct intel_crtc *intel_crtc; struct intel_crtc *intel_crtc;
...@@ -3613,7 +3578,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev, ...@@ -3613,7 +3578,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
if (!intel_crtc->active) if (!intel_crtc->active)
continue; continue;
wm_changed = skl_update_pipe_wm(&intel_crtc->base, config, wm_changed = skl_update_pipe_wm(&intel_crtc->base,
&r->ddb, &pipe_wm); &r->ddb, &pipe_wm);
/* /*
...@@ -3656,7 +3621,6 @@ static void skl_update_wm(struct drm_crtc *crtc) ...@@ -3656,7 +3621,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
struct skl_wm_values *results = &dev_priv->wm.skl_results; struct skl_wm_values *results = &dev_priv->wm.skl_results;
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl; struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
struct intel_wm_config config = {};
/* Clear all dirty flags */ /* Clear all dirty flags */
...@@ -3664,15 +3628,13 @@ static void skl_update_wm(struct drm_crtc *crtc) ...@@ -3664,15 +3628,13 @@ static void skl_update_wm(struct drm_crtc *crtc)
skl_clear_wm(results, intel_crtc->pipe); skl_clear_wm(results, intel_crtc->pipe);
skl_compute_wm_global_parameters(dev, &config); if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
if (!skl_update_pipe_wm(crtc, &config, &results->ddb, pipe_wm))
return; return;
skl_compute_wm_results(dev, pipe_wm, results, intel_crtc); skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
results->dirty[intel_crtc->pipe] = true; results->dirty[intel_crtc->pipe] = true;
skl_update_other_pipe_wm(dev, crtc, &config, results); skl_update_other_pipe_wm(dev, crtc, results);
skl_write_wm_values(dev_priv, results); skl_write_wm_values(dev_priv, results);
skl_flush_wm_values(dev_priv, results); skl_flush_wm_values(dev_priv, results);
...@@ -3685,20 +3647,18 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ...@@ -3685,20 +3647,18 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
struct drm_device *dev = dev_priv->dev; struct drm_device *dev = dev_priv->dev;
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max; struct ilk_wm_maximums max;
struct intel_wm_config config = {}; struct intel_wm_config *config = &dev_priv->wm.config;
struct ilk_wm_values results = {}; struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning; enum intel_ddb_partitioning partitioning;
ilk_compute_wm_config(dev, &config); ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
/* 5/6 split only in single pipe config on IVB+ */ /* 5/6 split only in single pipe config on IVB+ */
if (INTEL_INFO(dev)->gen >= 7 && if (INTEL_INFO(dev)->gen >= 7 &&
config.num_pipes_active == 1 && config.sprites_enabled) { config->num_pipes_active == 1 && config->sprites_enabled) {
ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
} else { } else {
......
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