Commit 76c9dd9d authored by David Lechner's avatar David Lechner Committed by Michael Turquette

clk: davinci: pll: allow dev == NULL

This modifies the TI Davinci PLL clock driver to allow for the case
when dev == NULL. On some (most) SoCs that use this driver, the PLL
clock needs to be registered during early boot because it is used
for clocksource/clkevent and there will be no platform device available.
Signed-off-by: default avatarDavid Lechner <david@lechnology.com>
Reviewed-by: default avatarSekhar Nori <nsekhar@ti.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
parent 9c39fc1f
......@@ -6,6 +6,7 @@
*/
#include <linux/clkdev.h>
#include <linux/clk/davinci.h>
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/types.h>
......@@ -36,11 +37,11 @@ SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
int da830_pll_init(struct device *dev, void __iomem *base)
int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base);
davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
......
......@@ -7,7 +7,9 @@
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/da8xx-cfgchip.h>
......@@ -81,11 +83,11 @@ static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
.ocsrc_mask = GENMASK(4, 0),
};
int da850_pll0_init(struct device *dev, void __iomem *base)
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base);
davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);
clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
......@@ -134,11 +136,11 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
NULL
};
int of_da850_pll0_init(struct device *dev, void __iomem *base)
int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
return of_davinci_pll_init(dev, &da850_pll0_info,
return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info,
&da850_pll0_obsclk_info,
da850_pll0_sysclk_info, 7, base);
da850_pll0_sysclk_info, 7, base, cfgchip);
}
static const struct davinci_pll_clk_info da850_pll1_info = {
......@@ -179,11 +181,11 @@ static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
.ocsrc_mask = GENMASK(4, 0),
};
int da850_pll1_init(struct device *dev, void __iomem *base)
int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base);
davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
......@@ -204,9 +206,9 @@ static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
NULL
};
int of_da850_pll1_init(struct device *dev, void __iomem *base)
int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
return of_davinci_pll_init(dev, &da850_pll1_info,
return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
&da850_pll1_obsclk_info,
da850_pll1_sysclk_info, 3, base);
da850_pll1_sysclk_info, 3, base, cfgchip);
}
......@@ -6,6 +6,7 @@
*/
#include <linux/bitops.h>
#include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/types.h>
......@@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED)
SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
int dm355_pll1_init(struct device *dev, void __iomem *base)
int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base);
davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
......@@ -64,9 +65,9 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
int dm355_pll2_init(struct device *dev, void __iomem *base)
int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base);
davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
......
......@@ -7,6 +7,7 @@
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <linux/clk/davinci.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
......@@ -56,11 +57,11 @@ static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
.ocsrc_mask = BIT(4),
};
int dm365_pll1_init(struct device *dev, void __iomem *base)
int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base);
davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
......@@ -119,11 +120,11 @@ static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
.ocsrc_mask = BIT(4),
};
int dm365_pll2_init(struct device *dev, void __iomem *base)
int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base);
davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
......
......@@ -6,6 +6,7 @@
*/
#include <linux/bitops.h>
#include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/types.h>
......@@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
int dm644x_pll1_init(struct device *dev, void __iomem *base)
int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base);
davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
......@@ -66,9 +67,9 @@ static const struct davinci_pll_clk_info dm644x_pll2_info = {
SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
int dm644x_pll2_init(struct device *dev, void __iomem *base)
int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base);
davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
......
......@@ -6,6 +6,7 @@
*/
#include <linux/clk-provider.h>
#include <linux/clk/davinci.h>
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/types.h>
......@@ -29,11 +30,11 @@ SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);
SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);
SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);
int dm646x_pll1_init(struct device *dev, void __iomem *base)
int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
struct clk *clk;
davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base);
davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip);
clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");
......@@ -74,9 +75,9 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
int dm646x_pll2_init(struct device *dev, void __iomem *base)
int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
{
davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base);
davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip);
davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
......
This diff is collapsed.
......@@ -11,6 +11,7 @@
#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/types.h>
#define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
......@@ -94,7 +95,8 @@ struct davinci_pll_obsclk_info {
struct clk *davinci_pll_clk_register(struct device *dev,
const struct davinci_pll_clk_info *info,
const char *parent_name,
void __iomem *base);
void __iomem *base,
struct regmap *cfgchip);
struct clk *davinci_pll_auxclk_register(struct device *dev,
const char *name,
void __iomem *base);
......@@ -110,32 +112,24 @@ davinci_pll_sysclk_register(struct device *dev,
const struct davinci_pll_sysclk_info *info,
void __iomem *base);
int of_davinci_pll_init(struct device *dev,
int of_davinci_pll_init(struct device *dev, struct device_node *node,
const struct davinci_pll_clk_info *info,
const struct davinci_pll_obsclk_info *obsclk_info,
const struct davinci_pll_sysclk_info **div_info,
u8 max_sysclk_id,
void __iomem *base);
void __iomem *base,
struct regmap *cfgchip);
/* Platform-specific callbacks */
int da830_pll_init(struct device *dev, void __iomem *base);
int da850_pll0_init(struct device *dev, void __iomem *base);
int da850_pll1_init(struct device *dev, void __iomem *base);
int of_da850_pll0_init(struct device *dev, void __iomem *base);
int of_da850_pll1_init(struct device *dev, void __iomem *base);
int dm355_pll1_init(struct device *dev, void __iomem *base);
int dm355_pll2_init(struct device *dev, void __iomem *base);
int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm365_pll1_init(struct device *dev, void __iomem *base);
int dm365_pll2_init(struct device *dev, void __iomem *base);
int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm644x_pll1_init(struct device *dev, void __iomem *base);
int dm644x_pll2_init(struct device *dev, void __iomem *base);
int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm646x_pll1_init(struct device *dev, void __iomem *base);
int dm646x_pll2_init(struct device *dev, void __iomem *base);
int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
#endif /* __CLK_DAVINCI_PLL_H___ */
// SPDX-License-Identifier: GPL-2.0
/*
* Clock drivers for TI DaVinci PLL and PSC controllers
*
* Copyright (C) 2018 David Lechner <david@lechnology.com>
*/
#ifndef __LINUX_CLK_DAVINCI_PLL_H___
#define __LINUX_CLK_DAVINCI_PLL_H___
#include <linux/device.h>
#include <linux/regmap.h>
/* function for registering clocks in early boot */
int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
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