Commit 7727eaa4 authored by Dave Jiang's avatar Dave Jiang Committed by Vinod Koul

ioatdma: Adding support for 16 src PQ ops and super extended descriptors

v3.3 introduced 16 sources PQ operations. This also introduced super extended
descriptors to support the 16 srcs operations. This patch adds support for
the 16 sources ops and in turn adds the super extended descriptors for those
ops.

5 SED pools are created depending on the descriptor sizes. An SED can be a 64
bytes sized descriptor or larger and must be physically contiguous. A kmem
cache pool is created for allocating the software descriptor that manages the
hardware descriptor. The super extended descriptor will take place of extended
descriptor under certain operations and be "attached" to the op descriptor
during operation. This is a new feature for ioatdma v3.3.
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Acked-by: default avatarDan Williams <djbw@fb.com>
Acked-by: default avatarDan Williams <djbw@fb.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent e0884772
...@@ -81,6 +81,9 @@ struct ioatdma_device { ...@@ -81,6 +81,9 @@ struct ioatdma_device {
void __iomem *reg_base; void __iomem *reg_base;
struct pci_pool *dma_pool; struct pci_pool *dma_pool;
struct pci_pool *completion_pool; struct pci_pool *completion_pool;
#define MAX_SED_POOLS 5
struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
struct kmem_cache *sed_pool;
struct dma_device common; struct dma_device common;
u8 version; u8 version;
struct msix_entry msix_entries[4]; struct msix_entry msix_entries[4];
...@@ -141,6 +144,20 @@ struct ioat_dma_chan { ...@@ -141,6 +144,20 @@ struct ioat_dma_chan {
u16 active; u16 active;
}; };
/**
* struct ioat_sed_ent - wrapper around super extended hardware descriptor
* @hw: hardware SED
* @sed_dma: dma address for the SED
* @list: list member
* @parent: point to the dma descriptor that's the parent
*/
struct ioat_sed_ent {
struct ioat_sed_raw_descriptor *hw;
dma_addr_t dma;
struct ioat_ring_ent *parent;
unsigned int hw_pool;
};
static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c) static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
{ {
return container_of(c, struct ioat_chan_common, common); return container_of(c, struct ioat_chan_common, common);
......
...@@ -137,6 +137,7 @@ struct ioat_ring_ent { ...@@ -137,6 +137,7 @@ struct ioat_ring_ent {
#ifdef DEBUG #ifdef DEBUG
int id; int id;
#endif #endif
struct ioat_sed_ent *sed;
}; };
static inline struct ioat_ring_ent * static inline struct ioat_ring_ent *
...@@ -157,6 +158,7 @@ static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr) ...@@ -157,6 +158,7 @@ static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
int ioat2_dma_probe(struct ioatdma_device *dev, int dca); int ioat2_dma_probe(struct ioatdma_device *dev, int dca);
int ioat3_dma_probe(struct ioatdma_device *dev, int dca); int ioat3_dma_probe(struct ioatdma_device *dev, int dca);
void ioat3_dma_remove(struct ioatdma_device *dev);
struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs); int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs);
......
This diff is collapsed.
...@@ -183,6 +183,8 @@ struct ioat_pq_descriptor { ...@@ -183,6 +183,8 @@ struct ioat_pq_descriptor {
unsigned int rsvd:11; unsigned int rsvd:11;
#define IOAT_OP_PQ 0x89 #define IOAT_OP_PQ 0x89
#define IOAT_OP_PQ_VAL 0x8a #define IOAT_OP_PQ_VAL 0x8a
#define IOAT_OP_PQ_16S 0xa0
#define IOAT_OP_PQ_VAL_16S 0xa1
unsigned int op:8; unsigned int op:8;
} ctl_f; } ctl_f;
}; };
...@@ -190,7 +192,10 @@ struct ioat_pq_descriptor { ...@@ -190,7 +192,10 @@ struct ioat_pq_descriptor {
uint64_t p_addr; uint64_t p_addr;
uint64_t next; uint64_t next;
uint64_t src_addr2; uint64_t src_addr2;
union {
uint64_t src_addr3; uint64_t src_addr3;
uint64_t sed_addr;
};
uint8_t coef[8]; uint8_t coef[8];
uint64_t q_addr; uint64_t q_addr;
}; };
...@@ -239,4 +244,40 @@ struct ioat_pq_update_descriptor { ...@@ -239,4 +244,40 @@ struct ioat_pq_update_descriptor {
struct ioat_raw_descriptor { struct ioat_raw_descriptor {
uint64_t field[8]; uint64_t field[8];
}; };
struct ioat_pq16a_descriptor {
uint8_t coef[8];
uint64_t src_addr3;
uint64_t src_addr4;
uint64_t src_addr5;
uint64_t src_addr6;
uint64_t src_addr7;
uint64_t src_addr8;
uint64_t src_addr9;
};
struct ioat_pq16b_descriptor {
uint64_t src_addr10;
uint64_t src_addr11;
uint64_t src_addr12;
uint64_t src_addr13;
uint64_t src_addr14;
uint64_t src_addr15;
uint64_t src_addr16;
uint64_t rsvd;
};
union ioat_sed_pq_descriptor {
struct ioat_pq16a_descriptor a;
struct ioat_pq16b_descriptor b;
};
#define SED_SIZE 64
struct ioat_sed_raw_descriptor {
uint64_t a[8];
uint64_t b[8];
uint64_t c[8];
};
#endif #endif
...@@ -207,6 +207,9 @@ static void ioat_remove(struct pci_dev *pdev) ...@@ -207,6 +207,9 @@ static void ioat_remove(struct pci_dev *pdev)
if (!device) if (!device)
return; return;
if (device->version >= IOAT_VER_3_0)
ioat3_dma_remove(device);
dev_err(&pdev->dev, "Removing dma and dca services\n"); dev_err(&pdev->dev, "Removing dma and dca services\n");
if (device->dca) { if (device->dca) {
unregister_dca_provider(device->dca, &pdev->dev); unregister_dca_provider(device->dca, &pdev->dev);
......
...@@ -79,6 +79,7 @@ ...@@ -79,6 +79,7 @@
#define IOAT_CAP_APIC 0x00000080 #define IOAT_CAP_APIC 0x00000080
#define IOAT_CAP_XOR 0x00000100 #define IOAT_CAP_XOR 0x00000100
#define IOAT_CAP_PQ 0x00000200 #define IOAT_CAP_PQ 0x00000200
#define IOAT_CAP_RAID16SS 0x00020000
#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
......
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