Commit 77f71730 authored by Mikko Perttunen's avatar Mikko Perttunen Committed by Peter De Schrijver

clk: tegra114: Initialize clocks needed for HDMI

Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 61792e40
...@@ -1294,6 +1294,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { ...@@ -1294,6 +1294,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
{TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
......
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