Commit 797ea240 authored by Stanislaw Gruszka's avatar Stanislaw Gruszka Committed by Kalle Valo

mt76: merge mt76x0/regs.h into mt76x02_regs.h

Add missed definitions for mt76x0 into mt76x02_regs.h. Remove
mt76x0/regs.h and fixup mt76x0 code to adjust to some diffrent
registers/fields names.
Signed-off-by: default avatarStanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent 89e1b1bc
...@@ -127,9 +127,9 @@ static void mt76x0_init_usb_dma(struct mt76x0_dev *dev) ...@@ -127,9 +127,9 @@ static void mt76x0_init_usb_dma(struct mt76x0_dev *dev)
val = mt76_rr(dev, MT_USB_DMA_CFG); val = mt76_rr(dev, MT_USB_DMA_CFG);
val |= MT_USB_DMA_CFG_RX_DROP_OR_PADDING; val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD;
mt76_wr(dev, MT_USB_DMA_CFG, val); mt76_wr(dev, MT_USB_DMA_CFG, val);
val &= ~MT_USB_DMA_CFG_RX_DROP_OR_PADDING; val &= ~MT_USB_DMA_CFG_RX_DROP_OR_PAD;
mt76_wr(dev, MT_USB_DMA_CFG, val); mt76_wr(dev, MT_USB_DMA_CFG, val);
} }
...@@ -274,12 +274,12 @@ static int mt76x0_init_wcid_attr_mem(struct mt76x0_dev *dev) ...@@ -274,12 +274,12 @@ static int mt76x0_init_wcid_attr_mem(struct mt76x0_dev *dev)
static void mt76x0_reset_counters(struct mt76x0_dev *dev) static void mt76x0_reset_counters(struct mt76x0_dev *dev)
{ {
mt76_rr(dev, MT_RX_STA_CNT0); mt76_rr(dev, MT_RX_STAT_0);
mt76_rr(dev, MT_RX_STA_CNT1); mt76_rr(dev, MT_RX_STAT_1);
mt76_rr(dev, MT_RX_STA_CNT2); mt76_rr(dev, MT_RX_STAT_2);
mt76_rr(dev, MT_TX_STA_CNT0); mt76_rr(dev, MT_TX_STA_0);
mt76_rr(dev, MT_TX_STA_CNT1); mt76_rr(dev, MT_TX_STA_1);
mt76_rr(dev, MT_TX_STA_CNT2); mt76_rr(dev, MT_TX_STA_2);
} }
int mt76x0_mac_start(struct mt76x0_dev *dev) int mt76x0_mac_start(struct mt76x0_dev *dev)
......
...@@ -355,8 +355,8 @@ void mt76x0_mac_work(struct work_struct *work) ...@@ -355,8 +355,8 @@ void mt76x0_mac_work(struct work_struct *work)
u32 span; u32 span;
u64 *stat_base; u64 *stat_base;
} spans[] = { } spans[] = {
{ MT_RX_STA_CNT0, 3, dev->stats.rx_stat }, { MT_RX_STAT_0, 3, dev->stats.rx_stat },
{ MT_TX_STA_CNT0, 3, dev->stats.tx_stat }, { MT_TX_STA_0, 3, dev->stats.tx_stat },
{ MT_TX_AGG_STAT, 1, dev->stats.aggr_stat }, { MT_TX_AGG_STAT, 1, dev->stats.aggr_stat },
{ MT_MPDU_DENSITY_CNT, 1, dev->stats.zero_len_del }, { MT_MPDU_DENSITY_CNT, 1, dev->stats.zero_len_del },
{ MT_TX_AGG_CNT_BASE0, 8, &dev->stats.aggr_n[0] }, { MT_TX_AGG_CNT_BASE0, 8, &dev->stats.aggr_n[0] },
...@@ -566,7 +566,7 @@ u32 mt76x0_mac_process_rx(struct mt76x0_dev *dev, struct sk_buff *skb, ...@@ -566,7 +566,7 @@ u32 mt76x0_mac_process_rx(struct mt76x0_dev *dev, struct sk_buff *skb,
return len; return len;
} }
static enum mt76_cipher_type static enum mt76x02_cipher_type
mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
{ {
memset(key_data, 0, 32); memset(key_data, 0, 32);
...@@ -595,7 +595,7 @@ mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) ...@@ -595,7 +595,7 @@ mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
int mt76x0_mac_wcid_set_key(struct mt76x0_dev *dev, u8 idx, int mt76x0_mac_wcid_set_key(struct mt76x0_dev *dev, u8 idx,
struct ieee80211_key_conf *key) struct ieee80211_key_conf *key)
{ {
enum mt76_cipher_type cipher; enum mt76x02_cipher_type cipher;
u8 key_data[32]; u8 key_data[32];
u8 iv_data[8]; u8 iv_data[8];
u32 val; u32 val;
...@@ -636,7 +636,7 @@ int mt76x0_mac_wcid_set_key(struct mt76x0_dev *dev, u8 idx, ...@@ -636,7 +636,7 @@ int mt76x0_mac_wcid_set_key(struct mt76x0_dev *dev, u8 idx,
int mt76x0_mac_shared_key_setup(struct mt76x0_dev *dev, u8 vif_idx, u8 key_idx, int mt76x0_mac_shared_key_setup(struct mt76x0_dev *dev, u8 vif_idx, u8 key_idx,
struct ieee80211_key_conf *key) struct ieee80211_key_conf *key)
{ {
enum mt76_cipher_type cipher; enum mt76x02_cipher_type cipher;
u8 key_data[32]; u8 key_data[32];
u32 val; u32 val;
......
...@@ -166,8 +166,8 @@ mt76x0_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ...@@ -166,8 +166,8 @@ mt76x0_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
if (changed & BSS_CHANGED_BASIC_RATES) { if (changed & BSS_CHANGED_BASIC_RATES) {
mt76_wr(dev, MT_LEGACY_BASIC_RATE, info->basic_rates); mt76_wr(dev, MT_LEGACY_BASIC_RATE, info->basic_rates);
mt76_wr(dev, MT_HT_FBK_CFG0, 0x65432100); mt76_wr(dev, MT_VHT_HT_FBK_CFG0, 0x65432100);
mt76_wr(dev, MT_HT_FBK_CFG1, 0xedcba980); mt76_wr(dev, MT_VHT_HT_FBK_CFG1, 0xedcba980);
mt76_wr(dev, MT_LG_FBK_CFG0, 0xedcba988); mt76_wr(dev, MT_LG_FBK_CFG0, 0xedcba988);
mt76_wr(dev, MT_LG_FBK_CFG1, 0x00002100); mt76_wr(dev, MT_LG_FBK_CFG1, 0x00002100);
} }
......
...@@ -591,9 +591,9 @@ static int mt76x0_load_firmware(struct mt76x0_dev *dev) ...@@ -591,9 +591,9 @@ static int mt76x0_load_firmware(struct mt76x0_dev *dev)
mt76_wr(dev, MT_FCE_SKIP_FS, 3); mt76_wr(dev, MT_FCE_SKIP_FS, 3);
val = mt76_rr(dev, MT_USB_DMA_CFG); val = mt76_rr(dev, MT_USB_DMA_CFG);
val |= MT_USB_DMA_CFG_TX_WL_DROP; val |= MT_USB_DMA_CFG_UDMA_TX_WL_DROP;
mt76_wr(dev, MT_USB_DMA_CFG, val); mt76_wr(dev, MT_USB_DMA_CFG, val);
val &= ~MT_USB_DMA_CFG_TX_WL_DROP; val &= ~MT_USB_DMA_CFG_UDMA_TX_WL_DROP;
mt76_wr(dev, MT_USB_DMA_CFG, val); mt76_wr(dev, MT_USB_DMA_CFG, val);
ret = mt76x0_upload_firmware(dev, (const struct mt76_fw *)fw->data); ret = mt76x0_upload_firmware(dev, (const struct mt76_fw *)fw->data);
......
...@@ -26,8 +26,8 @@ ...@@ -26,8 +26,8 @@
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include "../mt76.h" #include "../mt76.h"
#include "../mt76x02_regs.h"
#include "../mt76x02_mac.h" #include "../mt76x02_mac.h"
#include "regs.h"
#define MT_CALIBRATE_INTERVAL (4 * HZ) #define MT_CALIBRATE_INTERVAL (4 * HZ)
......
This diff is collapsed.
...@@ -46,6 +46,11 @@ ...@@ -46,6 +46,11 @@
#define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
#define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
#define MT_COEXCFG3 0x004c
#define MT_LDO_CTRL_0 0x006c
#define MT_LDO_CTRL_1 0x0070
#define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
#define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */
...@@ -75,6 +80,8 @@ ...@@ -75,6 +80,8 @@
#define MT_XO_CTRL7 0x011c #define MT_XO_CTRL7 0x011c
#define MT_IOCFG_6 0x0124
#define MT_USB_U3DMA_CFG 0x9018 #define MT_USB_U3DMA_CFG 0x9018
#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0) #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8) #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
...@@ -156,18 +163,23 @@ ...@@ -156,18 +163,23 @@
#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16) #define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16)
#define MT_WMM_TXOP_MASK GENMASK(15, 0) #define MT_WMM_TXOP_MASK GENMASK(15, 0)
#define MT_WMM_CTRL 0x0230 /* MT76x0 */
#define MT_FCE_DMA_ADDR 0x0230
#define MT_FCE_DMA_LEN 0x0234
#define MT_USB_DMA_CFG 0x0238
#define MT_TSO_CTRL 0x0250 #define MT_TSO_CTRL 0x0250
#define MT_HEADER_TRANS_CTRL_REG 0x0260 #define MT_HEADER_TRANS_CTRL_REG 0x0260
#define MT_US_CYC_CFG 0x02a4
#define MT_US_CYC_CNT GENMASK(7, 0)
#define MT_TX_RING_BASE 0x0300 #define MT_TX_RING_BASE 0x0300
#define MT_RX_RING_BASE 0x03c0 #define MT_RX_RING_BASE 0x03c0
#define MT_TX_HW_QUEUE_MCU 8 #define MT_TX_HW_QUEUE_MCU 8
#define MT_TX_HW_QUEUE_MGMT 9 #define MT_TX_HW_QUEUE_MGMT 9
#define MT_US_CYC_CFG 0x02a4
#define MT_US_CYC_CNT GENMASK(7, 0)
#define MT_PBF_SYS_CTRL 0x0400 #define MT_PBF_SYS_CTRL 0x0400
#define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
#define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)
...@@ -189,10 +201,20 @@ ...@@ -189,10 +201,20 @@
#define MT_BCN_OFFSET_BASE 0x041c #define MT_BCN_OFFSET_BASE 0x041c
#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2)) #define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))
#define MT_RXQ_STA 0x0430
#define MT_TXQ_STA 0x0434
#define MT_RF_CSR_CFG 0x0500
#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)
#define MT_RF_CSR_CFG_WR BIT(30)
#define MT_RF_CSR_CFG_KICK BIT(31)
#define MT_RF_BYPASS_0 0x0504 #define MT_RF_BYPASS_0 0x0504
#define MT_RF_BYPASS_1 0x0508 #define MT_RF_BYPASS_1 0x0508
#define MT_RF_SETTING_0 0x050c #define MT_RF_SETTING_0 0x050c
#define MT_RF_MISC 0x0518
#define MT_RF_DATA_WRITE 0x0524 #define MT_RF_DATA_WRITE 0x0524
#define MT_RF_CTRL 0x0528 #define MT_RF_CTRL 0x0528
...@@ -203,6 +225,11 @@ ...@@ -203,6 +225,11 @@
#define MT_RF_DATA_READ 0x052c #define MT_RF_DATA_READ 0x052c
#define MT_COM_REG0 0x0730
#define MT_COM_REG1 0x0734
#define MT_COM_REG2 0x0738
#define MT_COM_REG3 0x073C
#define MT_FCE_PSE_CTRL 0x0800 #define MT_FCE_PSE_CTRL 0x0800
#define MT_FCE_PARAMETERS 0x0804 #define MT_FCE_PARAMETERS 0x0804
#define MT_FCE_CSO 0x0808 #define MT_FCE_CSO 0x0808
...@@ -222,6 +249,7 @@ ...@@ -222,6 +249,7 @@
#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0 #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4 #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4 #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
#define MT_FCE_SKIP_FS 0x0a6c #define MT_FCE_SKIP_FS 0x0a6c
...@@ -250,6 +278,9 @@ ...@@ -250,6 +278,9 @@
#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24) #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
#define MT_MAX_LEN_CFG 0x1018 #define MT_MAX_LEN_CFG 0x1018
#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12)
#define MT_LED_CFG 0x102c
#define MT_AMPDU_MAX_LEN_20M1S 0x1030 #define MT_AMPDU_MAX_LEN_20M1S 0x1030
#define MT_AMPDU_MAX_LEN_20M2S 0x1034 #define MT_AMPDU_MAX_LEN_20M2S 0x1034
...@@ -365,6 +396,8 @@ ...@@ -365,6 +396,8 @@
#define MT_TX_SW_CFG2 0x1338 #define MT_TX_SW_CFG2 0x1338
#define MT_TXOP_CTRL_CFG 0x1340 #define MT_TXOP_CTRL_CFG 0x1340
#define MT_TXOP_TRUN_EN GENMASK(5, 0)
#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
#define MT_TX_RTS_CFG 0x1344 #define MT_TX_RTS_CFG 0x1344
#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0) #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
...@@ -376,7 +409,10 @@ ...@@ -376,7 +409,10 @@
#define MT_TX_RETRY_CFG 0x134c #define MT_TX_RETRY_CFG 0x134c
#define MT_TX_LINK_CFG 0x1350 #define MT_TX_LINK_CFG 0x1350
#define MT_VHT_HT_FBK_CFG0 0x1354
#define MT_VHT_HT_FBK_CFG1 0x1358 #define MT_VHT_HT_FBK_CFG1 0x1358
#define MT_LG_FBK_CFG0 0x135c
#define MT_LG_FBK_CFG1 0x1360
#define MT_PROT_CFG_RATE GENMASK(15, 0) #define MT_PROT_CFG_RATE GENMASK(15, 0)
#define MT_PROT_CFG_CTRL GENMASK(17, 16) #define MT_PROT_CFG_CTRL GENMASK(17, 16)
...@@ -391,6 +427,27 @@ ...@@ -391,6 +427,27 @@
#define MT_GF20_PROT_CFG 0x1374 #define MT_GF20_PROT_CFG 0x1374
#define MT_GF40_PROT_CFG 0x1378 #define MT_GF40_PROT_CFG 0x1378
#define MT_PROT_RATE GENMASK(15, 0)
#define MT_PROT_CTRL_RTS_CTS BIT(16)
#define MT_PROT_CTRL_CTS2SELF BIT(17)
#define MT_PROT_NAV_SHORT BIT(18)
#define MT_PROT_NAV_LONG BIT(19)
#define MT_PROT_TXOP_ALLOW_CCK BIT(20)
#define MT_PROT_TXOP_ALLOW_OFDM BIT(21)
#define MT_PROT_TXOP_ALLOW_MM20 BIT(22)
#define MT_PROT_TXOP_ALLOW_MM40 BIT(23)
#define MT_PROT_TXOP_ALLOW_GF20 BIT(24)
#define MT_PROT_TXOP_ALLOW_GF40 BIT(25)
#define MT_PROT_RTS_THR_EN BIT(26)
#define MT_PROT_RATE_CCK_11 0x0003
#define MT_PROT_RATE_OFDM_6 0x4000
#define MT_PROT_RATE_OFDM_24 0x4004
#define MT_PROT_RATE_DUP_OFDM_24 0x4084
#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20)
#define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \
~MT_PROT_TXOP_ALLOW_MM40 & \
~MT_PROT_TXOP_ALLOW_GF40)
#define MT_EXP_ACK_TIME 0x1380 #define MT_EXP_ACK_TIME 0x1380
#define MT_TX_PWR_CFG_0_EXT 0x1390 #define MT_TX_PWR_CFG_0_EXT 0x1390
...@@ -405,6 +462,8 @@ ...@@ -405,6 +462,8 @@
#define MT_TX0_RF_GAIN_CORR 0x13a0 #define MT_TX0_RF_GAIN_CORR 0x13a0
#define MT_TX1_RF_GAIN_CORR 0x13a4 #define MT_TX1_RF_GAIN_CORR 0x13a4
#define MT_TX0_RF_GAIN_ATTEN 0x13a8
#define MT_TX0_RF_GAIN_ATTEN 0x13a8 /* MT76x0 */
#define MT_TX_ALC_CFG_0 0x13b0 #define MT_TX_ALC_CFG_0 0x13b0
#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0) #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
...@@ -421,6 +480,7 @@ ...@@ -421,6 +480,7 @@
#define MT_TX_ALC_CFG_3 0x13ac #define MT_TX_ALC_CFG_3 0x13ac
#define MT_TX_ALC_CFG_4 0x13c0 #define MT_TX_ALC_CFG_4 0x13c0
#define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31) #define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31)
#define MT_TX0_BB_GAIN_ATTEN 0x13c0 /* MT76x0 */
#define MT_TX_ALC_VGA3 0x13c8 #define MT_TX_ALC_VGA3 0x13c8
...@@ -451,10 +511,13 @@ ...@@ -451,10 +511,13 @@
#define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)
#define MT_AUTO_RSP_CFG 0x1404 #define MT_AUTO_RSP_CFG 0x1404
#define MT_AUTO_RSP_PREAMB_SHORT BIT(4)
#define MT_LEGACY_BASIC_RATE 0x1408 #define MT_LEGACY_BASIC_RATE 0x1408
#define MT_HT_BASIC_RATE 0x140c #define MT_HT_BASIC_RATE 0x140c
#define MT_HT_CTRL_CFG 0x1410 #define MT_HT_CTRL_CFG 0x1410
#define MT_RX_PARSER_CFG 0x1418
#define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)
#define MT_EXT_CCA_CFG 0x141c #define MT_EXT_CCA_CFG 0x141c
#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0) #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
...@@ -498,7 +561,10 @@ ...@@ -498,7 +561,10 @@
#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8) #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16) #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
#define MT_TX_AGG_STAT 0x171c
#define MT_TX_AGG_CNT_BASE0 0x1720 #define MT_TX_AGG_CNT_BASE0 0x1720
#define MT_MPDU_DENSITY_CNT 0x1740
#define MT_TX_AGG_CNT_BASE1 0x174c #define MT_TX_AGG_CNT_BASE1 0x174c
#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \ #define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
...@@ -604,7 +670,7 @@ struct mt76_wcid_key { ...@@ -604,7 +670,7 @@ struct mt76_wcid_key {
u8 rx_mic[8]; u8 rx_mic[8];
} __packed __aligned(4); } __packed __aligned(4);
enum mt76x2_cipher_type { enum mt76x02_cipher_type {
MT_CIPHER_NONE, MT_CIPHER_NONE,
MT_CIPHER_WEP40, MT_CIPHER_WEP40,
MT_CIPHER_WEP104, MT_CIPHER_WEP104,
......
...@@ -229,7 +229,7 @@ void mt76x2_send_tx_status(struct mt76x2_dev *dev, ...@@ -229,7 +229,7 @@ void mt76x2_send_tx_status(struct mt76x2_dev *dev,
} }
EXPORT_SYMBOL_GPL(mt76x2_send_tx_status); EXPORT_SYMBOL_GPL(mt76x2_send_tx_status);
static enum mt76x2_cipher_type static enum mt76x02_cipher_type
mt76x2_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) mt76x2_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
{ {
memset(key_data, 0, 32); memset(key_data, 0, 32);
...@@ -258,7 +258,7 @@ mt76x2_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) ...@@ -258,7 +258,7 @@ mt76x2_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
int mt76x2_mac_shared_key_setup(struct mt76x2_dev *dev, u8 vif_idx, u8 key_idx, int mt76x2_mac_shared_key_setup(struct mt76x2_dev *dev, u8 vif_idx, u8 key_idx,
struct ieee80211_key_conf *key) struct ieee80211_key_conf *key)
{ {
enum mt76x2_cipher_type cipher; enum mt76x02_cipher_type cipher;
u8 key_data[32]; u8 key_data[32];
u32 val; u32 val;
...@@ -281,7 +281,7 @@ EXPORT_SYMBOL_GPL(mt76x2_mac_shared_key_setup); ...@@ -281,7 +281,7 @@ EXPORT_SYMBOL_GPL(mt76x2_mac_shared_key_setup);
int mt76x2_mac_wcid_set_key(struct mt76x2_dev *dev, u8 idx, int mt76x2_mac_wcid_set_key(struct mt76x2_dev *dev, u8 idx,
struct ieee80211_key_conf *key) struct ieee80211_key_conf *key)
{ {
enum mt76x2_cipher_type cipher; enum mt76x02_cipher_type cipher;
u8 key_data[32]; u8 key_data[32];
u8 iv_data[8]; u8 iv_data[8];
......
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