Commit 79d94306 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Enable HPLL watermarks on g4x

I don't see why we couldn't use the HPLL watermarks on g4x. So let's
enable them. Let's assume a 35 usec memory latency for the HPLL mode.
That's roughly what PNV uses.

Based on the behaviour of the ELK box I have 35 usec is probably
overkill. Actually all the current latency values used seem overkill as
I can reduce them pretty drastically before I start to see underruns.
But let's play things a bit safe for now.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170421181432.15216-14-ville.syrjala@linux.intel.comReviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent 04548cba
...@@ -1020,8 +1020,9 @@ static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv) ...@@ -1020,8 +1020,9 @@ static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
/* all latencies in usec */ /* all latencies in usec */
dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
dev_priv->wm.max_level = G4X_WM_LEVEL_SR; dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
} }
static int g4x_plane_fifo_size(enum plane_id plane_id, int level) static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment